2012-12-12 05:25:42 +08:00
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//===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2012-12-12 05:25:42 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
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/// \brief Implementation of the TargetInstrInfo class that is common to all
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2012-12-12 05:25:42 +08:00
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/// AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPUTargetMachine.h"
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AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
Summary:
MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction
and register defintions, which are huge so we only want to include
them where needed.
This will also make it easier if we want to split the R600 and GCN
definitions into separate tablegenerated files.
I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h
because it uses some enums from the header to initialize default values
for the SIMachineFunction class, so I ended up having to remove includes of
SIMachineFunctionInfo.h from headers too.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46272
llvm-svn: 332930
2018-05-22 10:03:23 +08:00
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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2012-12-12 05:25:42 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2014-04-22 10:03:14 +08:00
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using namespace llvm;
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2013-11-19 08:57:56 +08:00
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// Pin the vtable to this file.
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AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
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//void AMDGPUInstrInfo::anchor() {}
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2016-06-24 14:30:11 +08:00
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2018-07-12 04:59:01 +08:00
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AMDGPUInstrInfo::AMDGPUInstrInfo(const GCNSubtarget &ST) { }
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2016-06-24 14:30:11 +08:00
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2018-02-10 00:57:48 +08:00
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// TODO: Should largely merge with AMDGPUTTIImpl::isSourceOfDivergence.
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bool AMDGPUInstrInfo::isUniformMMO(const MachineMemOperand *MMO) {
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const Value *Ptr = MMO->getValue();
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// UndefValue means this is a load of a kernel input. These are uniform.
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// Sometimes LDS instructions have constant pointers.
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// If Ptr is null, then that means this mem operand contains a
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// PseudoSourceValue like GOT.
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if (!Ptr || isa<UndefValue>(Ptr) ||
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isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
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return true;
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2018-02-10 00:57:57 +08:00
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if (MMO->getAddrSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
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return true;
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2018-02-10 00:57:48 +08:00
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if (const Argument *Arg = dyn_cast<Argument>(Ptr))
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return AMDGPU::isArgPassedInSGPR(Arg);
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const Instruction *I = dyn_cast<Instruction>(Ptr);
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return I && I->getMetadata("amdgpu.uniform");
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}
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