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llvm-project/llvm/test/CodeGen/X86/shift-and.ll

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[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). llvm-svn: 55558
2008-08-30 10:03:58 +08:00
define i32 @t1(i32 %t, i32 %val) nounwind {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; X32-LABEL: t1:
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X32: # BB#0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shll %cl, %eax
; X32-NEXT: retl
;
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; X64-LABEL: t1:
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X64: # BB#0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; X64-NEXT: movl %edi, %ecx
; X64-NEXT: shll %cl, %esi
; X64-NEXT: movl %esi, %eax
; X64-NEXT: retq
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). llvm-svn: 55558
2008-08-30 10:03:58 +08:00
%shamt = and i32 %t, 31
%res = shl i32 %val, %shamt
ret i32 %res
}
X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63. llvm-svn: 148024
2012-01-12 20:41:34 +08:00
define i32 @t2(i32 %t, i32 %val) nounwind {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; X32-LABEL: t2:
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X32: # BB#0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shll %cl, %eax
; X32-NEXT: retl
;
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; X64-LABEL: t2:
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X64: # BB#0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; X64-NEXT: movl %edi, %ecx
; X64-NEXT: shll %cl, %esi
; X64-NEXT: movl %esi, %eax
; X64-NEXT: retq
X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63. llvm-svn: 148024
2012-01-12 20:41:34 +08:00
%shamt = and i32 %t, 63
%res = shl i32 %val, %shamt
ret i32 %res
}
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). llvm-svn: 55558
2008-08-30 10:03:58 +08:00
@X = internal global i16 0
X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63. llvm-svn: 148024
2012-01-12 20:41:34 +08:00
define void @t3(i16 %t) nounwind {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; X32-LABEL: t3:
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X32: # BB#0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X32-NEXT: sarw %cl, X
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; X32-NEXT: retl
;
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; X64-LABEL: t3:
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X64: # BB#0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; X64-NEXT: movl %edi, %ecx
; X64-NEXT: sarw %cl, {{.*}}(%rip)
; X64-NEXT: retq
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). llvm-svn: 55558
2008-08-30 10:03:58 +08:00
%shamt = and i16 %t, 31
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp = load i16, i16* @X
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). llvm-svn: 55558
2008-08-30 10:03:58 +08:00
%tmp1 = ashr i16 %tmp, %shamt
store i16 %tmp1, i16* @X
ret void
}
X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63. llvm-svn: 148024
2012-01-12 20:41:34 +08:00
define i64 @t4(i64 %t, i64 %val) nounwind {
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X32-LABEL: t4:
; X32: # BB#0:
; X32-NEXT: pushl %esi
; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl %esi, %edx
; X32-NEXT: shrl %cl, %edx
; X32-NEXT: shrdl %cl, %esi, %eax
; X32-NEXT: testb $32, %cl
; X32-NEXT: je .LBB3_2
; X32-NEXT: # BB#1:
; X32-NEXT: movl %edx, %eax
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: .LBB3_2:
; X32-NEXT: popl %esi
; X32-NEXT: retl
;
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; X64-LABEL: t4:
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X64: # BB#0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; X64-NEXT: movl %edi, %ecx
; X64-NEXT: shrq %cl, %rsi
; X64-NEXT: movq %rsi, %rax
; X64-NEXT: retq
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). llvm-svn: 55558
2008-08-30 10:03:58 +08:00
%shamt = and i64 %t, 63
%res = lshr i64 %val, %shamt
ret i64 %res
}
X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63. llvm-svn: 148024
2012-01-12 20:41:34 +08:00
define i64 @t5(i64 %t, i64 %val) nounwind {
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X32-LABEL: t5:
; X32: # BB#0:
; X32-NEXT: pushl %esi
; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl %esi, %edx
; X32-NEXT: shrl %cl, %edx
; X32-NEXT: shrdl %cl, %esi, %eax
; X32-NEXT: testb $32, %cl
; X32-NEXT: je .LBB4_2
; X32-NEXT: # BB#1:
; X32-NEXT: movl %edx, %eax
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: .LBB4_2:
; X32-NEXT: popl %esi
; X32-NEXT: retl
;
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; X64-LABEL: t5:
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X64: # BB#0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; X64-NEXT: movl %edi, %ecx
; X64-NEXT: shrq %cl, %rsi
; X64-NEXT: movq %rsi, %rax
; X64-NEXT: retq
X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63. llvm-svn: 148024
2012-01-12 20:41:34 +08:00
%shamt = and i64 %t, 191
%res = lshr i64 %val, %shamt
ret i64 %res
}
Add test case for r160387 llvm-svn: 160389
2012-07-18 03:40:05 +08:00
[X86] Add test case to demonstrate that we don't allow masks wider than 6 bits in the (shift x, (and y, mask)) patterns for the 64-bit memory form. We allow wider than 5 bits in the 16 and 32 bit store forms. And we allow wider than 6 bits on the 64-bit regsiter form.:w I'm assuming this was a mistake made back in r148024. llvm-svn: 308656
2017-07-21 03:29:56 +08:00
define void @t5ptr(i64 %t, i64* %ptr) nounwind {
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X32-LABEL: t5ptr:
; X32: # BB#0:
; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi
; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl (%eax), %edx
; X32-NEXT: movl 4(%eax), %edi
; X32-NEXT: movl %edi, %esi
; X32-NEXT: shrl %cl, %esi
; X32-NEXT: shrdl %cl, %edi, %edx
; X32-NEXT: testb $32, %cl
; X32-NEXT: je .LBB5_2
; X32-NEXT: # BB#1:
; X32-NEXT: movl %esi, %edx
; X32-NEXT: xorl %esi, %esi
; X32-NEXT: .LBB5_2:
; X32-NEXT: movl %esi, 4(%eax)
; X32-NEXT: movl %edx, (%eax)
; X32-NEXT: popl %esi
; X32-NEXT: popl %edi
; X32-NEXT: retl
;
[X86] Add test case to demonstrate that we don't allow masks wider than 6 bits in the (shift x, (and y, mask)) patterns for the 64-bit memory form. We allow wider than 5 bits in the 16 and 32 bit store forms. And we allow wider than 6 bits on the 64-bit regsiter form.:w I'm assuming this was a mistake made back in r148024. llvm-svn: 308656
2017-07-21 03:29:56 +08:00
; X64-LABEL: t5ptr:
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X64: # BB#0:
[X86] Add test case to demonstrate that we don't allow masks wider than 6 bits in the (shift x, (and y, mask)) patterns for the 64-bit memory form. We allow wider than 5 bits in the 16 and 32 bit store forms. And we allow wider than 6 bits on the 64-bit regsiter form.:w I'm assuming this was a mistake made back in r148024. llvm-svn: 308656
2017-07-21 03:29:56 +08:00
; X64-NEXT: movl %edi, %ecx
; X64-NEXT: shrq %cl, (%rsi)
; X64-NEXT: retq
%shamt = and i64 %t, 191
%tmp = load i64, i64* %ptr
%tmp1 = lshr i64 %tmp, %shamt
store i64 %tmp1, i64* %ptr
ret void
}
Add test case for r160387 llvm-svn: 160389
2012-07-18 03:40:05 +08:00
; rdar://11866926
define i64 @t6(i64 %key, i64* nocapture %val) nounwind {
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X32-LABEL: t6:
; X32: # BB#0:
; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shrdl $3, %eax, %esi
; X32-NEXT: movl %eax, %edi
; X32-NEXT: shrl $3, %edi
; X32-NEXT: movl (%ecx), %eax
; X32-NEXT: movl 4(%ecx), %edx
; X32-NEXT: addl $-1, %eax
; X32-NEXT: adcl $-1, %edx
; X32-NEXT: andl %esi, %eax
; X32-NEXT: andl %edi, %edx
; X32-NEXT: popl %esi
; X32-NEXT: popl %edi
; X32-NEXT: retl
;
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; X64-LABEL: t6:
[x86] remove over-specified platform from test config llvm-svn: 314027
2017-09-23 05:07:13 +08:00
; X64: # BB#0:
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
; X64-NEXT: shrq $3, %rdi
; X64-NEXT: movq (%rsi), %rax
; X64-NEXT: decq %rax
; X64-NEXT: andq %rdi, %rax
; X64-NEXT: retq
Add test case for r160387 llvm-svn: 160389
2012-07-18 03:40:05 +08:00
%shr = lshr i64 %key, 3
[X86] Regenerate shift-and.ll and shift-bmi2.ll using update_llc_test_checks.py. I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests. llvm-svn: 308589
2017-07-20 14:19:53 +08:00
%1 = load i64, i64* %val, align 8
%sub = add i64 %1, 2305843009213693951
Add test case for r160387 llvm-svn: 160389
2012-07-18 03:40:05 +08:00
%and = and i64 %sub, %shr
ret i64 %and
}