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llvm-project/llvm/test/CodeGen/X86/vector-merge-store-fp-const...

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[X86][SSE] Regenerate merge store tests llvm-svn: 305910
2017-06-21 21:46:42 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=DEFAULTCPU
; RUN: llc < %s -mcpu=x86-64 -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64CPU
DAGCombiner: Replace store of FP constant after attemping store merges If storing multiple FP constants, some subset of the stores would be replaced with integers due to visit order, so MergeConsecutiveStores would only partially merge these. llvm-svn: 248169
2015-09-21 23:59:46 +08:00
define void @merge_8_float_zero_stores(float* %ptr) {
[X86][SSE] Regenerate merge store tests llvm-svn: 305910
2017-06-21 21:46:42 +08:00
; DEFAULTCPU-LABEL: merge_8_float_zero_stores:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; DEFAULTCPU: # %bb.0:
[X86][SSE] Regenerate merge store tests llvm-svn: 305910
2017-06-21 21:46:42 +08:00
; DEFAULTCPU-NEXT: movq $0, (%rdi)
; DEFAULTCPU-NEXT: movq $0, 8(%rdi)
; DEFAULTCPU-NEXT: movq $0, 16(%rdi)
; DEFAULTCPU-NEXT: movq $0, 24(%rdi)
; DEFAULTCPU-NEXT: retq
;
; X64CPU-LABEL: merge_8_float_zero_stores:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64CPU: # %bb.0:
[X86][SSE] Regenerate merge store tests llvm-svn: 305910
2017-06-21 21:46:42 +08:00
; X64CPU-NEXT: xorps %xmm0, %xmm0
; X64CPU-NEXT: movups %xmm0, (%rdi)
; X64CPU-NEXT: movups %xmm0, 16(%rdi)
; X64CPU-NEXT: retq
DAGCombiner: Replace store of FP constant after attemping store merges If storing multiple FP constants, some subset of the stores would be replaced with integers due to visit order, so MergeConsecutiveStores would only partially merge these. llvm-svn: 248169
2015-09-21 23:59:46 +08:00
%idx0 = getelementptr float, float* %ptr, i64 0
%idx1 = getelementptr float, float* %ptr, i64 1
%idx2 = getelementptr float, float* %ptr, i64 2
%idx3 = getelementptr float, float* %ptr, i64 3
%idx4 = getelementptr float, float* %ptr, i64 4
%idx5 = getelementptr float, float* %ptr, i64 5
%idx6 = getelementptr float, float* %ptr, i64 6
%idx7 = getelementptr float, float* %ptr, i64 7
store float 0.0, float* %idx0, align 4
store float 0.0, float* %idx1, align 4
store float 0.0, float* %idx2, align 4
store float 0.0, float* %idx3, align 4
store float 0.0, float* %idx4, align 4
store float 0.0, float* %idx5, align 4
store float 0.0, float* %idx6, align 4
store float 0.0, float* %idx7, align 4
ret void
}