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llvm-project/llvm/test/CodeGen/X86/schedule-x86_32.ll

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[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=i686 | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=atom | FileCheck %s --check-prefix=CHECK --check-prefix=ATOM
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=slm | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=sandybridge | FileCheck %s --check-prefix=CHECK --check-prefix=SANDY
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=ivybridge | FileCheck %s --check-prefix=CHECK --check-prefix=SANDY
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=broadwell | FileCheck %s --check-prefix=CHECK --check-prefix=BROADWELL
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=SKYLAKE
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=skx | FileCheck %s --check-prefix=CHECK --check-prefix=SKX
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2
; RUN: llc < %s -mtriple=i686-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=ZNVER1
define i8 @test_aaa(i8 %a0) optsize {
; GENERIC-LABEL: test_aaa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; GENERIC-NEXT: movb {{[0-9]+}}(%esp), %al
; GENERIC-NEXT: #APP
; GENERIC-NEXT: aaa
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_aaa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ATOM: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ATOM-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [1:1.00]
; ATOM-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; ATOM-NEXT: aaa # sched: [13:6.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_aaa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SLM-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [3:1.00]
; SLM-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SLM-NEXT: aaa # sched: [100:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_aaa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SANDY-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SANDY-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SANDY-NEXT: aaa # sched: [100:0.33]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
;
; HASWELL-LABEL: test_aaa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; HASWELL-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; HASWELL-NEXT: aaa # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; HASWELL-NEXT: #NO_APP
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: retl # sched: [7:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
;
; BROADWELL-LABEL: test_aaa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BROADWELL-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; BROADWELL-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; BROADWELL-NEXT: aaa # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_aaa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKYLAKE-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SKYLAKE-NEXT: aaa # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_aaa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKX: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKX-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SKX-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SKX-NEXT: aaa # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_aaa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BTVER2-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:1.00]
; BTVER2-NEXT: #APP
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6) llvm-svn: 327632
2018-03-15 23:12:12 +08:00
; BTVER2-NEXT: aaa # sched: [100:0.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_aaa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ZNVER1-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]
; ZNVER1-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; ZNVER1-NEXT: aaa # sched: [100:?]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
%1 = tail call i8 asm "aaa", "=r,r"(i8 %a0) nounwind
ret i8 %1
}
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
define void @test_aad(i16 %a0) optsize {
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; GENERIC-LABEL: test_aad:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; GENERIC-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GENERIC-NEXT: #APP
; GENERIC-NEXT: aad
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; GENERIC-NEXT: aad $16
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_aad:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ATOM: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ATOM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [1:1.00]
; ATOM-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; ATOM-NEXT: aad # sched: [7:3.50]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; ATOM-NEXT: aad $16 # sched: [7:3.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_aad:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SLM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; SLM-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SLM-NEXT: aad # sched: [100:1.00]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; SLM-NEXT: aad $16 # sched: [100:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_aad:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SANDY-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SANDY-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SANDY-NEXT: aad # sched: [100:0.33]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; SANDY-NEXT: aad $16 # sched: [100:0.33]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
;
; HASWELL-LABEL: test_aad:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; HASWELL-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; HASWELL-NEXT: aad # sched: [100:0.25]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; HASWELL-NEXT: aad $16 # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; HASWELL-NEXT: #NO_APP
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: retl # sched: [7:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
;
; BROADWELL-LABEL: test_aad:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BROADWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; BROADWELL-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; BROADWELL-NEXT: aad # sched: [100:0.25]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; BROADWELL-NEXT: aad $16 # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_aad:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKYLAKE-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SKYLAKE-NEXT: aad # sched: [100:0.25]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; SKYLAKE-NEXT: aad $16 # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_aad:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKX: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKX-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKX-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SKX-NEXT: aad # sched: [100:0.25]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; SKX-NEXT: aad $16 # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_aad:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BTVER2-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; BTVER2-NEXT: #APP
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6) llvm-svn: 327632
2018-03-15 23:12:12 +08:00
; BTVER2-NEXT: aad # sched: [100:0.50]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; BTVER2-NEXT: aad $16 # sched: [100:0.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_aad:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; ZNVER1-NEXT: aad # sched: [100:?]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; ZNVER1-NEXT: aad $16 # sched: [100:?]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
tail call void asm "aad \0A\09 aad $1", "r,i"(i16 %a0, i16 16) nounwind
ret void
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
}
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
define void @test_aam(i8 %a0) optsize {
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; GENERIC-LABEL: test_aam:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; GENERIC-NEXT: movb {{[0-9]+}}(%esp), %al
; GENERIC-NEXT: #APP
; GENERIC-NEXT: aam
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; GENERIC-NEXT: aam $16
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_aam:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ATOM: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ATOM-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [1:1.00]
; ATOM-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; ATOM-NEXT: aam # sched: [21:10.50]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; ATOM-NEXT: aam $16 # sched: [21:10.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_aam:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SLM-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [3:1.00]
; SLM-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SLM-NEXT: aam # sched: [100:1.00]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; SLM-NEXT: aam $16 # sched: [100:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_aam:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SANDY-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SANDY-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SANDY-NEXT: aam # sched: [100:0.33]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; SANDY-NEXT: aam $16 # sched: [100:0.33]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
;
; HASWELL-LABEL: test_aam:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; HASWELL-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; HASWELL-NEXT: aam # sched: [100:0.25]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; HASWELL-NEXT: aam $16 # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; HASWELL-NEXT: #NO_APP
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: retl # sched: [7:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
;
; BROADWELL-LABEL: test_aam:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BROADWELL-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; BROADWELL-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; BROADWELL-NEXT: aam # sched: [100:0.25]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; BROADWELL-NEXT: aam $16 # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_aam:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKYLAKE-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SKYLAKE-NEXT: aam # sched: [100:0.25]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; SKYLAKE-NEXT: aam $16 # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_aam:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKX: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKX-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SKX-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SKX-NEXT: aam # sched: [100:0.25]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; SKX-NEXT: aam $16 # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_aam:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BTVER2-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:1.00]
; BTVER2-NEXT: #APP
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6) llvm-svn: 327632
2018-03-15 23:12:12 +08:00
; BTVER2-NEXT: aam # sched: [100:0.50]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; BTVER2-NEXT: aam $16 # sched: [100:0.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_aam:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ZNVER1-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]
; ZNVER1-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; ZNVER1-NEXT: aam # sched: [100:?]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; ZNVER1-NEXT: aam $16 # sched: [100:?]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
tail call void asm "aam \0A\09 aam $1", "r,i"(i8 %a0, i8 16) nounwind
ret void
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
}
define i8 @test_aas(i8 %a0) optsize {
; GENERIC-LABEL: test_aas:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; GENERIC-NEXT: movb {{[0-9]+}}(%esp), %al
; GENERIC-NEXT: #APP
; GENERIC-NEXT: aas
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_aas:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ATOM: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ATOM-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [1:1.00]
; ATOM-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; ATOM-NEXT: aas # sched: [13:6.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_aas:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SLM-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [3:1.00]
; SLM-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SLM-NEXT: aas # sched: [100:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_aas:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SANDY-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SANDY-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SANDY-NEXT: aas # sched: [100:0.33]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
;
; HASWELL-LABEL: test_aas:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; HASWELL-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; HASWELL-NEXT: aas # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; HASWELL-NEXT: #NO_APP
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: retl # sched: [7:1.00]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
;
; BROADWELL-LABEL: test_aas:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BROADWELL-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; BROADWELL-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; BROADWELL-NEXT: aas # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_aas:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKYLAKE-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SKYLAKE-NEXT: aas # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_aas:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKX: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKX-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SKX-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; SKX-NEXT: aas # sched: [100:0.25]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_aas:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BTVER2-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:1.00]
; BTVER2-NEXT: #APP
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6) llvm-svn: 327632
2018-03-15 23:12:12 +08:00
; BTVER2-NEXT: aas # sched: [100:0.50]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_aas:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ZNVER1-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]
; ZNVER1-NEXT: #APP
Add -print-schedule scheduling comments to inline asm. Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
2017-11-09 20:45:40 +08:00
; ZNVER1-NEXT: aas # sched: [100:?]
[X86] Add some initial scheduling tests for generic x86 instructions These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
2017-11-09 00:35:42 +08:00
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
%1 = tail call i8 asm "aas", "=r,r"(i8 %a0) nounwind
ret i8 %1
}
[X86] Added TODO list for missing generic x86 instruction scheduling tests. Not sure if we want to add the more exotic system instructions (IRET etc.) as well? llvm-svn: 317882
2017-11-10 20:04:39 +08:00
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
define void @test_arpl(i16 %a0, i16 *%a1) optsize {
; GENERIC-LABEL: test_arpl:
; GENERIC: # %bb.0:
; GENERIC-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GENERIC-NEXT: #APP
; GENERIC-NEXT: arpl %ax, (%ecx)
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_arpl:
; ATOM: # %bb.0:
; ATOM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [1:1.00]
; ATOM-NEXT: #APP
; ATOM-NEXT: arpl %ax, (%ecx) # sched: [23:11.50]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_arpl:
; SLM: # %bb.0:
; SLM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: arpl %ax, (%ecx) # sched: [100:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_arpl:
; SANDY: # %bb.0:
; SANDY-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SANDY-NEXT: #APP
; SANDY-NEXT: arpl %ax, (%ecx) # sched: [100:0.33]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
;
; HASWELL-LABEL: test_arpl:
; HASWELL: # %bb.0:
; HASWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; HASWELL-NEXT: #APP
; HASWELL-NEXT: arpl %ax, (%ecx) # sched: [100:0.25]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_arpl:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: arpl %ax, (%ecx) # sched: [100:0.25]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_arpl:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: arpl %ax, (%ecx) # sched: [100:0.25]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_arpl:
; SKX: # %bb.0:
; SKX-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: arpl %ax, (%ecx) # sched: [100:0.25]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_arpl:
; BTVER2: # %bb.0:
; BTVER2-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6) llvm-svn: 327632
2018-03-15 23:12:12 +08:00
; BTVER2-NEXT: arpl %ax, (%ecx) # sched: [100:0.50]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_arpl:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: arpl %ax, (%ecx) # sched: [100:?]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
call void asm sideeffect "arpl $0, $1", "r,*m"(i16 %a0, i16 *%a1)
ret void
}
define void @test_bound(i16 %a0, i16 *%a1, i32 %a2, i32 *%a3) optsize {
; GENERIC-LABEL: test_bound:
; GENERIC: # %bb.0:
; GENERIC-NEXT: pushl %esi
; GENERIC-NEXT: .cfi_def_cfa_offset 8
; GENERIC-NEXT: .cfi_offset %esi, -8
; GENERIC-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %edx
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %esi
; GENERIC-NEXT: #APP
[X86] Don't swap argument on BOUND instruction in at&t syntax. The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
2018-02-15 05:54:58 +08:00
; GENERIC-NEXT: bound %ax, (%esi)
; GENERIC-NEXT: bound %ecx, (%edx)
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: popl %esi
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; GENERIC-NEXT: .cfi_def_cfa_offset 4
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_bound:
; ATOM: # %bb.0:
; ATOM-NEXT: pushl %esi # sched: [1:1.00]
; ATOM-NEXT: .cfi_def_cfa_offset 8
; ATOM-NEXT: .cfi_offset %esi, -8
; ATOM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %esi # sched: [1:1.00]
; ATOM-NEXT: #APP
[X86] Don't swap argument on BOUND instruction in at&t syntax. The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
2018-02-15 05:54:58 +08:00
; ATOM-NEXT: bound %ax, (%esi) # sched: [11:5.50]
; ATOM-NEXT: bound %ecx, (%edx) # sched: [11:5.50]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: popl %esi # sched: [1:1.00]
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; ATOM-NEXT: .cfi_def_cfa_offset 4
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_bound:
; SLM: # %bb.0:
; SLM-NEXT: pushl %esi # sched: [1:1.00]
; SLM-NEXT: .cfi_def_cfa_offset 8
; SLM-NEXT: .cfi_offset %esi, -8
; SLM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [3:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %esi # sched: [3:1.00]
; SLM-NEXT: #APP
[X86] Don't swap argument on BOUND instruction in at&t syntax. The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
2018-02-15 05:54:58 +08:00
; SLM-NEXT: bound %ax, (%esi) # sched: [100:1.00]
; SLM-NEXT: bound %ecx, (%edx) # sched: [100:1.00]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; SLM-NEXT: #NO_APP
; SLM-NEXT: popl %esi # sched: [3:1.00]
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; SLM-NEXT: .cfi_def_cfa_offset 4
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_bound:
; SANDY: # %bb.0:
; SANDY-NEXT: pushl %esi # sched: [5:1.00]
; SANDY-NEXT: .cfi_def_cfa_offset 8
; SANDY-NEXT: .cfi_offset %esi, -8
; SANDY-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %esi # sched: [5:0.50]
; SANDY-NEXT: #APP
[X86] Don't swap argument on BOUND instruction in at&t syntax. The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
2018-02-15 05:54:58 +08:00
; SANDY-NEXT: bound %ax, (%esi) # sched: [100:0.33]
; SANDY-NEXT: bound %ecx, (%edx) # sched: [100:0.33]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; SANDY-NEXT: #NO_APP
; SANDY-NEXT: popl %esi # sched: [6:0.50]
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; SANDY-NEXT: .cfi_def_cfa_offset 4
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
;
; HASWELL-LABEL: test_bound:
; HASWELL: # %bb.0:
; HASWELL-NEXT: pushl %esi # sched: [2:1.00]
; HASWELL-NEXT: .cfi_def_cfa_offset 8
; HASWELL-NEXT: .cfi_offset %esi, -8
; HASWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %esi # sched: [5:0.50]
; HASWELL-NEXT: #APP
[X86] Don't swap argument on BOUND instruction in at&t syntax. The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
2018-02-15 05:54:58 +08:00
; HASWELL-NEXT: bound %ax, (%esi) # sched: [1:?]
; HASWELL-NEXT: bound %ecx, (%edx) # sched: [1:?]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: popl %esi # sched: [6:0.50]
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; HASWELL-NEXT: .cfi_def_cfa_offset 4
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_bound:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: pushl %esi # sched: [2:1.00]
; BROADWELL-NEXT: .cfi_def_cfa_offset 8
; BROADWELL-NEXT: .cfi_offset %esi, -8
; BROADWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %esi # sched: [5:0.50]
; BROADWELL-NEXT: #APP
[X86] Don't swap argument on BOUND instruction in at&t syntax. The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
2018-02-15 05:54:58 +08:00
; BROADWELL-NEXT: bound %ax, (%esi) # sched: [100:0.25]
; BROADWELL-NEXT: bound %ecx, (%edx) # sched: [100:0.25]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: popl %esi # sched: [6:0.50]
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; BROADWELL-NEXT: .cfi_def_cfa_offset 4
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_bound:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: pushl %esi # sched: [2:1.00]
; SKYLAKE-NEXT: .cfi_def_cfa_offset 8
; SKYLAKE-NEXT: .cfi_offset %esi, -8
; SKYLAKE-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %esi # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
[X86] Don't swap argument on BOUND instruction in at&t syntax. The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
2018-02-15 05:54:58 +08:00
; SKYLAKE-NEXT: bound %ax, (%esi) # sched: [100:0.25]
; SKYLAKE-NEXT: bound %ecx, (%edx) # sched: [100:0.25]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: popl %esi # sched: [6:0.50]
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; SKYLAKE-NEXT: .cfi_def_cfa_offset 4
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_bound:
; SKX: # %bb.0:
; SKX-NEXT: pushl %esi # sched: [2:1.00]
; SKX-NEXT: .cfi_def_cfa_offset 8
; SKX-NEXT: .cfi_offset %esi, -8
; SKX-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %esi # sched: [5:0.50]
; SKX-NEXT: #APP
[X86] Don't swap argument on BOUND instruction in at&t syntax. The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
2018-02-15 05:54:58 +08:00
; SKX-NEXT: bound %ax, (%esi) # sched: [100:0.25]
; SKX-NEXT: bound %ecx, (%edx) # sched: [100:0.25]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: popl %esi # sched: [6:0.50]
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; SKX-NEXT: .cfi_def_cfa_offset 4
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_bound:
; BTVER2: # %bb.0:
; BTVER2-NEXT: pushl %esi # sched: [1:1.00]
; BTVER2-NEXT: .cfi_def_cfa_offset 8
; BTVER2-NEXT: .cfi_offset %esi, -8
; BTVER2-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %esi # sched: [5:1.00]
; BTVER2-NEXT: #APP
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6) llvm-svn: 327632
2018-03-15 23:12:12 +08:00
; BTVER2-NEXT: bound %ax, (%esi) # sched: [100:0.50]
; BTVER2-NEXT: bound %ecx, (%edx) # sched: [100:0.50]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: popl %esi # sched: [5:1.00]
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; BTVER2-NEXT: .cfi_def_cfa_offset 4
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_bound:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: pushl %esi # sched: [1:0.50]
; ZNVER1-NEXT: .cfi_def_cfa_offset 8
; ZNVER1-NEXT: .cfi_offset %esi, -8
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [8:0.50]
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %esi # sched: [8:0.50]
; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: #APP
[X86] Don't swap argument on BOUND instruction in at&t syntax. The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
2018-02-15 05:54:58 +08:00
; ZNVER1-NEXT: bound %ax, (%esi) # sched: [100:?]
; ZNVER1-NEXT: bound %ecx, (%edx) # sched: [100:?]
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: popl %esi # sched: [8:0.50]
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; ZNVER1-NEXT: .cfi_def_cfa_offset 4
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
; ZNVER1-NEXT: retl # sched: [1:0.50]
[X86] Don't swap argument on BOUND instruction in at&t syntax. The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
2018-02-15 05:54:58 +08:00
call void asm sideeffect "bound $0, $1 \0A\09 bound $2, $3", "r,*m,r,*m"(i16 %a0, i16 *%a1, i32 %a2, i32 *%a3)
[X86] Add ARPL/BOUND schedule tests llvm-svn: 320580
2017-12-13 21:54:45 +08:00
ret void
}
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; TODO - test_call
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
define i8 @test_daa(i8 %a0) optsize {
; GENERIC-LABEL: test_daa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; GENERIC-NEXT: movb {{[0-9]+}}(%esp), %al
; GENERIC-NEXT: #APP
; GENERIC-NEXT: daa
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_daa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ATOM: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; ATOM-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [1:1.00]
; ATOM-NEXT: #APP
; ATOM-NEXT: daa # sched: [18:9.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_daa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; SLM-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: daa # sched: [100:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_daa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; SANDY-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SANDY-NEXT: #APP
; SANDY-NEXT: daa # sched: [100:0.33]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
;
; HASWELL-LABEL: test_daa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; HASWELL-NEXT: #APP
; HASWELL-NEXT: daa # sched: [100:0.25]
; HASWELL-NEXT: #NO_APP
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: retl # sched: [7:1.00]
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
;
; BROADWELL-LABEL: test_daa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; BROADWELL-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: daa # sched: [100:0.25]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_daa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; SKYLAKE-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: daa # sched: [100:0.25]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_daa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKX: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; SKX-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: daa # sched: [100:0.25]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_daa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; BTVER2-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:1.00]
; BTVER2-NEXT: #APP
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6) llvm-svn: 327632
2018-03-15 23:12:12 +08:00
; BTVER2-NEXT: daa # sched: [100:0.50]
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_daa:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; ZNVER1-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: daa # sched: [100:?]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
%1 = tail call i8 asm "daa", "=r,r"(i8 %a0) nounwind
ret i8 %1
}
define i8 @test_das(i8 %a0) optsize {
; GENERIC-LABEL: test_das:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; GENERIC: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; GENERIC-NEXT: movb {{[0-9]+}}(%esp), %al
; GENERIC-NEXT: #APP
; GENERIC-NEXT: das
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_das:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ATOM: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; ATOM-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [1:1.00]
; ATOM-NEXT: #APP
; ATOM-NEXT: das # sched: [20:10.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_das:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SLM: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; SLM-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: das # sched: [100:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_das:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SANDY: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; SANDY-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SANDY-NEXT: #APP
; SANDY-NEXT: das # sched: [100:0.33]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
;
; HASWELL-LABEL: test_das:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; HASWELL: # %bb.0:
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; HASWELL-NEXT: #APP
; HASWELL-NEXT: das # sched: [100:0.25]
; HASWELL-NEXT: #NO_APP
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: retl # sched: [7:1.00]
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
;
; BROADWELL-LABEL: test_das:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BROADWELL: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; BROADWELL-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: das # sched: [100:0.25]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_das:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKYLAKE: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; SKYLAKE-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: das # sched: [100:0.25]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_das:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SKX: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; SKX-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: das # sched: [100:0.25]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_das:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; BTVER2: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; BTVER2-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [5:1.00]
; BTVER2-NEXT: #APP
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6) llvm-svn: 327632
2018-03-15 23:12:12 +08:00
; BTVER2-NEXT: das # sched: [100:0.50]
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_das:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ZNVER1: # %bb.0:
[X86] Add scheduling tests for DAA/DAS llvm-svn: 317892
2017-11-10 23:49:41 +08:00
; ZNVER1-NEXT: movb {{[0-9]+}}(%esp), %al # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: das # sched: [100:?]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
%1 = tail call i8 asm "das", "=r,r"(i8 %a0) nounwind
ret i8 %1
}
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
define void @test_dec16(i16 %a0, i16* %a1) optsize {
; GENERIC-LABEL: test_dec16:
; GENERIC: # %bb.0:
; GENERIC-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GENERIC-NEXT: #APP
; GENERIC-NEXT: decw %ax
; GENERIC-NEXT: decw (%ecx)
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_dec16:
; ATOM: # %bb.0:
; ATOM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [1:1.00]
; ATOM-NEXT: #APP
; ATOM-NEXT: decw %ax # sched: [1:0.50]
; ATOM-NEXT: decw (%ecx) # sched: [1:1.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_dec16:
; SLM: # %bb.0:
; SLM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: decw %ax # sched: [1:0.50]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SLM-NEXT: decw (%ecx) # sched: [5:2.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_dec16:
; SANDY: # %bb.0:
; SANDY-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SANDY-NEXT: #APP
; SANDY-NEXT: decw %ax # sched: [1:0.33]
; SANDY-NEXT: decw (%ecx) # sched: [7:1.00]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
;
; HASWELL-LABEL: test_dec16:
; HASWELL: # %bb.0:
; HASWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; HASWELL-NEXT: #APP
; HASWELL-NEXT: decw %ax # sched: [1:0.25]
; HASWELL-NEXT: decw (%ecx) # sched: [7:1.00]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_dec16:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: decw %ax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; BROADWELL-NEXT: decw (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_dec16:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: decw %ax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SKYLAKE-NEXT: decw (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_dec16:
; SKX: # %bb.0:
; SKX-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: decw %ax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SKX-NEXT: decw (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_dec16:
; BTVER2: # %bb.0:
; BTVER2-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: decw %ax # sched: [1:0.50]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; BTVER2-NEXT: decw (%ecx) # sched: [5:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_dec16:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: decw %ax # sched: [1:0.25]
; ZNVER1-NEXT: decw (%ecx) # sched: [5:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
tail call void asm "decw $0 \0A\09 decw $1", "r,*m"(i16 %a0, i16* %a1) nounwind
ret void
}
define void @test_dec32(i32 %a0, i32* %a1) optsize {
; GENERIC-LABEL: test_dec32:
; GENERIC: # %bb.0:
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %eax
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GENERIC-NEXT: #APP
; GENERIC-NEXT: decl %eax
; GENERIC-NEXT: decl (%ecx)
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_dec32:
; ATOM: # %bb.0:
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [1:1.00]
; ATOM-NEXT: #APP
; ATOM-NEXT: decl %eax # sched: [1:0.50]
; ATOM-NEXT: decl (%ecx) # sched: [1:1.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_dec32:
; SLM: # %bb.0:
; SLM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: decl %eax # sched: [1:0.50]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SLM-NEXT: decl (%ecx) # sched: [5:2.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_dec32:
; SANDY: # %bb.0:
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SANDY-NEXT: #APP
; SANDY-NEXT: decl %eax # sched: [1:0.33]
; SANDY-NEXT: decl (%ecx) # sched: [7:1.00]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
;
; HASWELL-LABEL: test_dec32:
; HASWELL: # %bb.0:
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; HASWELL-NEXT: #APP
; HASWELL-NEXT: decl %eax # sched: [1:0.25]
; HASWELL-NEXT: decl (%ecx) # sched: [7:1.00]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_dec32:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: decl %eax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; BROADWELL-NEXT: decl (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_dec32:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: decl %eax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SKYLAKE-NEXT: decl (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_dec32:
; SKX: # %bb.0:
; SKX-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: decl %eax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SKX-NEXT: decl (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_dec32:
; BTVER2: # %bb.0:
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: decl %eax # sched: [1:0.50]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; BTVER2-NEXT: decl (%ecx) # sched: [5:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_dec32:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: decl %eax # sched: [1:0.25]
; ZNVER1-NEXT: decl (%ecx) # sched: [5:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
tail call void asm "decl $0 \0A\09 decl $1", "r,*m"(i32 %a0, i32* %a1) nounwind
ret void
}
define void @test_inc16(i16 %a0, i16* %a1) optsize {
; GENERIC-LABEL: test_inc16:
; GENERIC: # %bb.0:
; GENERIC-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GENERIC-NEXT: #APP
; GENERIC-NEXT: incw %ax
; GENERIC-NEXT: incw (%ecx)
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_inc16:
; ATOM: # %bb.0:
; ATOM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [1:1.00]
; ATOM-NEXT: #APP
; ATOM-NEXT: incw %ax # sched: [1:0.50]
; ATOM-NEXT: incw (%ecx) # sched: [1:1.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_inc16:
; SLM: # %bb.0:
; SLM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: incw %ax # sched: [1:0.50]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SLM-NEXT: incw (%ecx) # sched: [5:2.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_inc16:
; SANDY: # %bb.0:
; SANDY-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SANDY-NEXT: #APP
; SANDY-NEXT: incw %ax # sched: [1:0.33]
; SANDY-NEXT: incw (%ecx) # sched: [7:1.00]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
;
; HASWELL-LABEL: test_inc16:
; HASWELL: # %bb.0:
; HASWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; HASWELL-NEXT: #APP
; HASWELL-NEXT: incw %ax # sched: [1:0.25]
; HASWELL-NEXT: incw (%ecx) # sched: [7:1.00]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_inc16:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: incw %ax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; BROADWELL-NEXT: incw (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_inc16:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: incw %ax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SKYLAKE-NEXT: incw (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_inc16:
; SKX: # %bb.0:
; SKX-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: incw %ax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SKX-NEXT: incw (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_inc16:
; BTVER2: # %bb.0:
; BTVER2-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: incw %ax # sched: [1:0.50]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; BTVER2-NEXT: incw (%ecx) # sched: [5:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_inc16:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: incw %ax # sched: [1:0.25]
; ZNVER1-NEXT: incw (%ecx) # sched: [5:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
tail call void asm "incw $0 \0A\09 incw $1", "r,*m"(i16 %a0, i16* %a1) nounwind
ret void
}
define void @test_inc32(i32 %a0, i32* %a1) optsize {
; GENERIC-LABEL: test_inc32:
; GENERIC: # %bb.0:
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %eax
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GENERIC-NEXT: #APP
; GENERIC-NEXT: incl %eax
; GENERIC-NEXT: incl (%ecx)
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_inc32:
; ATOM: # %bb.0:
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [1:1.00]
; ATOM-NEXT: #APP
; ATOM-NEXT: incl %eax # sched: [1:0.50]
; ATOM-NEXT: incl (%ecx) # sched: [1:1.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_inc32:
; SLM: # %bb.0:
; SLM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: incl %eax # sched: [1:0.50]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SLM-NEXT: incl (%ecx) # sched: [5:2.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_inc32:
; SANDY: # %bb.0:
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SANDY-NEXT: #APP
; SANDY-NEXT: incl %eax # sched: [1:0.33]
; SANDY-NEXT: incl (%ecx) # sched: [7:1.00]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
;
; HASWELL-LABEL: test_inc32:
; HASWELL: # %bb.0:
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; HASWELL-NEXT: #APP
; HASWELL-NEXT: incl %eax # sched: [1:0.25]
; HASWELL-NEXT: incl (%ecx) # sched: [7:1.00]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_inc32:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: incl %eax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; BROADWELL-NEXT: incl (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_inc32:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: incl %eax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SKYLAKE-NEXT: incl (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_inc32:
; SKX: # %bb.0:
; SKX-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: incl %eax # sched: [1:0.25]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; SKX-NEXT: incl (%ecx) # sched: [7:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_inc32:
; BTVER2: # %bb.0:
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: incl %eax # sched: [1:0.50]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
2018-04-07 00:16:48 +08:00
; BTVER2-NEXT: incl (%ecx) # sched: [5:1.00]
[X86] Add DEC/INC schedule tests Include i686 (non-REX) variant tests as well llvm-svn: 320332
2017-12-11 05:28:00 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_inc32:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: incl %eax # sched: [1:0.25]
; ZNVER1-NEXT: incl (%ecx) # sched: [5:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
tail call void asm "incl $0 \0A\09 incl $1", "r,*m"(i32 %a0, i32* %a1) nounwind
ret void
}
[X86] Add INT/INTO schedule tests llvm-svn: 320386
2017-12-12 00:32:58 +08:00
define void @test_into() optsize {
; GENERIC-LABEL: test_into:
; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP
; GENERIC-NEXT: into
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_into:
; ATOM: # %bb.0:
; ATOM-NEXT: #APP
[X86][Atom] Convert Atom scheduler model to SchedRW (PR32431) Atom is the only x86 target that still uses schedule itineraries, if we can remove this then we can begin the work on removing x86 itineraries. I've also found that it will help with PR36550. I've focussed on matching the existing model as closely as possible (relying on the schedule tests), PR36895 indicated a lot of these were incorrect but we can just as easily fix these after this patch as before. Hopefully we can get llvm-exegesis to help here, There are a few instructions that rely on itinerary scheduling (mainly push/pop/return) of multiple resource stages, but I don't think any of these are show stoppers. There are also a few codegen changes that seem related to the post-ra scheduler acting a little differently, I haven't tracked these down but they don't seem critical. NOTE: I don't have access to any Atom hardware, so this hasn't been tested in the wild. Differential Revision: https://reviews.llvm.org/D45486 llvm-svn: 329837
2018-04-12 02:23:01 +08:00
; ATOM-NEXT: into # sched: [6:3.00]
[X86] Add INT/INTO schedule tests llvm-svn: 320386
2017-12-12 00:32:58 +08:00
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_into:
; SLM: # %bb.0:
; SLM-NEXT: #APP
; SLM-NEXT: into # sched: [100:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_into:
; SANDY: # %bb.0:
; SANDY-NEXT: #APP
; SANDY-NEXT: into # sched: [100:0.33]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add INT/INTO schedule tests llvm-svn: 320386
2017-12-12 00:32:58 +08:00
;
; HASWELL-LABEL: test_into:
; HASWELL: # %bb.0:
; HASWELL-NEXT: #APP
; HASWELL-NEXT: into # sched: [1:?]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_into:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: into # sched: [100:0.25]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_into:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: into # sched: [100:0.25]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_into:
; SKX: # %bb.0:
; SKX-NEXT: #APP
; SKX-NEXT: into # sched: [100:0.25]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_into:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6) llvm-svn: 327632
2018-03-15 23:12:12 +08:00
; BTVER2-NEXT: into # sched: [100:0.50]
[X86] Add INT/INTO schedule tests llvm-svn: 320386
2017-12-12 00:32:58 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_into:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: into # sched: [100:?]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
call void asm sideeffect "into", ""()
ret void
}
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; TODO - test_jmp
[X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests llvm-svn: 320603
2017-12-14 02:09:45 +08:00
define void @test_jcxz_jecxz() optsize {
; GENERIC-LABEL: test_jcxz_jecxz:
; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP
; GENERIC-NEXT: JXTGT:
; GENERIC-NEXT: jcxz JXTGT
; GENERIC-NEXT: jecxz JXTGT
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_jcxz_jecxz:
; ATOM: # %bb.0:
; ATOM-NEXT: #APP
; ATOM-NEXT: JXTGT:
; ATOM-NEXT: jcxz JXTGT # sched: [4:2.00]
; ATOM-NEXT: jecxz JXTGT # sched: [4:2.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_jcxz_jecxz:
; SLM: # %bb.0:
; SLM-NEXT: #APP
; SLM-NEXT: JXTGT:
; SLM-NEXT: jcxz JXTGT # sched: [1:1.00]
; SLM-NEXT: jecxz JXTGT # sched: [1:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_jcxz_jecxz:
; SANDY: # %bb.0:
; SANDY-NEXT: #APP
; SANDY-NEXT: JXTGT:
[X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models. JRCXZ was already present, but not the others. We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output. llvm-svn: 327881
2018-03-20 03:00:32 +08:00
; SANDY-NEXT: jcxz JXTGT # sched: [2:1.00]
; SANDY-NEXT: jecxz JXTGT # sched: [2:1.00]
[X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests llvm-svn: 320603
2017-12-14 02:09:45 +08:00
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests llvm-svn: 320603
2017-12-14 02:09:45 +08:00
;
; HASWELL-LABEL: test_jcxz_jecxz:
; HASWELL: # %bb.0:
; HASWELL-NEXT: #APP
; HASWELL-NEXT: JXTGT:
[X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models. JRCXZ was already present, but not the others. We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output. llvm-svn: 327881
2018-03-20 03:00:32 +08:00
; HASWELL-NEXT: jcxz JXTGT # sched: [2:0.50]
; HASWELL-NEXT: jecxz JXTGT # sched: [2:0.50]
[X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests llvm-svn: 320603
2017-12-14 02:09:45 +08:00
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_jcxz_jecxz:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: JXTGT:
[X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models. JRCXZ was already present, but not the others. We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output. llvm-svn: 327881
2018-03-20 03:00:32 +08:00
; BROADWELL-NEXT: jcxz JXTGT # sched: [2:0.50]
; BROADWELL-NEXT: jecxz JXTGT # sched: [2:0.50]
[X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests llvm-svn: 320603
2017-12-14 02:09:45 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_jcxz_jecxz:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: JXTGT:
[X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models. JRCXZ was already present, but not the others. We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output. llvm-svn: 327881
2018-03-20 03:00:32 +08:00
; SKYLAKE-NEXT: jcxz JXTGT # sched: [2:0.50]
; SKYLAKE-NEXT: jecxz JXTGT # sched: [2:0.50]
[X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests llvm-svn: 320603
2017-12-14 02:09:45 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_jcxz_jecxz:
; SKX: # %bb.0:
; SKX-NEXT: #APP
; SKX-NEXT: JXTGT:
[X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models. JRCXZ was already present, but not the others. We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output. llvm-svn: 327881
2018-03-20 03:00:32 +08:00
; SKX-NEXT: jcxz JXTGT # sched: [2:0.50]
; SKX-NEXT: jecxz JXTGT # sched: [2:0.50]
[X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests llvm-svn: 320603
2017-12-14 02:09:45 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_jcxz_jecxz:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
; BTVER2-NEXT: JXTGT:
; BTVER2-NEXT: jcxz JXTGT # sched: [1:0.50]
; BTVER2-NEXT: jecxz JXTGT # sched: [1:0.50]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_jcxz_jecxz:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: JXTGT:
; ZNVER1-NEXT: jcxz JXTGT # sched: [1:0.50]
[X86] Correct regular expression in Zen scheduler model that was excluding JECXZ instruction. The regex was looking for JECXZ_32 or JECXZ_64, but their is just one instruction called JECXZ. They used to exist as separate instructions, but were merged over 3 years ago. llvm-svn: 327880
2018-03-20 03:00:29 +08:00
; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.50]
[X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests llvm-svn: 320603
2017-12-14 02:09:45 +08:00
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
call void asm sideeffect "JXTGT: \0A\09 jcxz JXTGT \0A\09 jecxz JXTGT", ""()
ret void
}
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; TODO - test_lds
[X86] Add ENTER/LEAVE schedule tests llvm-svn: 320583
2017-12-13 22:46:33 +08:00
define void @test_leave() optsize {
; GENERIC-LABEL: test_leave:
; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP
; GENERIC-NEXT: leave
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_leave:
; ATOM: # %bb.0:
; ATOM-NEXT: #APP
; ATOM-NEXT: leave # sched: [2:1.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_leave:
; SLM: # %bb.0:
; SLM-NEXT: #APP
; SLM-NEXT: leave # sched: [1:0.50]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_leave:
; SANDY: # %bb.0:
; SANDY-NEXT: #APP
[X86] Add LEAVE instruction to the scheduler models using the same data as LEAVE64. Make LEAVE/LEAVE64 more correct on Sandy Bridge. This is the 32-bit mode version of LEAVE64. It should be at least somewhat similar to LEAVE64. The Sandy Bridge version was missing a load port use. llvm-svn: 329347
2018-04-06 05:16:26 +08:00
; SANDY-NEXT: leave # sched: [7:0.67]
[X86] Add ENTER/LEAVE schedule tests llvm-svn: 320583
2017-12-13 22:46:33 +08:00
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add ENTER/LEAVE schedule tests llvm-svn: 320583
2017-12-13 22:46:33 +08:00
;
; HASWELL-LABEL: test_leave:
; HASWELL: # %bb.0:
; HASWELL-NEXT: #APP
[X86] Add LEAVE instruction to the scheduler models using the same data as LEAVE64. Make LEAVE/LEAVE64 more correct on Sandy Bridge. This is the 32-bit mode version of LEAVE64. It should be at least somewhat similar to LEAVE64. The Sandy Bridge version was missing a load port use. llvm-svn: 329347
2018-04-06 05:16:26 +08:00
; HASWELL-NEXT: leave # sched: [7:0.50]
[X86] Add ENTER/LEAVE schedule tests llvm-svn: 320583
2017-12-13 22:46:33 +08:00
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_leave:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: #APP
[X86] Add LEAVE instruction to the scheduler models using the same data as LEAVE64. Make LEAVE/LEAVE64 more correct on Sandy Bridge. This is the 32-bit mode version of LEAVE64. It should be at least somewhat similar to LEAVE64. The Sandy Bridge version was missing a load port use. llvm-svn: 329347
2018-04-06 05:16:26 +08:00
; BROADWELL-NEXT: leave # sched: [7:0.50]
[X86] Add ENTER/LEAVE schedule tests llvm-svn: 320583
2017-12-13 22:46:33 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_leave:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: #APP
[X86] Add LEAVE instruction to the scheduler models using the same data as LEAVE64. Make LEAVE/LEAVE64 more correct on Sandy Bridge. This is the 32-bit mode version of LEAVE64. It should be at least somewhat similar to LEAVE64. The Sandy Bridge version was missing a load port use. llvm-svn: 329347
2018-04-06 05:16:26 +08:00
; SKYLAKE-NEXT: leave # sched: [7:0.50]
[X86] Add ENTER/LEAVE schedule tests llvm-svn: 320583
2017-12-13 22:46:33 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_leave:
; SKX: # %bb.0:
; SKX-NEXT: #APP
[X86] Add LEAVE instruction to the scheduler models using the same data as LEAVE64. Make LEAVE/LEAVE64 more correct on Sandy Bridge. This is the 32-bit mode version of LEAVE64. It should be at least somewhat similar to LEAVE64. The Sandy Bridge version was missing a load port use. llvm-svn: 329347
2018-04-06 05:16:26 +08:00
; SKX-NEXT: leave # sched: [7:0.50]
[X86] Add ENTER/LEAVE schedule tests llvm-svn: 320583
2017-12-13 22:46:33 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_leave:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
; BTVER2-NEXT: leave # sched: [1:0.50]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_leave:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: leave # sched: [8:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
tail call void asm "leave", ""() nounwind
ret void
}
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; TODO - test_les
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
define void @test_pop_push() optsize {
; GENERIC-LABEL: test_pop_push:
; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP
; GENERIC-NEXT: popl %ds
; GENERIC-NEXT: popl %es
; GENERIC-NEXT: popl %ss
; GENERIC-NEXT: popl %fs
; GENERIC-NEXT: popl %gs
; GENERIC-NEXT: pushl %cs
; GENERIC-NEXT: pushl %ds
; GENERIC-NEXT: pushl %es
; GENERIC-NEXT: pushl %ss
; GENERIC-NEXT: pushl %fs
; GENERIC-NEXT: pushl %gs
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_pop_push:
; ATOM: # %bb.0:
; ATOM-NEXT: #APP
; ATOM-NEXT: popl %ds # sched: [29:14.50]
; ATOM-NEXT: popl %es # sched: [29:14.50]
; ATOM-NEXT: popl %ss # sched: [48:24.00]
; ATOM-NEXT: popl %fs # sched: [29:14.50]
; ATOM-NEXT: popl %gs # sched: [29:14.50]
; ATOM-NEXT: pushl %cs # sched: [2:1.00]
; ATOM-NEXT: pushl %ds # sched: [2:1.00]
; ATOM-NEXT: pushl %es # sched: [2:1.00]
; ATOM-NEXT: pushl %ss # sched: [2:1.00]
; ATOM-NEXT: pushl %fs # sched: [2:1.00]
; ATOM-NEXT: pushl %gs # sched: [2:1.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_pop_push:
; SLM: # %bb.0:
; SLM-NEXT: #APP
; SLM-NEXT: popl %ds # sched: [100:1.00]
; SLM-NEXT: popl %es # sched: [100:1.00]
; SLM-NEXT: popl %ss # sched: [100:1.00]
; SLM-NEXT: popl %fs # sched: [100:1.00]
; SLM-NEXT: popl %gs # sched: [100:1.00]
; SLM-NEXT: pushl %cs # sched: [100:1.00]
; SLM-NEXT: pushl %ds # sched: [100:1.00]
; SLM-NEXT: pushl %es # sched: [100:1.00]
; SLM-NEXT: pushl %ss # sched: [100:1.00]
; SLM-NEXT: pushl %fs # sched: [100:1.00]
; SLM-NEXT: pushl %gs # sched: [100:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_pop_push:
; SANDY: # %bb.0:
; SANDY-NEXT: #APP
; SANDY-NEXT: popl %ds # sched: [100:0.33]
; SANDY-NEXT: popl %es # sched: [100:0.33]
; SANDY-NEXT: popl %ss # sched: [100:0.33]
; SANDY-NEXT: popl %fs # sched: [100:0.33]
; SANDY-NEXT: popl %gs # sched: [100:0.33]
; SANDY-NEXT: pushl %cs # sched: [100:0.33]
; SANDY-NEXT: pushl %ds # sched: [100:0.33]
; SANDY-NEXT: pushl %es # sched: [100:0.33]
; SANDY-NEXT: pushl %ss # sched: [100:0.33]
; SANDY-NEXT: pushl %fs # sched: [100:0.33]
; SANDY-NEXT: pushl %gs # sched: [100:0.33]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
;
; HASWELL-LABEL: test_pop_push:
; HASWELL: # %bb.0:
; HASWELL-NEXT: #APP
; HASWELL-NEXT: popl %ds # sched: [100:0.25]
; HASWELL-NEXT: popl %es # sched: [100:0.25]
; HASWELL-NEXT: popl %ss # sched: [100:0.25]
; HASWELL-NEXT: popl %fs # sched: [100:0.25]
; HASWELL-NEXT: popl %gs # sched: [100:0.25]
; HASWELL-NEXT: pushl %cs # sched: [100:0.25]
; HASWELL-NEXT: pushl %ds # sched: [100:0.25]
; HASWELL-NEXT: pushl %es # sched: [100:0.25]
; HASWELL-NEXT: pushl %ss # sched: [100:0.25]
; HASWELL-NEXT: pushl %fs # sched: [100:0.25]
; HASWELL-NEXT: pushl %gs # sched: [100:0.25]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_pop_push:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: popl %ds # sched: [100:0.25]
; BROADWELL-NEXT: popl %es # sched: [100:0.25]
; BROADWELL-NEXT: popl %ss # sched: [100:0.25]
; BROADWELL-NEXT: popl %fs # sched: [100:0.25]
; BROADWELL-NEXT: popl %gs # sched: [100:0.25]
; BROADWELL-NEXT: pushl %cs # sched: [100:0.25]
; BROADWELL-NEXT: pushl %ds # sched: [100:0.25]
; BROADWELL-NEXT: pushl %es # sched: [100:0.25]
; BROADWELL-NEXT: pushl %ss # sched: [100:0.25]
; BROADWELL-NEXT: pushl %fs # sched: [100:0.25]
; BROADWELL-NEXT: pushl %gs # sched: [100:0.25]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_pop_push:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: popl %ds # sched: [100:0.25]
; SKYLAKE-NEXT: popl %es # sched: [100:0.25]
; SKYLAKE-NEXT: popl %ss # sched: [100:0.25]
; SKYLAKE-NEXT: popl %fs # sched: [100:0.25]
; SKYLAKE-NEXT: popl %gs # sched: [100:0.25]
; SKYLAKE-NEXT: pushl %cs # sched: [100:0.25]
; SKYLAKE-NEXT: pushl %ds # sched: [100:0.25]
; SKYLAKE-NEXT: pushl %es # sched: [100:0.25]
; SKYLAKE-NEXT: pushl %ss # sched: [100:0.25]
; SKYLAKE-NEXT: pushl %fs # sched: [100:0.25]
; SKYLAKE-NEXT: pushl %gs # sched: [100:0.25]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_pop_push:
; SKX: # %bb.0:
; SKX-NEXT: #APP
; SKX-NEXT: popl %ds # sched: [100:0.25]
; SKX-NEXT: popl %es # sched: [100:0.25]
; SKX-NEXT: popl %ss # sched: [100:0.25]
; SKX-NEXT: popl %fs # sched: [100:0.25]
; SKX-NEXT: popl %gs # sched: [100:0.25]
; SKX-NEXT: pushl %cs # sched: [100:0.25]
; SKX-NEXT: pushl %ds # sched: [100:0.25]
; SKX-NEXT: pushl %es # sched: [100:0.25]
; SKX-NEXT: pushl %ss # sched: [100:0.25]
; SKX-NEXT: pushl %fs # sched: [100:0.25]
; SKX-NEXT: pushl %gs # sched: [100:0.25]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_pop_push:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6) llvm-svn: 327632
2018-03-15 23:12:12 +08:00
; BTVER2-NEXT: popl %ds # sched: [100:0.50]
; BTVER2-NEXT: popl %es # sched: [100:0.50]
; BTVER2-NEXT: popl %ss # sched: [100:0.50]
; BTVER2-NEXT: popl %fs # sched: [100:0.50]
; BTVER2-NEXT: popl %gs # sched: [100:0.50]
; BTVER2-NEXT: pushl %cs # sched: [100:0.50]
; BTVER2-NEXT: pushl %ds # sched: [100:0.50]
; BTVER2-NEXT: pushl %es # sched: [100:0.50]
; BTVER2-NEXT: pushl %ss # sched: [100:0.50]
; BTVER2-NEXT: pushl %fs # sched: [100:0.50]
; BTVER2-NEXT: pushl %gs # sched: [100:0.50]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_pop_push:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: popl %ds # sched: [100:?]
; ZNVER1-NEXT: popl %es # sched: [100:?]
; ZNVER1-NEXT: popl %ss # sched: [100:?]
; ZNVER1-NEXT: popl %fs # sched: [100:?]
; ZNVER1-NEXT: popl %gs # sched: [100:?]
; ZNVER1-NEXT: pushl %cs # sched: [100:?]
; ZNVER1-NEXT: pushl %ds # sched: [100:?]
; ZNVER1-NEXT: pushl %es # sched: [100:?]
; ZNVER1-NEXT: pushl %ss # sched: [100:?]
; ZNVER1-NEXT: pushl %fs # sched: [100:?]
; ZNVER1-NEXT: pushl %gs # sched: [100:?]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
call void asm sideeffect "pop %DS \0A\09 pop %ES \0A\09 pop %SS \0A\09 pop %FS \0A\09 pop %GS \0A\09 push %CS \0A\09 push %DS \0A\09 push %ES \0A\09 push %SS \0A\09 push %FS \0A\09 push %GS", ""()
ret void
}
define i16 @test_pop_push_16(i16 %a0, i16 *%a1) optsize {
; GENERIC-LABEL: test_pop_push_16:
; GENERIC: # %bb.0:
; GENERIC-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GENERIC-NEXT: #APP
; GENERIC-NEXT: popw %ax
; GENERIC-NEXT: popw (%ecx)
; GENERIC-NEXT: pushw %ax
; GENERIC-NEXT: pushw (%ecx)
; GENERIC-NEXT: pushw $4095 # imm = 0xFFF
; GENERIC-NEXT: pushw $7
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_pop_push_16:
; ATOM: # %bb.0:
; ATOM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [1:1.00]
; ATOM-NEXT: #APP
; ATOM-NEXT: popw %ax # sched: [2:1.00]
; ATOM-NEXT: popw (%ecx) # sched: [3:1.50]
; ATOM-NEXT: pushw %ax # sched: [1:1.00]
; ATOM-NEXT: pushw (%ecx) # sched: [2:1.00]
; ATOM-NEXT: pushw $4095 # imm = 0xFFF
; ATOM-NEXT: # sched: [1:1.00]
; ATOM-NEXT: pushw $7 # sched: [1:1.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_pop_push_16:
; SLM: # %bb.0:
; SLM-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: popw %ax # sched: [3:1.00]
; SLM-NEXT: popw (%ecx) # sched: [1:1.00]
; SLM-NEXT: pushw %ax # sched: [1:1.00]
; SLM-NEXT: pushw (%ecx) # sched: [1:1.00]
; SLM-NEXT: pushw $4095 # imm = 0xFFF
; SLM-NEXT: # sched: [1:1.00]
; SLM-NEXT: pushw $7 # sched: [1:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_pop_push_16:
; SANDY: # %bb.0:
; SANDY-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SANDY-NEXT: #APP
; SANDY-NEXT: popw %ax # sched: [6:0.50]
; SANDY-NEXT: popw (%ecx) # sched: [6:0.50]
; SANDY-NEXT: pushw %ax # sched: [5:1.00]
; SANDY-NEXT: pushw (%ecx) # sched: [5:1.00]
; SANDY-NEXT: pushw $4095 # imm = 0xFFF
; SANDY-NEXT: # sched: [1:1.00]
; SANDY-NEXT: pushw $7 # sched: [1:1.00]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
;
; HASWELL-LABEL: test_pop_push_16:
; HASWELL: # %bb.0:
; HASWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; HASWELL-NEXT: #APP
; HASWELL-NEXT: popw %ax # sched: [6:0.50]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; HASWELL-NEXT: popw (%ecx) # sched: [7:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; HASWELL-NEXT: pushw %ax # sched: [2:1.00]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; HASWELL-NEXT: pushw (%ecx) # sched: [7:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; HASWELL-NEXT: pushw $4095 # imm = 0xFFF
; HASWELL-NEXT: # sched: [1:1.00]
; HASWELL-NEXT: pushw $7 # sched: [1:1.00]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_pop_push_16:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: popw %ax # sched: [6:0.50]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; BROADWELL-NEXT: popw (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; BROADWELL-NEXT: pushw %ax # sched: [2:1.00]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; BROADWELL-NEXT: pushw (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; BROADWELL-NEXT: pushw $4095 # imm = 0xFFF
; BROADWELL-NEXT: # sched: [1:1.00]
; BROADWELL-NEXT: pushw $7 # sched: [1:1.00]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_pop_push_16:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: popw %ax # sched: [6:0.50]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; SKYLAKE-NEXT: popw (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; SKYLAKE-NEXT: pushw %ax # sched: [2:1.00]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; SKYLAKE-NEXT: pushw (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; SKYLAKE-NEXT: pushw $4095 # imm = 0xFFF
; SKYLAKE-NEXT: # sched: [1:1.00]
; SKYLAKE-NEXT: pushw $7 # sched: [1:1.00]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_pop_push_16:
; SKX: # %bb.0:
; SKX-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: popw %ax # sched: [6:0.50]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; SKX-NEXT: popw (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; SKX-NEXT: pushw %ax # sched: [2:1.00]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; SKX-NEXT: pushw (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; SKX-NEXT: pushw $4095 # imm = 0xFFF
; SKX-NEXT: # sched: [1:1.00]
; SKX-NEXT: pushw $7 # sched: [1:1.00]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_pop_push_16:
; BTVER2: # %bb.0:
; BTVER2-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [4:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: popw %ax # sched: [5:1.00]
; BTVER2-NEXT: popw (%ecx) # sched: [1:1.00]
; BTVER2-NEXT: pushw %ax # sched: [1:1.00]
; BTVER2-NEXT: pushw (%ecx) # sched: [1:1.00]
; BTVER2-NEXT: pushw $4095 # imm = 0xFFF
; BTVER2-NEXT: # sched: [1:1.00]
; BTVER2-NEXT: pushw $7 # sched: [1:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_pop_push_16:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: popw %ax # sched: [8:0.50]
; ZNVER1-NEXT: popw (%ecx) # sched: [5:0.50]
; ZNVER1-NEXT: pushw %ax # sched: [1:0.50]
; ZNVER1-NEXT: pushw (%ecx) # sched: [4:0.50]
; ZNVER1-NEXT: pushw $4095 # imm = 0xFFF
; ZNVER1-NEXT: # sched: [1:0.50]
; ZNVER1-NEXT: pushw $7 # sched: [1:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
%1 = call i16 asm sideeffect "popw $0 \0A\09 popw $2 \0A\09 pushw $1 \0A\09 pushw $2 \0A\09 pushw $3 \0A\09 pushw $4", "=r,r,*m,i,i"(i16 %a0, i16 *%a1, i16 4095, i8 7)
ret i16 %1
}
define i32 @test_pop_push_32(i32 %a0, i32 *%a1) optsize {
; GENERIC-LABEL: test_pop_push_32:
; GENERIC: # %bb.0:
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %eax
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GENERIC-NEXT: #APP
; GENERIC-NEXT: popl %eax
; GENERIC-NEXT: popl (%ecx)
; GENERIC-NEXT: pushl %eax
; GENERIC-NEXT: pushl (%ecx)
; GENERIC-NEXT: pushl $4095 # imm = 0xFFF
; GENERIC-NEXT: pushl $7
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_pop_push_32:
; ATOM: # %bb.0:
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [1:1.00]
; ATOM-NEXT: #APP
; ATOM-NEXT: popl %eax # sched: [1:1.00]
; ATOM-NEXT: popl (%ecx) # sched: [3:1.50]
; ATOM-NEXT: pushl %eax # sched: [1:1.00]
; ATOM-NEXT: pushl (%ecx) # sched: [2:1.00]
; ATOM-NEXT: pushl $4095 # imm = 0xFFF
; ATOM-NEXT: # sched: [1:1.00]
; ATOM-NEXT: pushl $7 # sched: [1:1.00]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_pop_push_32:
; SLM: # %bb.0:
; SLM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: popl %eax # sched: [3:1.00]
; SLM-NEXT: popl (%ecx) # sched: [1:1.00]
; SLM-NEXT: pushl %eax # sched: [1:1.00]
; SLM-NEXT: pushl (%ecx) # sched: [1:1.00]
; SLM-NEXT: pushl $4095 # imm = 0xFFF
; SLM-NEXT: # sched: [1:1.00]
; SLM-NEXT: pushl $7 # sched: [1:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_pop_push_32:
; SANDY: # %bb.0:
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SANDY-NEXT: #APP
; SANDY-NEXT: popl %eax # sched: [6:0.50]
; SANDY-NEXT: popl (%ecx) # sched: [6:0.50]
; SANDY-NEXT: pushl %eax # sched: [5:1.00]
; SANDY-NEXT: pushl (%ecx) # sched: [5:1.00]
; SANDY-NEXT: pushl $4095 # imm = 0xFFF
; SANDY-NEXT: # sched: [1:1.00]
; SANDY-NEXT: pushl $7 # sched: [1:1.00]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
;
; HASWELL-LABEL: test_pop_push_32:
; HASWELL: # %bb.0:
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; HASWELL-NEXT: #APP
; HASWELL-NEXT: popl %eax # sched: [6:0.50]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; HASWELL-NEXT: popl (%ecx) # sched: [7:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; HASWELL-NEXT: pushl %eax # sched: [2:1.00]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; HASWELL-NEXT: pushl (%ecx) # sched: [7:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; HASWELL-NEXT: pushl $4095 # imm = 0xFFF
; HASWELL-NEXT: # sched: [1:1.00]
; HASWELL-NEXT: pushl $7 # sched: [1:1.00]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_pop_push_32:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: popl %eax # sched: [6:0.50]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; BROADWELL-NEXT: popl (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; BROADWELL-NEXT: pushl %eax # sched: [2:1.00]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; BROADWELL-NEXT: pushl (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; BROADWELL-NEXT: pushl $4095 # imm = 0xFFF
; BROADWELL-NEXT: # sched: [1:1.00]
; BROADWELL-NEXT: pushl $7 # sched: [1:1.00]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_pop_push_32:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: popl %eax # sched: [6:0.50]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; SKYLAKE-NEXT: popl (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; SKYLAKE-NEXT: pushl %eax # sched: [2:1.00]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; SKYLAKE-NEXT: pushl (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; SKYLAKE-NEXT: pushl $4095 # imm = 0xFFF
; SKYLAKE-NEXT: # sched: [1:1.00]
; SKYLAKE-NEXT: pushl $7 # sched: [1:1.00]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_pop_push_32:
; SKX: # %bb.0:
; SKX-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: #APP
; SKX-NEXT: popl %eax # sched: [6:0.50]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; SKX-NEXT: popl (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; SKX-NEXT: pushl %eax # sched: [2:1.00]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models. llvm-svn: 327787
2018-03-18 16:38:06 +08:00
; SKX-NEXT: pushl (%ecx) # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; SKX-NEXT: pushl $4095 # imm = 0xFFF
; SKX-NEXT: # sched: [1:1.00]
; SKX-NEXT: pushl $7 # sched: [1:1.00]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_pop_push_32:
; BTVER2: # %bb.0:
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: popl %eax # sched: [5:1.00]
; BTVER2-NEXT: popl (%ecx) # sched: [1:1.00]
; BTVER2-NEXT: pushl %eax # sched: [1:1.00]
; BTVER2-NEXT: pushl (%ecx) # sched: [1:1.00]
; BTVER2-NEXT: pushl $4095 # imm = 0xFFF
; BTVER2-NEXT: # sched: [1:1.00]
; BTVER2-NEXT: pushl $7 # sched: [1:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_pop_push_32:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: popl %eax # sched: [8:0.50]
; ZNVER1-NEXT: popl (%ecx) # sched: [1:0.50]
; ZNVER1-NEXT: pushl %eax # sched: [1:0.50]
; ZNVER1-NEXT: pushl (%ecx) # sched: [4:0.50]
; ZNVER1-NEXT: pushl $4095 # imm = 0xFFF
; ZNVER1-NEXT: # sched: [1:0.50]
; ZNVER1-NEXT: pushl $7 # sched: [1:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
%1 = call i32 asm sideeffect "popl $0 \0A\09 popl $2 \0A\09 pushl $1 \0A\09 pushl $2 \0A\09 pushl $3 \0A\09 pushl $4", "=r,r,*m,i,i"(i32 %a0, i32 *%a1, i32 4095, i8 7)
ret i32 %1
}
define void @test_popa_popf_pusha_pushf() optsize {
; GENERIC-LABEL: test_popa_popf_pusha_pushf:
; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP
; GENERIC-NEXT: popal
; GENERIC-NEXT: popfl
; GENERIC-NEXT: pushal
; GENERIC-NEXT: pushfl
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_popa_popf_pusha_pushf:
; ATOM: # %bb.0:
; ATOM-NEXT: #APP
; ATOM-NEXT: popal # sched: [9:4.50]
; ATOM-NEXT: popfl # sched: [26:13.00]
; ATOM-NEXT: pushal # sched: [8:4.00]
; ATOM-NEXT: pushfl # sched: [9:4.50]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_popa_popf_pusha_pushf:
; SLM: # %bb.0:
; SLM-NEXT: #APP
; SLM-NEXT: popal # sched: [3:1.00]
; SLM-NEXT: popfl # sched: [3:1.00]
; SLM-NEXT: pushal # sched: [1:1.00]
; SLM-NEXT: pushfl # sched: [1:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_popa_popf_pusha_pushf:
; SANDY: # %bb.0:
; SANDY-NEXT: #APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: popal # sched: [5:0.50]
; SANDY-NEXT: popfl # sched: [5:0.50]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
; SANDY-NEXT: pushal # sched: [1:1.00]
; SANDY-NEXT: pushfl # sched: [1:1.00]
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add POP/PUSH schedule tests llvm-svn: 320598
2017-12-14 01:42:25 +08:00
;
; HASWELL-LABEL: test_popa_popf_pusha_pushf:
; HASWELL: # %bb.0:
; HASWELL-NEXT: #APP
; HASWELL-NEXT: popal # sched: [1:?]
; HASWELL-NEXT: popfl # sched: [5:0.50]
; HASWELL-NEXT: pushal # sched: [1:?]
; HASWELL-NEXT: pushfl # sched: [1:1.00]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_popa_popf_pusha_pushf:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: popal # sched: [5:0.50]
; BROADWELL-NEXT: popfl # sched: [5:0.50]
; BROADWELL-NEXT: pushal # sched: [1:1.00]
; BROADWELL-NEXT: pushfl # sched: [1:1.00]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_popa_popf_pusha_pushf:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: popal # sched: [5:0.50]
; SKYLAKE-NEXT: popfl # sched: [5:0.50]
; SKYLAKE-NEXT: pushal # sched: [1:1.00]
; SKYLAKE-NEXT: pushfl # sched: [1:1.00]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_popa_popf_pusha_pushf:
; SKX: # %bb.0:
; SKX-NEXT: #APP
; SKX-NEXT: popal # sched: [5:0.50]
; SKX-NEXT: popfl # sched: [5:0.50]
; SKX-NEXT: pushal # sched: [1:1.00]
; SKX-NEXT: pushfl # sched: [1:1.00]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_popa_popf_pusha_pushf:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
; BTVER2-NEXT: popal # sched: [5:1.00]
; BTVER2-NEXT: popfl # sched: [5:1.00]
; BTVER2-NEXT: pushal # sched: [1:1.00]
; BTVER2-NEXT: pushfl # sched: [1:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_popa_popf_pusha_pushf:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: popal # sched: [100:?]
; ZNVER1-NEXT: popfl # sched: [100:?]
; ZNVER1-NEXT: pushal # sched: [8:0.50]
; ZNVER1-NEXT: pushfl # sched: [100:?]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
call void asm sideeffect "popa \0A\09 popf \0A\09 pusha \0A\09 pushf", ""()
ret void
}
[X86] Add RET/RETF schedule tests llvm-svn: 320600
2017-12-14 01:50:40 +08:00
define void @test_ret() optsize {
; GENERIC-LABEL: test_ret:
; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP
; GENERIC-NEXT: retl
; GENERIC-NEXT: retl $4095 # imm = 0xFFF
; GENERIC-NEXT: lretl
; GENERIC-NEXT: lretl $4095 # imm = 0xFFF
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_ret:
; ATOM: # %bb.0:
; ATOM-NEXT: #APP
; ATOM-NEXT: retl # sched: [79:39.50]
; ATOM-NEXT: retl $4095 # imm = 0xFFF
; ATOM-NEXT: # sched: [1:1.00]
; ATOM-NEXT: lretl # sched: [79:39.50]
; ATOM-NEXT: lretl $4095 # imm = 0xFFF
; ATOM-NEXT: # sched: [79:39.50]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_ret:
; SLM: # %bb.0:
; SLM-NEXT: #APP
; SLM-NEXT: retl # sched: [4:1.00]
; SLM-NEXT: retl $4095 # imm = 0xFFF
; SLM-NEXT: # sched: [4:1.00]
; SLM-NEXT: lretl # sched: [4:1.00]
; SLM-NEXT: lretl $4095 # imm = 0xFFF
; SLM-NEXT: # sched: [4:1.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_ret:
; SANDY: # %bb.0:
; SANDY-NEXT: #APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add RET/RETF schedule tests llvm-svn: 320600
2017-12-14 01:50:40 +08:00
; SANDY-NEXT: retl $4095 # imm = 0xFFF
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: # sched: [6:1.00]
; SANDY-NEXT: lretl # sched: [6:1.00]
[X86] Add RET/RETF schedule tests llvm-svn: 320600
2017-12-14 01:50:40 +08:00
; SANDY-NEXT: lretl $4095 # imm = 0xFFF
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: # sched: [6:1.00]
[X86] Add RET/RETF schedule tests llvm-svn: 320600
2017-12-14 01:50:40 +08:00
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add RET/RETF schedule tests llvm-svn: 320600
2017-12-14 01:50:40 +08:00
;
; HASWELL-LABEL: test_ret:
; HASWELL: # %bb.0:
; HASWELL-NEXT: #APP
; HASWELL-NEXT: retl # sched: [7:1.00]
; HASWELL-NEXT: retl $4095 # imm = 0xFFF
; HASWELL-NEXT: # sched: [1:2.00]
; HASWELL-NEXT: lretl # sched: [6:0.50]
; HASWELL-NEXT: lretl $4095 # imm = 0xFFF
; HASWELL-NEXT: # sched: [1:2.00]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_ret:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: #APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
; BROADWELL-NEXT: retl $4095 # imm = 0xFFF
; BROADWELL-NEXT: # sched: [6:0.50]
; BROADWELL-NEXT: lretl # sched: [6:0.50]
; BROADWELL-NEXT: lretl $4095 # imm = 0xFFF
; BROADWELL-NEXT: # sched: [6:0.50]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_ret:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: #APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
; SKYLAKE-NEXT: retl $4095 # imm = 0xFFF
; SKYLAKE-NEXT: # sched: [6:0.50]
; SKYLAKE-NEXT: lretl # sched: [6:0.50]
; SKYLAKE-NEXT: lretl $4095 # imm = 0xFFF
; SKYLAKE-NEXT: # sched: [6:0.50]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_ret:
; SKX: # %bb.0:
; SKX-NEXT: #APP
; SKX-NEXT: retl # sched: [6:0.50]
; SKX-NEXT: retl $4095 # imm = 0xFFF
; SKX-NEXT: # sched: [6:0.50]
; SKX-NEXT: lretl # sched: [6:0.50]
; SKX-NEXT: lretl $4095 # imm = 0xFFF
; SKX-NEXT: # sched: [6:0.50]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_ret:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
; BTVER2-NEXT: retl # sched: [4:1.00]
; BTVER2-NEXT: retl $4095 # imm = 0xFFF
; BTVER2-NEXT: # sched: [4:1.00]
; BTVER2-NEXT: lretl # sched: [4:1.00]
; BTVER2-NEXT: lretl $4095 # imm = 0xFFF
; BTVER2-NEXT: # sched: [4:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_ret:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
; ZNVER1-NEXT: retl $4095 # imm = 0xFFF
; ZNVER1-NEXT: # sched: [5:0.50]
; ZNVER1-NEXT: lretl # sched: [1:0.50]
; ZNVER1-NEXT: lretl $4095 # imm = 0xFFF
; ZNVER1-NEXT: # sched: [5:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
call void asm sideeffect "ret \0A\09 ret $0 \0A\09 lret \0A\09 lret $0", "i"(i16 4095)
ret void
}
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
define i8 @test_salc() optsize {
; GENERIC-LABEL: test_salc:
; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP
; GENERIC-NEXT: salc
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_salc:
; ATOM: # %bb.0:
; ATOM-NEXT: #APP
[X86] Tag SALC instructions scheduler class Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
2017-12-08 00:07:06 +08:00
; ATOM-NEXT: salc # sched: [1:0.50]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_salc:
; SLM: # %bb.0:
; SLM-NEXT: #APP
[X86] Tag SALC instructions scheduler class Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
2017-12-08 00:07:06 +08:00
; SLM-NEXT: salc # sched: [1:0.50]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_salc:
; SANDY: # %bb.0:
; SANDY-NEXT: #APP
[X86] Tag SALC instructions scheduler class Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
2017-12-08 00:07:06 +08:00
; SANDY-NEXT: salc # sched: [1:0.33]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
;
; HASWELL-LABEL: test_salc:
; HASWELL: # %bb.0:
; HASWELL-NEXT: #APP
[X86] Tag SALC instructions scheduler class Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
2017-12-08 00:07:06 +08:00
; HASWELL-NEXT: salc # sched: [1:0.25]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
; HASWELL-NEXT: #NO_APP
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget. Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
2017-12-08 17:48:44 +08:00
; HASWELL-NEXT: retl # sched: [7:1.00]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
;
; BROADWELL-LABEL: test_salc:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: #APP
[X86] Tag SALC instructions scheduler class Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
2017-12-08 00:07:06 +08:00
; BROADWELL-NEXT: salc # sched: [1:0.25]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_salc:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: #APP
[X86] Tag SALC instructions scheduler class Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
2017-12-08 00:07:06 +08:00
; SKYLAKE-NEXT: salc # sched: [1:0.25]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_salc:
; SKX: # %bb.0:
; SKX-NEXT: #APP
[X86] Tag SALC instructions scheduler class Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
2017-12-08 00:07:06 +08:00
; SKX-NEXT: salc # sched: [1:0.25]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_salc:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
[X86] Tag SALC instructions scheduler class Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
2017-12-08 00:07:06 +08:00
; BTVER2-NEXT: salc # sched: [1:0.50]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_salc:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: #APP
[X86] Tag SALC instructions scheduler class Treat these the same as LAHF/SAHF (although its not a x86_64 instruction) llvm-svn: 320055
2017-12-08 00:07:06 +08:00
; ZNVER1-NEXT: salc # sched: [1:0.25]
[X86] Add SALC scheduling test llvm-svn: 320052
2017-12-07 23:46:58 +08:00
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
%1 = tail call i8 asm "salc", "=r"() nounwind
ret i8 %1
}
[X86] Add XCHG schedule tests llvm-svn: 320586
2017-12-13 23:02:10 +08:00
[X86] Added missing AAD/AAM immediate schedule tests Added some more TODOs for missing instructions llvm-svn: 329626
2018-04-10 05:46:57 +08:00
; TODO - test_sgdt
; TODO - test_sidt
[X86] Add XCHG schedule tests llvm-svn: 320586
2017-12-13 23:02:10 +08:00
define void @test_xchg_32(i32 %a0, i32 %a1, i32 *%a2) optsize {
; GENERIC-LABEL: test_xchg_32:
; GENERIC: # %bb.0:
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %eax
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
; GENERIC-NEXT: movl {{[0-9]+}}(%esp), %edx
; GENERIC-NEXT: #APP
; GENERIC-NEXT: xchgl %eax, %eax
; GENERIC-NEXT: xchgl %ecx, %eax
; GENERIC-NEXT: xchgl %eax, (%edx)
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retl
;
; ATOM-LABEL: test_xchg_32:
; ATOM: # %bb.0:
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [1:1.00]
; ATOM-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [1:1.00]
; ATOM-NEXT: #APP
; ATOM-NEXT: xchgl %eax, %eax # sched: [2:1.00]
; ATOM-NEXT: xchgl %ecx, %eax # sched: [2:1.00]
; ATOM-NEXT: xchgl %eax, (%edx) # sched: [3:1.50]
; ATOM-NEXT: #NO_APP
; ATOM-NEXT: retl # sched: [79:39.50]
;
; SLM-LABEL: test_xchg_32:
; SLM: # %bb.0:
; SLM-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [3:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [3:1.00]
; SLM-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [3:1.00]
; SLM-NEXT: #APP
; SLM-NEXT: xchgl %eax, %eax # sched: [1:0.50]
; SLM-NEXT: xchgl %ecx, %eax # sched: [1:0.50]
; SLM-NEXT: xchgl %eax, (%edx) # sched: [4:2.00]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
; SANDY-LABEL: test_xchg_32:
; SANDY: # %bb.0:
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SANDY-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
; SANDY-NEXT: #APP
[X86] Correct the scheduling data for register forms of XCHG and XADD on Intel CPUs. The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register. XADD is probably 2 moves and an add also using a temporary register. Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available. llvm-svn: 330349
2018-04-20 02:00:17 +08:00
; SANDY-NEXT: xchgl %eax, %eax # sched: [2:1.00]
; SANDY-NEXT: xchgl %ecx, %eax # sched: [2:1.00]
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: xchgl %eax, (%edx) # sched: [6:1.00]
[X86] Add XCHG schedule tests llvm-svn: 320586
2017-12-13 23:02:10 +08:00
; SANDY-NEXT: #NO_APP
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
2018-04-06 19:00:51 +08:00
; SANDY-NEXT: retl # sched: [6:1.00]
[X86] Add XCHG schedule tests llvm-svn: 320586
2017-12-13 23:02:10 +08:00
;
; HASWELL-LABEL: test_xchg_32:
; HASWELL: # %bb.0:
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; HASWELL-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
; HASWELL-NEXT: #APP
[X86] Correct the scheduling data for register forms of XCHG and XADD on Intel CPUs. The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register. XADD is probably 2 moves and an add also using a temporary register. Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available. llvm-svn: 330349
2018-04-20 02:00:17 +08:00
; HASWELL-NEXT: xchgl %eax, %eax # sched: [2:0.75]
; HASWELL-NEXT: xchgl %ecx, %eax # sched: [2:0.75]
[X86] Add XCHG schedule tests llvm-svn: 320586
2017-12-13 23:02:10 +08:00
; HASWELL-NEXT: xchgl %eax, (%edx) # sched: [9:1.00]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_xchg_32:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; BROADWELL-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
; BROADWELL-NEXT: #APP
[X86] Correct the scheduling data for register forms of XCHG and XADD on Intel CPUs. The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register. XADD is probably 2 moves and an add also using a temporary register. Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available. llvm-svn: 330349
2018-04-20 02:00:17 +08:00
; BROADWELL-NEXT: xchgl %eax, %eax # sched: [2:0.75]
; BROADWELL-NEXT: xchgl %ecx, %eax # sched: [2:0.75]
[X86] Add XCHG schedule tests llvm-svn: 320586
2017-12-13 23:02:10 +08:00
; BROADWELL-NEXT: xchgl %eax, (%edx) # sched: [8:1.00]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_xchg_32:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKYLAKE-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
; SKYLAKE-NEXT: #APP
[X86] Correct the scheduling data for register forms of XCHG and XADD on Intel CPUs. The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register. XADD is probably 2 moves and an add also using a temporary register. Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available. llvm-svn: 330349
2018-04-20 02:00:17 +08:00
; SKYLAKE-NEXT: xchgl %eax, %eax # sched: [2:0.75]
; SKYLAKE-NEXT: xchgl %ecx, %eax # sched: [2:0.75]
[X86] Add XCHG schedule tests llvm-svn: 320586
2017-12-13 23:02:10 +08:00
; SKYLAKE-NEXT: xchgl %eax, (%edx) # sched: [10:1.25]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_xchg_32:
; SKX: # %bb.0:
; SKX-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:0.50]
; SKX-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:0.50]
; SKX-NEXT: #APP
[X86] Correct the scheduling data for register forms of XCHG and XADD on Intel CPUs. The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register. XADD is probably 2 moves and an add also using a temporary register. Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available. llvm-svn: 330349
2018-04-20 02:00:17 +08:00
; SKX-NEXT: xchgl %eax, %eax # sched: [2:0.75]
; SKX-NEXT: xchgl %ecx, %eax # sched: [2:0.75]
[X86] Add XCHG schedule tests llvm-svn: 320586
2017-12-13 23:02:10 +08:00
; SKX-NEXT: xchgl %eax, (%edx) # sched: [10:1.25]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
; BTVER2-LABEL: test_xchg_32:
; BTVER2: # %bb.0:
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [5:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [5:1.00]
; BTVER2-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [5:1.00]
; BTVER2-NEXT: #APP
; BTVER2-NEXT: xchgl %eax, %eax # sched: [1:0.50]
; BTVER2-NEXT: xchgl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: xchgl %eax, (%edx) # sched: [4:1.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
; ZNVER1-LABEL: test_xchg_32:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: xchgl %eax, %eax # sched: [1:0.50]
; ZNVER1-NEXT: xchgl %ecx, %eax # sched: [1:0.50]
; ZNVER1-NEXT: xchgl %eax, (%edx) # sched: [5:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
tail call void asm "xchg %EAX, $0 \0A\09 xchg $1, $0 \0A\09 xchg $2, $0", "r,r,*m"(i32 %a0, i32 %a1, i32 *%a2) nounwind
ret void
}