2017-08-02 08:28:10 +08:00
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; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=X64
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=X32
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2014-09-26 01:27:43 +08:00
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; On x86, an atomic rmw operation that does not modify the value in memory
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; (such as atomic add 0) can be replaced by an mfence followed by a mov.
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; This is explained (with the motivation for such an optimization) in
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; http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
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define i8 @add8(i8* %p) {
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; CHECK-LABEL: add8
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; CHECK: mfence
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; CHECK: movb
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%1 = atomicrmw add i8* %p, i8 0 monotonic
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ret i8 %1
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}
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define i16 @or16(i16* %p) {
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; CHECK-LABEL: or16
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; CHECK: mfence
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; CHECK: movw
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%1 = atomicrmw or i16* %p, i16 0 acquire
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ret i16 %1
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}
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define i32 @xor32(i32* %p) {
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; CHECK-LABEL: xor32
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; CHECK: mfence
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; CHECK: movl
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%1 = atomicrmw xor i32* %p, i32 0 release
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ret i32 %1
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}
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define i64 @sub64(i64* %p) {
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; CHECK-LABEL: sub64
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; X64: mfence
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; X64: movq
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; X32-NOT: mfence
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%1 = atomicrmw sub i64* %p, i64 0 seq_cst
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ret i64 %1
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}
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define i128 @or128(i128* %p) {
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; CHECK-LABEL: or128
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; CHECK-NOT: mfence
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%1 = atomicrmw or i128* %p, i128 0 monotonic
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ret i128 %1
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}
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; For 'and', the idempotent value is (-1)
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define i32 @and32 (i32* %p) {
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; CHECK-LABEL: and32
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; CHECK: mfence
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; CHECK: movl
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%1 = atomicrmw and i32* %p, i32 -1 acq_rel
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ret i32 %1
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}
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