2015-06-30 07:51:55 +08:00
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//=- WebAssemblyInstrInfo.h - WebAssembly Instruction Information -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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2018-05-01 23:54:18 +08:00
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/// This file contains the WebAssembly implementation of the
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2015-06-30 07:51:55 +08:00
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/// TargetInstrInfo class.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
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#include "WebAssemblyRegisterInfo.h"
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2017-11-08 09:01:31 +08:00
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#include "llvm/CodeGen/TargetInstrInfo.h"
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2015-06-30 07:51:55 +08:00
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2015-07-23 05:28:15 +08:00
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#define GET_INSTRINFO_HEADER
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#include "WebAssemblyGenInstrInfo.inc"
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2015-06-30 07:51:55 +08:00
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namespace llvm {
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class WebAssemblySubtarget;
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2015-07-23 05:28:15 +08:00
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class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo {
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2015-06-30 07:51:55 +08:00
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const WebAssemblyRegisterInfo RI;
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public:
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explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI);
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const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
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2015-09-09 08:52:47 +08:00
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2016-06-30 08:01:54 +08:00
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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2016-01-20 00:59:23 +08:00
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AliasAnalysis *AA) const override;
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2015-09-09 08:52:47 +08:00
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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2016-06-12 23:39:02 +08:00
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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2015-09-09 08:52:47 +08:00
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bool KillSrc) const override;
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2016-06-30 08:01:54 +08:00
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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2016-01-28 09:22:44 +08:00
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unsigned OpIdx1,
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unsigned OpIdx2) const override;
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2015-09-17 00:51:30 +08:00
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2016-07-15 22:41:04 +08:00
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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2015-09-17 00:51:30 +08:00
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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2016-09-15 04:43:16 +08:00
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unsigned removeBranch(MachineBasicBlock &MBB,
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2016-09-15 01:23:48 +08:00
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int *BytesRemoved = nullptr) const override;
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2016-09-15 01:24:15 +08:00
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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2015-11-30 06:32:02 +08:00
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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2016-09-15 01:23:48 +08:00
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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2015-09-17 00:51:30 +08:00
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bool
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2016-09-15 04:43:16 +08:00
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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2015-06-30 07:51:55 +08:00
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};
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} // end namespace llvm
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#endif
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