2018-07-16 23:42:20 +08:00
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# REQUIRES: asserts
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# RUN: llc -mtriple=x86_64-- -run-pass=greedy %s -debug-only=regalloc -huge-size-for-split=0 -o /dev/null 2>&1 | FileCheck %s
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# Check no global region split is needed because the live range to split is trivially rematerializable.
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# CHECK-NOT: Compact region bundles
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--- |
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; ModuleID = '<stdin>'
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source_filename = "2.cc"
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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@m = local_unnamed_addr global i32 0, align 4
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@.str = private unnamed_addr constant [4 x i8] c"abc\00", align 1
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@.str.1 = private unnamed_addr constant [4 x i8] c"def\00", align 1
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@.str.2 = private unnamed_addr constant [4 x i8] c"ghi\00", align 1
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; Function Attrs: uwtable
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define void @_Z3fooi(i32 %value) local_unnamed_addr #0 {
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entry:
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br label %do.body
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do.body: ; preds = %do.cond, %entry
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tail call void asm sideeffect "", "~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"() #2, !srcloc !3
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switch i32 %value, label %do.cond [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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]
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sw.bb: ; preds = %do.body
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tail call void @_Z3gooPKc(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0))
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br label %sw.bb1
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sw.bb1: ; preds = %sw.bb, %do.body
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tail call void @_Z3gooPKc(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.1, i64 0, i64 0))
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br label %sw.bb2
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sw.bb2: ; preds = %sw.bb1, %do.body
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tail call void @_Z3gooPKc(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.2, i64 0, i64 0))
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br label %do.cond
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do.cond: ; preds = %sw.bb2, %do.body
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%0 = load i32, i32* @m, align 4, !tbaa !4
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%cmp = icmp eq i32 %0, 5
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br i1 %cmp, label %do.end, label %do.body
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do.end: ; preds = %do.cond
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ret void
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}
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declare void @_Z3gooPKc(i8*) local_unnamed_addr #1
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #2
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2019-12-25 08:11:33 +08:00
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attributes #0 = { uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
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2018-07-16 23:42:20 +08:00
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attributes #2 = { nounwind }
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!llvm.module.flags = !{!0, !1}
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!llvm.ident = !{!2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 7, !"PIC Level", i32 2}
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!2 = !{!"clang version 7.0.0 (trunk 335057)"}
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!3 = !{i32 80}
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!4 = !{!5, !5, i64 0}
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!5 = !{!"int", !6, i64 0}
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!6 = !{!"omnipotent char", !7, i64 0}
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!7 = !{!"Simple C++ TBAA"}
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...
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---
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name: _Z3fooi
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[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
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alignment: 16
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2018-07-16 23:42:20 +08:00
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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- { id: 1, class: gr32 }
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- { id: 2, class: gr32 }
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- { id: 3, class: gr64 }
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- { id: 4, class: gr64 }
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- { id: 5, class: gr64 }
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- { id: 6, class: gr64 }
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- { id: 7, class: gr32 }
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- { id: 8, class: gr32 }
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liveins:
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- { reg: '$edi', virtual-reg: '%0' }
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frameInfo:
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hasCalls: true
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body: |
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bb.0.entry:
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liveins: $edi
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%0:gr32 = COPY $edi
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%5:gr64 = LEA64r $rip, 1, $noreg, @.str.2, $noreg
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%6:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @m, $noreg :: (load 8 from got)
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%4:gr64 = LEA64r $rip, 1, $noreg, @.str.1, $noreg
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%3:gr64 = LEA64r $rip, 1, $noreg, @.str, $noreg
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bb.1.do.body:
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successors: %bb.6(0x20000000), %bb.2(0x60000000)
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INLINEASM &"", 1, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15, 12, implicit-def dead early-clobber $eflags, !3
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CMP32ri8 %0, 2, implicit-def $eflags
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
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JCC_1 %bb.6, 4, implicit killed $eflags
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2018-07-16 23:42:20 +08:00
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JMP_1 %bb.2
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bb.2.do.body:
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successors: %bb.5(0x2aaaaaab), %bb.3(0x55555555)
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CMP32ri8 %0, 1, implicit-def $eflags
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
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JCC_1 %bb.5, 4, implicit killed $eflags
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2018-07-16 23:42:20 +08:00
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JMP_1 %bb.3
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bb.3.do.body:
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successors: %bb.4, %bb.7
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TEST32rr %0, %0, implicit-def $eflags
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
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JCC_1 %bb.7, 5, implicit killed $eflags
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2018-07-16 23:42:20 +08:00
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JMP_1 %bb.4
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bb.4.sw.bb:
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ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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$rdi = COPY %3
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CALL64pcrel32 target-flags(x86-plt) @_Z3gooPKc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp
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ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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bb.5.sw.bb1:
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ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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$rdi = COPY %4
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CALL64pcrel32 target-flags(x86-plt) @_Z3gooPKc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp
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ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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bb.6.sw.bb2:
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ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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$rdi = COPY %5
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CALL64pcrel32 target-flags(x86-plt) @_Z3gooPKc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp
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ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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bb.7.do.cond:
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successors: %bb.8(0x04000000), %bb.1(0x7c000000)
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CMP32mi8 %6, 1, $noreg, 0, $noreg, 5, implicit-def $eflags :: (dereferenceable load 4 from @m, !tbaa !4)
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
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JCC_1 %bb.1, 5, implicit killed $eflags
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2018-07-16 23:42:20 +08:00
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JMP_1 %bb.8
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bb.8.do.end:
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RET 0
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...
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