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llvm-project/llvm/test/CodeGen/PowerPC/rlwimi-and-or-bits.ll

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Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
[PowerPC] Fix and(or(x, c1), c2) -> rlwimi generation PPCISelDAGToDAG has a transformation that generates a rlwimi instruction from an input pattern that looks like this: and(or(x, c1), c2) but the associated logic does not work if there are bits that are 1 in c1 but 0 in c2 (these are normally canonicalized away, but that can't happen if the 'or' has other users. Make sure we abort the transformation if such bits are discovered. Fixes PR24704. llvm-svn: 246900
2015-09-05 08:02:59 +08:00
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@m = external global i32, align 4
; Function Attrs: nounwind
define signext i32 @main() #0 {
entry:
; CHECK-LABEL: @main
; CHECK-NOT: rlwimi
; CHECK: andi
%0 = load i32, i32* @m, align 4
%or = or i32 %0, 250
store i32 %or, i32* @m, align 4
%and = and i32 %or, 249
%sub.i = sub i32 %and, 0
%sext = shl i32 %sub.i, 24
%conv = ashr exact i32 %sext, 24
ret i32 %conv
}
attributes #0 = { nounwind "target-cpu"="pwr7" }
attributes #1 = { nounwind }