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llvm-project/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll

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Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s -check-prefix=FPCVT
; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s -check-prefix=PPC64
[PowerPC] Improve int_to_fp(fp_to_int(x)) combining The old target DAG combine that allowed for performing int_to_fp(fp_to_int(x)) without a load/store pair is updated here with support for unsigned integers, and to support single-precision values without a third rounding step, on newer cores with the appropriate instructions. llvm-svn: 225248
2015-01-06 14:01:57 +08:00
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone
define float @fool(float %X) #0 {
entry:
%conv = fptosi float %X to i64
%conv1 = sitofp i64 %conv to float
ret float %conv1
; FPCVT-LABEL: @fool
[DAGCombine] (float)((int) f) --> ftrunc (PR36617) fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC, so replace a pair of casts with the equivalent node. We don't have to account for special cases (NaN, INF) because out-of-range casts are undefined. Differential Revision: https://reviews.llvm.org/D44909 llvm-svn: 328921
2018-04-01 01:55:44 +08:00
; FPCVT: friz 1, 1
[PowerPC] Improve int_to_fp(fp_to_int(x)) combining The old target DAG combine that allowed for performing int_to_fp(fp_to_int(x)) without a load/store pair is updated here with support for unsigned integers, and to support single-precision values without a third rounding step, on newer cores with the appropriate instructions. llvm-svn: 225248
2015-01-06 14:01:57 +08:00
; FPCVT: blr
; PPC64-LABEL: @fool
; PPC64: fctidz [[REG1:[0-9]+]], 1
; PPC64: fcfid [[REG2:[0-9]+]], [[REG1]]
; PPC64: frsp 1, [[REG2]]
; PPC64: blr
}
; Function Attrs: nounwind readnone
define double @foodl(double %X) #0 {
entry:
%conv = fptosi double %X to i64
%conv1 = sitofp i64 %conv to double
ret double %conv1
; FPCVT-LABEL: @foodl
[DAGCombine] (float)((int) f) --> ftrunc (PR36617) fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC, so replace a pair of casts with the equivalent node. We don't have to account for special cases (NaN, INF) because out-of-range casts are undefined. Differential Revision: https://reviews.llvm.org/D44909 llvm-svn: 328921
2018-04-01 01:55:44 +08:00
; FPCVT: friz 1, 1
[PowerPC] Improve int_to_fp(fp_to_int(x)) combining The old target DAG combine that allowed for performing int_to_fp(fp_to_int(x)) without a load/store pair is updated here with support for unsigned integers, and to support single-precision values without a third rounding step, on newer cores with the appropriate instructions. llvm-svn: 225248
2015-01-06 14:01:57 +08:00
; FPCVT: blr
; PPC64-LABEL: @foodl
; PPC64: fctidz [[REG1:[0-9]+]], 1
; PPC64: fcfid 1, [[REG1]]
; PPC64: blr
}
; Function Attrs: nounwind readnone
define float @fooul(float %X) #0 {
entry:
%conv = fptoui float %X to i64
%conv1 = uitofp i64 %conv to float
ret float %conv1
; FPCVT-LABEL: @fooul
[DAGCombine] (float)((int) f) --> ftrunc (PR36617) fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC, so replace a pair of casts with the equivalent node. We don't have to account for special cases (NaN, INF) because out-of-range casts are undefined. Differential Revision: https://reviews.llvm.org/D44909 llvm-svn: 328921
2018-04-01 01:55:44 +08:00
; FPCVT: friz 1, 1
[PowerPC] Improve int_to_fp(fp_to_int(x)) combining The old target DAG combine that allowed for performing int_to_fp(fp_to_int(x)) without a load/store pair is updated here with support for unsigned integers, and to support single-precision values without a third rounding step, on newer cores with the appropriate instructions. llvm-svn: 225248
2015-01-06 14:01:57 +08:00
; FPCVT: blr
}
; Function Attrs: nounwind readnone
define double @fooudl(double %X) #0 {
entry:
%conv = fptoui double %X to i64
%conv1 = uitofp i64 %conv to double
ret double %conv1
; FPCVT-LABEL: @fooudl
[DAGCombine] (float)((int) f) --> ftrunc (PR36617) fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC, so replace a pair of casts with the equivalent node. We don't have to account for special cases (NaN, INF) because out-of-range casts are undefined. Differential Revision: https://reviews.llvm.org/D44909 llvm-svn: 328921
2018-04-01 01:55:44 +08:00
; FPCVT: friz 1, 1
[PowerPC] Improve int_to_fp(fp_to_int(x)) combining The old target DAG combine that allowed for performing int_to_fp(fp_to_int(x)) without a load/store pair is updated here with support for unsigned integers, and to support single-precision values without a third rounding step, on newer cores with the appropriate instructions. llvm-svn: 225248
2015-01-06 14:01:57 +08:00
; FPCVT: blr
}
attributes #0 = { nounwind readnone }