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llvm-project/llvm/test/CodeGen/ARM/crash-on-pow2-shufflevector.ll

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[DAGCombiner] Fix an off-by-one error in vector logic Without this, we could end up trying to get the Nth (0-indexed) element from a subvector of size N. Differential Revision: https://reviews.llvm.org/D37880 llvm-svn: 314380
2017-09-28 14:17:19 +08:00
; RUN: llc < %s -mtriple=armv7 | FileCheck %s
;
; Ensure that don't crash given a largeish power-of-two shufflevector index.
%struct.desc = type { i32, [7 x i32] }
define i32 @foo(%struct.desc* %descs, i32 %num, i32 %cw) local_unnamed_addr #0 {
; CHECK-LABEL: foo:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: @ %bb.0: @ %entry
[DAGCombiner] Fix an off-by-one error in vector logic Without this, we could end up trying to get the Nth (0-indexed) element from a subvector of size N. Differential Revision: https://reviews.llvm.org/D37880 llvm-svn: 314380
2017-09-28 14:17:19 +08:00
; CHECK-NEXT: mov r1, #32
; CHECK-NEXT: vld1.32 {d16, d17}, [r0], r1
; CHECK-NEXT: vld1.32 {d18, d19}, [r0]
; CHECK-NEXT: vtrn.32 q8, q9
; CHECK-NEXT: vadd.i32 d16, d16, d16
; CHECK-NEXT: vmov.32 r0, d16[1]
; CHECK-NEXT: bx lr
entry:
%descs.vec = bitcast %struct.desc* %descs to <16 x i32>*
%wide.vec = load <16 x i32>, <16 x i32>* %descs.vec, align 4
%strided.vec = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <2 x i32> <i32 0, i32 8>
%bin.rdx20 = add <2 x i32> %strided.vec, %strided.vec
%0 = extractelement <2 x i32> %bin.rdx20, i32 1
ret i32 %0
}