forked from OSchip/llvm-project
41 lines
1.4 KiB
LLVM
41 lines
1.4 KiB
LLVM
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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; Use bar.sync to arrive at a pre-computed barrier number and
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; wait for all threads in CTA to also arrive:
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define ptx_device void @test_barrier_named_cta() {
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; CHECK: mov.u32 %r[[REG0:[0-9]+]], 0;
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; CHECK: bar.sync %r[[REG0]];
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; CHECK: mov.u32 %r[[REG1:[0-9]+]], 10;
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; CHECK: bar.sync %r[[REG1]];
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; CHECK: mov.u32 %r[[REG2:[0-9]+]], 15;
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; CHECK: bar.sync %r[[REG2]];
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; CHECK: ret;
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call void @llvm.nvvm.barrier.n(i32 0)
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call void @llvm.nvvm.barrier.n(i32 10)
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call void @llvm.nvvm.barrier.n(i32 15)
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ret void
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}
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; Use bar.sync to arrive at a pre-computed barrier number and
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; wait for fixed number of cooperating threads to arrive:
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define ptx_device void @test_barrier_named() {
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; CHECK: mov.u32 %r[[REG0A:[0-9]+]], 32;
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; CHECK: mov.u32 %r[[REG0B:[0-9]+]], 0;
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; CHECK: bar.sync %r[[REG0B]], %r[[REG0A]];
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; CHECK: mov.u32 %r[[REG1A:[0-9]+]], 352;
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; CHECK: mov.u32 %r[[REG1B:[0-9]+]], 10;
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; CHECK: bar.sync %r[[REG1B]], %r[[REG1A]];
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; CHECK: mov.u32 %r[[REG2A:[0-9]+]], 992;
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; CHECK: mov.u32 %r[[REG2B:[0-9]+]], 15;
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; CHECK: bar.sync %r[[REG2B]], %r[[REG2A]];
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; CHECK: ret;
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call void @llvm.nvvm.barrier(i32 0, i32 32)
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call void @llvm.nvvm.barrier(i32 10, i32 352)
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call void @llvm.nvvm.barrier(i32 15, i32 992)
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ret void
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}
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declare void @llvm.nvvm.barrier(i32, i32)
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declare void @llvm.nvvm.barrier.n(i32)
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