forked from OSchip/llvm-project
34 lines
1.2 KiB
LLVM
34 lines
1.2 KiB
LLVM
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=sse4.1 -o /dev/null
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; Testcase for PR31593.
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; Revision r291120 introduced a regression and this test started failing
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; because of a 'fatal error in the backend':
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; Cannot select: t14: v2i64 = zero_extend_vector_inreg t18
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; t18: v4i32 = bitcast t17
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; t17: v2i64,ch = load<LD16[%0](dereferenceable)> t0, FrameIndex:i64<1>, undef:i64
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; t1: i64 = FrameIndex<1>
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; t3: i64 = undef
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; In function: _Z3foov
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; This regression was fixed in r291535.
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%struct.S = type { <2 x i64> }
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declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
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define void @_Z3foov() local_unnamed_addr #2 {
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entry:
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%zero = alloca %struct.S, align 16
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%e = alloca %struct.S, align 16
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%s = alloca %struct.S, align 16
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%0 = bitcast %struct.S* %zero to i8*
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%1 = bitcast %struct.S* %e to i8*
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%2 = bitcast %struct.S* %e to <4 x i32>*
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%3 = load <4 x i32>, <4 x i32>* %2, align 16
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%vecext.i = extractelement <4 x i32> %3, i32 0
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%4 = bitcast %struct.S* %s to i8*
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%5 = bitcast %struct.S* %s to <4 x i32>*
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%6 = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 %vecext.i)
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store <4 x i32> %6, <4 x i32>* %5, align 16
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ret void
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}
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attributes #2 = { "target-features"="+sse4.1" }
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