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llvm-project/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll

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Make utils/update_llc_test_checks.py note that the assertions are autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
2015-11-24 05:33:58 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[x86] Now that the new vector shuffle legality is enabled and everything is going well, remove the flag and the code for the old legality tests. This is the first step toward removing the entire old vector shuffle lowering. *Much* more code to delete coming up next. llvm-svn: 229963
2015-02-20 11:59:35 +08:00
; RUN: llc < %s -mtriple=i686-darwin -mattr=+mmx,+sse2 | FileCheck --check-prefix=X32 %s
; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck --check-prefix=X64 %s
[x86][MMX] Rename and cleanup tests: arith, intrinsics and shuffle - Rename mmx-builtins to mmx-intrinsics to match other intrinsic test naming. - Remove tests that duplicate functionality from mmx-intrinsics.ll. - Move arith related tests to mmx-arith.ll. - MMX related shuffle goes to vector-shuffle-mmx.ll. llvm-svn: 227130
2015-01-27 04:06:51 +08:00
; If there is no explicit MMX type usage, always promote to XMM.
define void @test0(<1 x i64>* %x) {
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X32-LABEL: test0:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X32: ## %bb.0: ## %entry
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86][SSE] Add support for combining target shuffles to SHUFPS. As discussed on D27692, the next step will be to allow cross-domain shuffles once the combined shuffle depth passes a certain point. llvm-svn: 290064
2016-12-18 22:26:02 +08:00
; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
; X32-NEXT: movlps %xmm0, (%eax)
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X32-NEXT: retl
;
; X64-LABEL: test0:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: ## %bb.0: ## %entry
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
[DagCombiner] Allow shuffles to merge through bitcasts Currently shuffles may only be combined if they are of the same type, despite the fact that bitcasts are often introduced in between shuffle nodes (e.g. x86 shuffle type widening). This patch allows a single input shuffle to peek through bitcasts and if the input is another shuffle will merge them, shuffling using the smallest sized type, and re-applying the bitcasts at the inputs and output instead. Dropped old ShuffleToZext test - this patch removes the use of the zext and vector-zext.ll covers these anyhow. Differential Revision: http://reviews.llvm.org/D7939 llvm-svn: 231380
2015-03-06 01:14:04 +08:00
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X64-NEXT: movq %xmm0, (%rdi)
; X64-NEXT: retq
[x86][MMX] Rename and cleanup tests: arith, intrinsics and shuffle - Rename mmx-builtins to mmx-intrinsics to match other intrinsic test naming. - Remove tests that duplicate functionality from mmx-intrinsics.ll. - Move arith related tests to mmx-arith.ll. - MMX related shuffle goes to vector-shuffle-mmx.ll. llvm-svn: 227130
2015-01-27 04:06:51 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp2 = load <1 x i64>, <1 x i64>* %x
[x86][MMX] Rename and cleanup tests: arith, intrinsics and shuffle - Rename mmx-builtins to mmx-intrinsics to match other intrinsic test naming. - Remove tests that duplicate functionality from mmx-intrinsics.ll. - Move arith related tests to mmx-arith.ll. - MMX related shuffle goes to vector-shuffle-mmx.ll. llvm-svn: 227130
2015-01-27 04:06:51 +08:00
%tmp6 = bitcast <1 x i64> %tmp2 to <2 x i32>
%tmp9 = shufflevector <2 x i32> %tmp6, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
%tmp10 = bitcast <2 x i32> %tmp9 to <1 x i64>
store <1 x i64> %tmp10, <1 x i64>* %x
ret void
}
define void @test1() {
; X32-LABEL: test1:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X32: ## %bb.0: ## %entry
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X32-NEXT: pushl %edi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %edi, -8
[X86][MMX] Add support for MMX zero vector creation As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register. This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well. Differential Revision: https://reviews.llvm.org/D41908 llvm-svn: 322525
2018-01-16 06:32:40 +08:00
; X32-NEXT: pxor %mm0, %mm0
[X86][MMX] Improve handling of 64-bit MMX constants 64-bit MMX constant generation usually ends up lowering into SSE instructions before being spilled/reloaded as a MMX type. This patch bitcasts the constant to a double value to allow correct loading directly to the MMX register. I've added MMX constant asm comment support to improve testing, it's better to always print the double values as hex constants as MMX is mainly an integer unit (and even with 3DNow! its just floats). Differential Revision: https://reviews.llvm.org/D43616 llvm-svn: 326497
2018-03-02 06:22:31 +08:00
; X32-NEXT: movq LCPI1_0, %mm1 ## mm1 = 0x7070606040400000
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X32-NEXT: xorl %edi, %edi
; X32-NEXT: maskmovq %mm1, %mm0
; X32-NEXT: popl %edi
; X32-NEXT: retl
;
; X64-LABEL: test1:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: ## %bb.0: ## %entry
[X86][MMX] Add support for MMX zero vector creation As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register. This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well. Differential Revision: https://reviews.llvm.org/D41908 llvm-svn: 322525
2018-01-16 06:32:40 +08:00
; X64-NEXT: pxor %mm0, %mm0
[X86][MMX] Improve handling of 64-bit MMX constants 64-bit MMX constant generation usually ends up lowering into SSE instructions before being spilled/reloaded as a MMX type. This patch bitcasts the constant to a double value to allow correct loading directly to the MMX register. I've added MMX constant asm comment support to improve testing, it's better to always print the double values as hex constants as MMX is mainly an integer unit (and even with 3DNow! its just floats). Differential Revision: https://reviews.llvm.org/D43616 llvm-svn: 326497
2018-03-02 06:22:31 +08:00
; X64-NEXT: movq {{.*}}(%rip), %mm1 ## mm1 = 0x7070606040400000
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X64-NEXT: xorl %edi, %edi
; X64-NEXT: maskmovq %mm1, %mm0
; X64-NEXT: retq
[x86][MMX] Rename and cleanup tests: arith, intrinsics and shuffle - Rename mmx-builtins to mmx-intrinsics to match other intrinsic test naming. - Remove tests that duplicate functionality from mmx-intrinsics.ll. - Move arith related tests to mmx-arith.ll. - MMX related shuffle goes to vector-shuffle-mmx.ll. llvm-svn: 227130
2015-01-27 04:06:51 +08:00
entry:
%tmp528 = bitcast <8 x i8> zeroinitializer to <2 x i32>
%tmp529 = and <2 x i32> %tmp528, bitcast (<4 x i16> < i16 -32640, i16 16448, i16 8224, i16 4112 > to <2 x i32>)
%tmp542 = bitcast <2 x i32> %tmp529 to <4 x i16>
%tmp543 = add <4 x i16> %tmp542, < i16 0, i16 16448, i16 24672, i16 28784 >
%tmp555 = bitcast <4 x i16> %tmp543 to <8 x i8>
%tmp556 = bitcast <8 x i8> %tmp555 to x86_mmx
%tmp557 = bitcast <8 x i8> zeroinitializer to x86_mmx
tail call void @llvm.x86.mmx.maskmovq( x86_mmx %tmp557, x86_mmx %tmp556, i8* null)
ret void
}
[X86][MMX] Cleanup shuffle, bitcast and insert element tests - Merge MMX arg passing test files - Merge MMX bitcast, insert elt and shuffle tests llvm-svn: 227867
2015-02-03 05:56:11 +08:00
@tmp_V2i = common global <2 x i32> zeroinitializer
define void @test2() nounwind {
; X32-LABEL: test2:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X32: ## %bb.0: ## %entry
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X32-NEXT: movl L_tmp_V2i$non_lazy_ptr, %eax
; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
[DagCombiner] Allow shuffles to merge through bitcasts Currently shuffles may only be combined if they are of the same type, despite the fact that bitcasts are often introduced in between shuffle nodes (e.g. x86 shuffle type widening). This patch allows a single input shuffle to peek through bitcasts and if the input is another shuffle will merge them, shuffling using the smallest sized type, and re-applying the bitcasts at the inputs and output instead. Dropped old ShuffleToZext test - this patch removes the use of the zext and vector-zext.ll covers these anyhow. Differential Revision: http://reviews.llvm.org/D7939 llvm-svn: 231380
2015-03-06 01:14:04 +08:00
; X32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0,0,1,1]
; X32-NEXT: movlps %xmm0, (%eax)
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X32-NEXT: retl
;
; X64-LABEL: test2:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: ## %bb.0: ## %entry
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X64-NEXT: movq _tmp_V2i@{{.*}}(%rip), %rax
; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
[DagCombiner] Allow shuffles to merge through bitcasts Currently shuffles may only be combined if they are of the same type, despite the fact that bitcasts are often introduced in between shuffle nodes (e.g. x86 shuffle type widening). This patch allows a single input shuffle to peek through bitcasts and if the input is another shuffle will merge them, shuffling using the smallest sized type, and re-applying the bitcasts at the inputs and output instead. Dropped old ShuffleToZext test - this patch removes the use of the zext and vector-zext.ll covers these anyhow. Differential Revision: http://reviews.llvm.org/D7939 llvm-svn: 231380
2015-03-06 01:14:04 +08:00
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
[x86] Teach my test updating script about another quirk of the printed asm and port the mmx vector shuffle test to it. Not thrilled with how it handles the stack manipulation logic, but I'm much less bothered by that than I am by updating the test manually. =] If anyone wants to teach the test checks management script about stack adjustment patterns, that'd be cool too. llvm-svn: 229268
2015-02-15 08:08:01 +08:00
; X64-NEXT: movq %xmm0, (%rax)
; X64-NEXT: retq
[X86][MMX] Cleanup shuffle, bitcast and insert element tests - Merge MMX arg passing test files - Merge MMX bitcast, insert elt and shuffle tests llvm-svn: 227867
2015-02-03 05:56:11 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load <2 x i32>, <2 x i32>* @tmp_V2i, align 8
[X86][MMX] Cleanup shuffle, bitcast and insert element tests - Merge MMX arg passing test files - Merge MMX bitcast, insert elt and shuffle tests llvm-svn: 227867
2015-02-03 05:56:11 +08:00
%1 = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer
store <2 x i32> %1, <2 x i32>* @tmp_V2i, align 8
ret void
}
[X86][MMX] Add test for PR35869 llvm-svn: 322197
2018-01-11 01:05:03 +08:00
define <4 x float> @pr35869() nounwind {
; X32-LABEL: pr35869:
; X32: ## %bb.0:
; X32-NEXT: movl $64, %eax
[X86][MMX] Improve MMX constant generation Extend the MMX zero code to take any constant with zero'd upper 32-bits llvm-svn: 322553
2018-01-16 22:21:28 +08:00
; X32-NEXT: movd %eax, %mm0
[X86][MMX] Add support for MMX zero vector creation As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register. This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well. Differential Revision: https://reviews.llvm.org/D41908 llvm-svn: 322525
2018-01-16 06:32:40 +08:00
; X32-NEXT: pxor %mm1, %mm1
; X32-NEXT: punpcklbw %mm1, %mm0 ## mm0 = mm0[0],mm1[0],mm0[1],mm1[1],mm0[2],mm1[2],mm0[3],mm1[3]
[X86][MMX] Add test for PR35869 llvm-svn: 322197
2018-01-11 01:05:03 +08:00
; X32-NEXT: pcmpgtw %mm0, %mm1
; X32-NEXT: movq %mm0, %mm2
; X32-NEXT: punpckhwd %mm1, %mm2 ## mm2 = mm2[2],mm1[2],mm2[3],mm1[3]
[X86][MMX] Improve MMX constant generation Extend the MMX zero code to take any constant with zero'd upper 32-bits llvm-svn: 322553
2018-01-16 22:21:28 +08:00
; X32-NEXT: xorps %xmm0, %xmm0
[X86][MMX] Add test for PR35869 llvm-svn: 322197
2018-01-11 01:05:03 +08:00
; X32-NEXT: cvtpi2ps %mm2, %xmm0
; X32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
; X32-NEXT: punpcklwd %mm1, %mm0 ## mm0 = mm0[0],mm1[0],mm0[1],mm1[1]
; X32-NEXT: cvtpi2ps %mm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: pr35869:
; X64: ## %bb.0:
; X64-NEXT: movl $64, %eax
[X86][MMX] Improve MMX constant generation Extend the MMX zero code to take any constant with zero'd upper 32-bits llvm-svn: 322553
2018-01-16 22:21:28 +08:00
; X64-NEXT: movd %eax, %mm0
[X86][MMX] Add support for MMX zero vector creation As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register. This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well. Differential Revision: https://reviews.llvm.org/D41908 llvm-svn: 322525
2018-01-16 06:32:40 +08:00
; X64-NEXT: pxor %mm1, %mm1
; X64-NEXT: punpcklbw %mm1, %mm0 ## mm0 = mm0[0],mm1[0],mm0[1],mm1[1],mm0[2],mm1[2],mm0[3],mm1[3]
[X86][MMX] Add test for PR35869 llvm-svn: 322197
2018-01-11 01:05:03 +08:00
; X64-NEXT: pcmpgtw %mm0, %mm1
; X64-NEXT: movq %mm0, %mm2
; X64-NEXT: punpckhwd %mm1, %mm2 ## mm2 = mm2[2],mm1[2],mm2[3],mm1[3]
[X86][MMX] Improve MMX constant generation Extend the MMX zero code to take any constant with zero'd upper 32-bits llvm-svn: 322553
2018-01-16 22:21:28 +08:00
; X64-NEXT: xorps %xmm0, %xmm0
[X86][MMX] Add test for PR35869 llvm-svn: 322197
2018-01-11 01:05:03 +08:00
; X64-NEXT: cvtpi2ps %mm2, %xmm0
; X64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
; X64-NEXT: punpcklwd %mm1, %mm0 ## mm0 = mm0[0],mm1[0],mm0[1],mm1[1]
; X64-NEXT: cvtpi2ps %mm0, %xmm0
; X64-NEXT: retq
%1 = tail call x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx bitcast (<8 x i8> <i8 64, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> to x86_mmx), x86_mmx bitcast (<8 x i8> zeroinitializer to x86_mmx))
%2 = tail call x86_mmx @llvm.x86.mmx.pcmpgt.w(x86_mmx bitcast (<4 x i16> zeroinitializer to x86_mmx), x86_mmx %1)
%3 = tail call x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx %1, x86_mmx %2)
%4 = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> zeroinitializer, x86_mmx %3)
%5 = shufflevector <4 x float> %4, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%6 = tail call x86_mmx @llvm.x86.mmx.punpcklwd(x86_mmx %1, x86_mmx %2)
%7 = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %5, x86_mmx %6)
ret <4 x float> %7
}
[x86][MMX] Rename and cleanup tests: arith, intrinsics and shuffle - Rename mmx-builtins to mmx-intrinsics to match other intrinsic test naming. - Remove tests that duplicate functionality from mmx-intrinsics.ll. - Move arith related tests to mmx-arith.ll. - MMX related shuffle goes to vector-shuffle-mmx.ll. llvm-svn: 227130
2015-01-27 04:06:51 +08:00
declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, i8*)
[X86][MMX] Add test for PR35869 llvm-svn: 322197
2018-01-11 01:05:03 +08:00
declare x86_mmx @llvm.x86.mmx.pcmpgt.w(x86_mmx, x86_mmx)
declare x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx, x86_mmx)
declare x86_mmx @llvm.x86.mmx.punpcklwd(x86_mmx, x86_mmx)
declare x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx, x86_mmx)
declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, x86_mmx)