2017-10-19 07:33:31 +08:00
|
|
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
2018-05-06 05:19:59 +08:00
|
|
|
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512F
|
2017-05-23 16:23:51 +08:00
|
|
|
--- |
|
|
|
|
define <16 x i32> @test_load_v16i32_noalign(<16 x i32>* %p1) {
|
|
|
|
%r = load <16 x i32>, <16 x i32>* %p1, align 1
|
|
|
|
ret <16 x i32> %r
|
|
|
|
}
|
|
|
|
|
|
|
|
define <16 x i32> @test_load_v16i32_align(<16 x i32>* %p1) {
|
|
|
|
%r = load <16 x i32>, <16 x i32>* %p1, align 32
|
|
|
|
ret <16 x i32> %r
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test_store_v16i32_noalign(<16 x i32> %val, <16 x i32>* %p1) {
|
|
|
|
store <16 x i32> %val, <16 x i32>* %p1, align 1
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @test_store_v16i32_align(<16 x i32> %val, <16 x i32>* %p1) {
|
|
|
|
store <16 x i32> %val, <16 x i32>* %p1, align 32
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_load_v16i32_noalign
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 16
|
2017-05-23 16:23:51 +08:00
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr }
|
|
|
|
- { id: 1, class: vecr }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $rdi
|
2017-05-23 16:23:51 +08:00
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; AVX512F-LABEL: name: test_load_v16i32_noalign
|
2018-02-01 06:04:26 +08:00
|
|
|
; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
|
|
|
|
; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load 64 from %ir.p1, align 1)
|
|
|
|
; AVX512F: $zmm0 = COPY [[VMOVUPSZrm]]
|
|
|
|
; AVX512F: RET 0, implicit $zmm0
|
|
|
|
%0(p0) = COPY $rdi
|
2017-05-23 16:23:51 +08:00
|
|
|
%1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1)
|
2018-02-01 06:04:26 +08:00
|
|
|
$zmm0 = COPY %1(<16 x s32>)
|
|
|
|
RET 0, implicit $zmm0
|
2017-05-23 16:23:51 +08:00
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_load_v16i32_align
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 16
|
2017-05-23 16:23:51 +08:00
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr }
|
|
|
|
- { id: 1, class: vecr }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $rdi
|
2017-05-23 16:23:51 +08:00
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; AVX512F-LABEL: name: test_load_v16i32_align
|
2018-02-01 06:04:26 +08:00
|
|
|
; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
|
|
|
|
; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load 64 from %ir.p1, align 32)
|
|
|
|
; AVX512F: $zmm0 = COPY [[VMOVUPSZrm]]
|
|
|
|
; AVX512F: RET 0, implicit $zmm0
|
|
|
|
%0(p0) = COPY $rdi
|
2017-05-23 16:23:51 +08:00
|
|
|
%1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 32)
|
2018-02-01 06:04:26 +08:00
|
|
|
$zmm0 = COPY %1(<16 x s32>)
|
|
|
|
RET 0, implicit $zmm0
|
2017-05-23 16:23:51 +08:00
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_store_v16i32_noalign
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 16
|
2017-05-23 16:23:51 +08:00
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vecr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $rdi, $zmm0
|
2017-05-23 16:23:51 +08:00
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; AVX512F-LABEL: name: test_store_v16i32_noalign
|
2018-02-01 06:04:26 +08:00
|
|
|
; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
|
|
|
|
; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
|
|
|
|
; AVX512F: VMOVUPSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 64 into %ir.p1, align 1)
|
2017-10-19 07:33:31 +08:00
|
|
|
; AVX512F: RET 0
|
2018-02-01 06:04:26 +08:00
|
|
|
%0(<16 x s32>) = COPY $zmm0
|
|
|
|
%1(p0) = COPY $rdi
|
2017-05-23 16:23:51 +08:00
|
|
|
G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1)
|
|
|
|
RET 0
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_store_v16i32_align
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 16
|
2017-05-23 16:23:51 +08:00
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: vecr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
2018-02-01 06:04:26 +08:00
|
|
|
liveins: $rdi, $zmm0
|
2017-05-23 16:23:51 +08:00
|
|
|
|
2017-10-19 07:33:31 +08:00
|
|
|
; AVX512F-LABEL: name: test_store_v16i32_align
|
2018-02-01 06:04:26 +08:00
|
|
|
; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
|
|
|
|
; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
|
|
|
|
; AVX512F: VMOVUPSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 64 into %ir.p1, align 32)
|
2017-10-19 07:33:31 +08:00
|
|
|
; AVX512F: RET 0
|
2018-02-01 06:04:26 +08:00
|
|
|
%0(<16 x s32>) = COPY $zmm0
|
|
|
|
%1(p0) = COPY $rdi
|
2017-05-23 16:23:51 +08:00
|
|
|
G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 32)
|
|
|
|
RET 0
|
|
|
|
|
|
|
|
...
|