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llvm-project/llvm/test/CodeGen/Thumb2/mve-stacksplot.mir

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[ARM] Fix for MVE load/store stack accesses MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices. Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used. Differential Revision: https://reviews.llvm.org/D67327 llvm-svn: 372114
2019-09-17 20:58:51 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
[ARM] Replace arm vendor with none. NFC
2020-04-22 23:33:11 +08:00
# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
[ARM] Fix for MVE load/store stack accesses MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices. Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used. Differential Revision: https://reviews.llvm.org/D67327 llvm-svn: 372114
2019-09-17 20:58:51 +08:00
---
name: func0
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -16, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
body: |
bb.0:
; CHECK-LABEL: name: func0
; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
[ARM] Reegenerate MVE tests. NFC The mve-phireg.ll test no longer really tests what it was added for, but the original case was fairly complex. I've left the test in as a general codegen test.
2020-01-15 15:50:14 +08:00
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
; CHECK: $sp = frame-setup tSUBspi $sp, 5, 14 /* CC::al */, $noreg
[ARM] Reegenerate MVE tests. NFC The mve-phireg.ll test no longer really tests what it was added for, but the original case was fairly complex. I've left the test in as a general codegen test.
2020-01-15 15:50:14 +08:00
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 56
; CHECK: $r0 = IMPLICIT_DEF
; CHECK: $r1 = IMPLICIT_DEF
; CHECK: $r2 = IMPLICIT_DEF
; CHECK: $r3 = IMPLICIT_DEF
; CHECK: $r4 = IMPLICIT_DEF
; CHECK: $r5 = IMPLICIT_DEF
; CHECK: $r6 = IMPLICIT_DEF
; CHECK: $r7 = IMPLICIT_DEF
; CHECK: $r8 = IMPLICIT_DEF
; CHECK: $r9 = IMPLICIT_DEF
; CHECK: $r10 = IMPLICIT_DEF
; CHECK: $r11 = IMPLICIT_DEF
; CHECK: $r12 = IMPLICIT_DEF
; CHECK: $lr = IMPLICIT_DEF
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
; CHECK: $r0 = tMOVr killed $sp, 14 /* CC::al */, $noreg
[ARM] Reegenerate MVE tests. NFC The mve-phireg.ll test no longer really tests what it was added for, but the original case was fairly complex. I've left the test in as a general codegen test.
2020-01-15 15:50:14 +08:00
; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12)
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.1)
[ARM] Reegenerate MVE tests. NFC The mve-phireg.ll test no longer really tests what it was added for, but the original case was fairly complex. I've left the test in as a general codegen test.
2020-01-15 15:50:14 +08:00
; CHECK: KILL $r0
; CHECK: KILL $r1
; CHECK: KILL $r2
; CHECK: KILL $r3
; CHECK: KILL $r4
; CHECK: KILL $r5
; CHECK: KILL $r6
; CHECK: KILL $r7
; CHECK: KILL $r8
; CHECK: KILL $r9
; CHECK: KILL $r10
; CHECK: KILL $r11
; CHECK: KILL $r12
; CHECK: KILL $lr
[ARM] Fix for MVE load/store stack accesses MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices. Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used. Differential Revision: https://reviews.llvm.org/D67327 llvm-svn: 372114
2019-09-17 20:58:51 +08:00
$r0 = IMPLICIT_DEF
$r1 = IMPLICIT_DEF
$r2 = IMPLICIT_DEF
$r3 = IMPLICIT_DEF
$r4 = IMPLICIT_DEF
$r5 = IMPLICIT_DEF
$r6 = IMPLICIT_DEF
$r7 = IMPLICIT_DEF
$r8 = IMPLICIT_DEF
$r9 = IMPLICIT_DEF
$r10 = IMPLICIT_DEF
$r11 = IMPLICIT_DEF
$r12 = IMPLICIT_DEF
$lr = IMPLICIT_DEF
renamable $q2 = MVE_VLDRBU32 %stack.0, 12, 0, $noreg :: (load 4 from %stack.0 + 12)
KILL $r0
KILL $r1
KILL $r2
KILL $r3
KILL $r4
KILL $r5
KILL $r6
KILL $r7
KILL $r8
KILL $r9
KILL $r10
KILL $r11
KILL $r12
KILL $lr
...
---
name: func1
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -1200, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 1, name: '', type: default, offset: 0, size: 1200, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -1200, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
body: |
bb.0:
; CHECK-LABEL: name: func1
; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
[ARM] Reegenerate MVE tests. NFC The mve-phireg.ll test no longer really tests what it was added for, but the original case was fairly complex. I've left the test in as a general codegen test.
2020-01-15 15:50:14 +08:00
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
; CHECK: $sp = frame-setup t2SUBspImm12 killed $sp, 1220, 14 /* CC::al */, $noreg
[ARM] Reegenerate MVE tests. NFC The mve-phireg.ll test no longer really tests what it was added for, but the original case was fairly complex. I've left the test in as a general codegen test.
2020-01-15 15:50:14 +08:00
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1256
; CHECK: $r0 = IMPLICIT_DEF
; CHECK: $r1 = IMPLICIT_DEF
; CHECK: $r2 = IMPLICIT_DEF
; CHECK: $r3 = IMPLICIT_DEF
; CHECK: $r4 = IMPLICIT_DEF
; CHECK: $r5 = IMPLICIT_DEF
; CHECK: $r6 = IMPLICIT_DEF
; CHECK: $r7 = IMPLICIT_DEF
; CHECK: $r8 = IMPLICIT_DEF
; CHECK: $r9 = IMPLICIT_DEF
; CHECK: $r10 = IMPLICIT_DEF
; CHECK: $r11 = IMPLICIT_DEF
; CHECK: $r12 = IMPLICIT_DEF
; CHECK: $lr = IMPLICIT_DEF
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.2)
; CHECK: $r0 = t2ADDri killed $sp, 1152, 14 /* CC::al */, $noreg, $noreg
[ARM] Reegenerate MVE tests. NFC The mve-phireg.ll test no longer really tests what it was added for, but the original case was fairly complex. I've left the test in as a general codegen test.
2020-01-15 15:50:14 +08:00
; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0)
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 22:19:21 +08:00
; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.2)
[ARM] Reegenerate MVE tests. NFC The mve-phireg.ll test no longer really tests what it was added for, but the original case was fairly complex. I've left the test in as a general codegen test.
2020-01-15 15:50:14 +08:00
; CHECK: KILL $r0
; CHECK: KILL $r1
; CHECK: KILL $r2
; CHECK: KILL $r3
; CHECK: KILL $r4
; CHECK: KILL $r5
; CHECK: KILL $r6
; CHECK: KILL $r7
; CHECK: KILL $r8
; CHECK: KILL $r9
; CHECK: KILL $r10
; CHECK: KILL $r11
; CHECK: KILL $r12
; CHECK: KILL $lr
[ARM] Fix for MVE load/store stack accesses MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices. Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used. Differential Revision: https://reviews.llvm.org/D67327 llvm-svn: 372114
2019-09-17 20:58:51 +08:00
$r0 = IMPLICIT_DEF
$r1 = IMPLICIT_DEF
$r2 = IMPLICIT_DEF
$r3 = IMPLICIT_DEF
$r4 = IMPLICIT_DEF
$r5 = IMPLICIT_DEF
$r6 = IMPLICIT_DEF
$r7 = IMPLICIT_DEF
$r8 = IMPLICIT_DEF
$r9 = IMPLICIT_DEF
$r10 = IMPLICIT_DEF
$r11 = IMPLICIT_DEF
$r12 = IMPLICIT_DEF
$lr = IMPLICIT_DEF
renamable $q2 = MVE_VLDRBU8 %stack.0, 0, 0, $noreg :: (load 4 from %stack.0)
KILL $r0
KILL $r1
KILL $r2
KILL $r3
KILL $r4
KILL $r5
KILL $r6
KILL $r7
KILL $r8
KILL $r9
KILL $r10
KILL $r11
KILL $r12
KILL $lr
...