forked from OSchip/llvm-project
34 lines
1.1 KiB
LLVM
34 lines
1.1 KiB
LLVM
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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; Make sure the code size estimate for inline asm is 12-bytes per
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; instruction, rather than 8 in previous generations.
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; GCN-LABEL: {{^}}long_forward_branch_gfx10only:
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; GFX9: s_cmp_eq_u32
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; GFX9-NEXT: s_cbranch_scc1
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; GFX10: s_cmp_eq_u32
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; GFX10-NEXT: s_cbranch_scc0
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; GFX10: s_getpc_b64
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; GFX10: s_add_u32
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; GFX10: s_addc_u32
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; GFX10: s_setpc_b64
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define amdgpu_kernel void @long_forward_branch_gfx10only(i32 addrspace(1)* %arg, i32 %cnd) #0 {
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bb0:
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%cmp = icmp eq i32 %cnd, 0
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br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch
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bb2:
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; Estimated as 40-bytes on gfx10 (requiring a long branch), but
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; 16-bytes on gfx9 (allowing a short branch)
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call void asm sideeffect
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"v_nop_e64
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v_nop_e64", ""() #0
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br label %bb3
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bb3:
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store volatile i32 %cnd, i32 addrspace(1)* %arg
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ret void
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}
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