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llvm-project/llvm/test/CodeGen/Thumb2/thumb2-tbh.ll

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[Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables [Reapplying r284580 and r285917 with fix and testing to ensure emitted jump tables for Thumb-1 have 4-byte alignment] The TBB and TBH instructions in Thumb-2 allow jump tables to be compressed into sequences of bytes or shorts respectively. These instructions do not exist in Thumb-1, however it is possible to synthesize them out of a sequence of other instructions. It turns out this sequence is so short that it's almost never a lose for performance and is ALWAYS a significant win for code size. TBB example: Before: lsls r0, r0, #2 After: add r0, pc adr r1, .LJTI0_0 ldrb r0, [r0, #6] ldr r0, [r0, r1] lsls r0, r0, #1 mov pc, r0 add pc, r0 => No change in prologue code size or dynamic instruction count. Jump table shrunk by a factor of 4. The only case that can increase dynamic instruction count is the TBH case: Before: lsls r0, r4, #2 After: lsls r4, r4, #1 adr r1, .LJTI0_0 add r4, pc ldr r0, [r0, r1] ldrh r4, [r4, #6] mov pc, r0 lsls r4, r4, #1 add pc, r4 => 1 more instruction in prologue. Jump table shrunk by a factor of 2. So there is an argument that this should be disabled when optimizing for performance (and a TBH needs to be generated). I'm not so sure about that in practice, because on small cores with Thumb-1 performance is often tied to code size. But I'm willing to turn it off when optimizing for performance if people want (also note that TBHs are fairly rare in practice!) llvm-svn: 285690
2016-11-01 21:37:41 +08:00
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=T2
[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. The "dead" markings allow existing target-independent optimizations, like MachineSink, to trigger more frequently. The CPSR defs would have eventually been marked dead by LiveVariables, so this only affects optimizations before regalloc. The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible with this change: the transform adds a use to an otherwise dead def of CPSR. This is covered by existing regression tests. thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the generated code; I'll fix it in D53452. Differential Revision: https://reviews.llvm.org/D53453 llvm-svn: 345420
2018-10-27 03:32:24 +08:00
; RUN: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=T1DISABLED
; FIXME: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=T1
; FIXME: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=static | FileCheck %s --check-prefix=CHECK --check-prefix=T1
; FIXME: Thumb1 tests temporarily disabled; MachineLICM is now hoisting the
; subs, so the jump table can't be formed.
; T1DISABLED: .data_region jt32
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
tbb / tbh instructions only branch forward, not backwards. llvm-svn: 77522
2009-07-30 07:20:20 +08:00
; Thumb2 target should reorder the bb's in order to use tbb / tbh.
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
%struct.R_flstr = type { i32, i32, i8* }
%struct._T_tstr = type { i32, %struct.R_flstr*, %struct._T_tstr* }
@_C_nextcmd = external global i32 ; <i32*> [#uses=3]
@.str31 = external constant [28 x i8], align 1 ; <[28 x i8]*> [#uses=1]
@_T_gtol = external global %struct._T_tstr* ; <%struct._T_tstr**> [#uses=2]
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
declare i32 @strlen(i8* nocapture) nounwind readonly
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
declare void @Z_fatal(i8*) noreturn nounwind
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
declare noalias i8* @calloc(i32, i32) nounwind
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
ARM: recommit r237590: allow jump tables to be placed as constant islands. The original version didn't properly account for the base register being modified before the final jump, so caused miscompilations in Chromium and LLVM. I've fixed this and tested with an LLVM self-host (I don't have the means to build & test Chromium). The general idea remains the same: in pathological cases jump tables can be too far away from the instructions referencing them (like other constants) so they need to be movable. Should fix PR23627. llvm-svn: 238680
2015-06-01 03:22:07 +08:00
; Jump tables are not anchored next to the TBB/TBH any more. Make sure the
; correct address is still calculated (i.e. via a PC-relative symbol *at* the
; TBB/TBH).
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LABEL: main:
ARM: recommit r237590: allow jump tables to be placed as constant islands. The original version didn't properly account for the base register being modified before the final jump, so caused miscompilations in Chromium and LLVM. I've fixed this and tested with an LLVM self-host (I don't have the means to build & test Chromium). The general idea remains the same: in pathological cases jump tables can be too far away from the instructions referencing them (like other constants) so they need to be movable. Should fix PR23627. llvm-svn: 238680
2015-06-01 03:22:07 +08:00
; CHECK-NOT: adr {{r[0-9]+}}, LJTI
[Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables [Reapplying r284580 and r285917 with fix and testing to ensure emitted jump tables for Thumb-1 have 4-byte alignment] The TBB and TBH instructions in Thumb-2 allow jump tables to be compressed into sequences of bytes or shorts respectively. These instructions do not exist in Thumb-1, however it is possible to synthesize them out of a sequence of other instructions. It turns out this sequence is so short that it's almost never a lose for performance and is ALWAYS a significant win for code size. TBB example: Before: lsls r0, r0, #2 After: add r0, pc adr r1, .LJTI0_0 ldrb r0, [r0, #6] ldr r0, [r0, r1] lsls r0, r0, #1 mov pc, r0 add pc, r0 => No change in prologue code size or dynamic instruction count. Jump table shrunk by a factor of 4. The only case that can increase dynamic instruction count is the TBH case: Before: lsls r0, r4, #2 After: lsls r4, r4, #1 adr r1, .LJTI0_0 add r4, pc ldr r0, [r0, r1] ldrh r4, [r4, #6] mov pc, r0 lsls r4, r4, #1 add pc, r4 => 1 more instruction in prologue. Jump table shrunk by a factor of 2. So there is an argument that this should be disabled when optimizing for performance (and a TBH needs to be generated). I'm not so sure about that in practice, because on small cores with Thumb-1 performance is often tied to code size. But I'm willing to turn it off when optimizing for performance if people want (also note that TBHs are fairly rare in practice!) llvm-svn: 285690
2016-11-01 21:37:41 +08:00
; T1: lsls r[[x:[0-9]+]], {{r[0-9]+}}, #1
ARM: recommit r237590: allow jump tables to be placed as constant islands. The original version didn't properly account for the base register being modified before the final jump, so caused miscompilations in Chromium and LLVM. I've fixed this and tested with an LLVM self-host (I don't have the means to build & test Chromium). The general idea remains the same: in pathological cases jump tables can be too far away from the instructions referencing them (like other constants) so they need to be movable. Should fix PR23627. llvm-svn: 238680
2015-06-01 03:22:07 +08:00
; CHECK: [[PCREL_ANCHOR:LCPI[0-9]+_[0-9]+]]:
[Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables [Reapplying r284580 and r285917 with fix and testing to ensure emitted jump tables for Thumb-1 have 4-byte alignment] The TBB and TBH instructions in Thumb-2 allow jump tables to be compressed into sequences of bytes or shorts respectively. These instructions do not exist in Thumb-1, however it is possible to synthesize them out of a sequence of other instructions. It turns out this sequence is so short that it's almost never a lose for performance and is ALWAYS a significant win for code size. TBB example: Before: lsls r0, r0, #2 After: add r0, pc adr r1, .LJTI0_0 ldrb r0, [r0, #6] ldr r0, [r0, r1] lsls r0, r0, #1 mov pc, r0 add pc, r0 => No change in prologue code size or dynamic instruction count. Jump table shrunk by a factor of 4. The only case that can increase dynamic instruction count is the TBH case: Before: lsls r0, r4, #2 After: lsls r4, r4, #1 adr r1, .LJTI0_0 add r4, pc ldr r0, [r0, r1] ldrh r4, [r4, #6] mov pc, r0 lsls r4, r4, #1 add pc, r4 => 1 more instruction in prologue. Jump table shrunk by a factor of 2. So there is an argument that this should be disabled when optimizing for performance (and a TBH needs to be generated). I'm not so sure about that in practice, because on small cores with Thumb-1 performance is often tied to code size. But I'm willing to turn it off when optimizing for performance if people want (also note that TBHs are fairly rare in practice!) llvm-svn: 285690
2016-11-01 21:37:41 +08:00
; T2-NEXT: tbb [pc, {{r[0-9]+}}]
; T1-NEXT: add pc, r[[x]]
ARM: recommit r237590: allow jump tables to be placed as constant islands. The original version didn't properly account for the base register being modified before the final jump, so caused miscompilations in Chromium and LLVM. I've fixed this and tested with an LLVM self-host (I don't have the means to build & test Chromium). The general idea remains the same: in pathological cases jump tables can be too far away from the instructions referencing them (like other constants) so they need to be movable. Should fix PR23627. llvm-svn: 238680
2015-06-01 03:22:07 +08:00
; CHECK: LJTI0_0:
; CHECK-NEXT: .data_region jt8
; CHECK-NEXT: .byte (LBB{{[0-9]+_[0-9]+}}-([[PCREL_ANCHOR]]+4))/2
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
entry:
br label %bb42.i
bb1.i2: ; preds = %bb42.i
br label %bb40.i
bb5.i: ; preds = %bb42.i
Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input. llvm-svn: 86997
2009-11-13 01:19:09 +08:00
%0 = or i32 %argc, 32 ; <i32> [#uses=1]
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
br label %bb40.i
bb7.i: ; preds = %bb42.i
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
call void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 0, i8* null) nounwind
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
unreachable
bb15.i: ; preds = %bb42.i
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
call void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 2, i8* null) nounwind
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
unreachable
bb23.i: ; preds = %bb42.i
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
%1 = call i32 @strlen(i8* null) nounwind readonly ; <i32> [#uses=0]
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
unreachable
bb33.i: ; preds = %bb42.i
store i32 0, i32* @_C_nextcmd, align 4
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
%2 = call noalias i8* @calloc(i32 21, i32 1) nounwind ; <i8*> [#uses=0]
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
unreachable
bb34.i: ; preds = %bb42.i
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%3 = load i32, i32* @_C_nextcmd, align 4 ; <i32> [#uses=1]
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
%4 = add i32 %3, 1 ; <i32> [#uses=1]
store i32 %4, i32* @_C_nextcmd, align 4
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
%5 = call noalias i8* @calloc(i32 22, i32 1) nounwind ; <i8*> [#uses=0]
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
unreachable
bb35.i: ; preds = %bb42.i
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
%6 = call noalias i8* @calloc(i32 20, i32 1) nounwind ; <i8*> [#uses=0]
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
unreachable
bb37.i: ; preds = %bb42.i
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
%7 = call noalias i8* @calloc(i32 14, i32 1) nounwind ; <i8*> [#uses=0]
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
unreachable
bb39.i: ; preds = %bb42.i
[opaque pointer type] Add textual IR support for explicit type parameter to gep operator Similar to gep (r230786) and load (r230794) changes. Similar migration script can be used to update test cases, which successfully migrated all of LLVM and Polly, but about 4 test cases needed manually changes in Clang. (this script will read the contents of stdin and massage it into stdout - wrap it in the 'apply.sh' script shown in previous commits + xargs to apply it over a large set of test cases) import fileinput import sys import re rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL) def conv(match): line = match.group(1) line += match.group(4) line += ", " line += match.group(2) return line line = sys.stdin.read() off = 0 for match in re.finditer(rep, line): sys.stdout.write(line[off:match.start()]) sys.stdout.write(conv(match)) off = match.end() sys.stdout.write(line[off:]) llvm-svn: 232184
2015-03-14 02:20:45 +08:00
call void @Z_fatal(i8* getelementptr ([28 x i8], [28 x i8]* @.str31, i32 0, i32 0)) nounwind
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
unreachable
bb40.i: ; preds = %bb42.i, %bb5.i, %bb1.i2
br label %bb42.i
bb42.i: ; preds = %bb40.i, %entry
Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input. llvm-svn: 86997
2009-11-13 01:19:09 +08:00
switch i32 %argc, label %bb39.i [
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 10:18:14 +08:00
i32 67, label %bb33.i
i32 70, label %bb35.i
i32 77, label %bb37.i
i32 83, label %bb34.i
i32 97, label %bb7.i
i32 100, label %bb5.i
i32 101, label %bb40.i
i32 102, label %bb23.i
i32 105, label %bb15.i
i32 116, label %bb1.i2
]
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
declare void @_T_addtol(%struct._T_tstr** nocapture, i32, i8*) nounwind