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llvm-project/llvm/test/CodeGen/Thumb2/cortex-fp.ll

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ARM: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309755
2017-08-02 06:20:49 +08:00
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM3
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM4
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM7
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXA8
cortex m4 has floating point support, but only single precision. llvm-svn: 110810
2010-08-11 23:44:15 +08:00
define float @foo(float %a, float %b) {
entry:
Add extra CHECK prefix to tests with explicit prefix These tests mistakenly assume that CHECK is still available even if an explicit prefix is specified. llvm-svn: 201492
2014-02-16 21:28:15 +08:00
; CHECK-LABEL: foo:
ARM: do not generate BLX instructions on Cortex-M CPUs. Particularly on MachO, we were generating "blx _dest" instructions on M-class CPUs, which don't actually exist. They happen to get fixed up by the linker into valid "bl _dest" instructions (which is why such a massive issue has remained largely undetected), but we shouldn't rely on that. llvm-svn: 214959
2014-08-06 19:13:14 +08:00
; CORTEXM3: bl ___mulsf3
Remove some register allocation order dependencies. llvm-svn: 172874
2013-01-19 08:03:32 +08:00
; CORTEXM4: vmul.f32 s
[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM) The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218747
2014-10-01 17:02:17 +08:00
; CORTEXM7: vmul.f32 s
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
; CORTEXA8: vmul.f32 d
cortex m4 has floating point support, but only single precision. llvm-svn: 110810
2010-08-11 23:44:15 +08:00
%0 = fmul float %a, %b
ret float %0
}
define double @bar(double %a, double %b) {
entry:
Add extra CHECK prefix to tests with explicit prefix These tests mistakenly assume that CHECK is still available even if an explicit prefix is specified. llvm-svn: 201492
2014-02-16 21:28:15 +08:00
; CHECK-LABEL: bar:
cortex m4 has floating point support, but only single precision. llvm-svn: 110810
2010-08-11 23:44:15 +08:00
%0 = fmul double %a, %b
ARM: do not generate BLX instructions on Cortex-M CPUs. Particularly on MachO, we were generating "blx _dest" instructions on M-class CPUs, which don't actually exist. They happen to get fixed up by the linker into valid "bl _dest" instructions (which is why such a massive issue has remained largely undetected), but we shouldn't rely on that. llvm-svn: 214959
2014-08-06 19:13:14 +08:00
; CORTEXM3: bl ___muldf3
[ARM] Enable DP copy, load and store instructions for FPv4-SP The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
2014-08-21 20:50:31 +08:00
; CORTEXM4: {{bl|b.w}} ___muldf3
[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM) The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. llvm-svn: 218747
2014-10-01 17:02:17 +08:00
; CORTEXM7: vmul.f64 d
Add LLVM support for Swift. llvm-svn: 164899
2012-09-30 05:43:49 +08:00
; CORTEXA8: vmul.f64 d
cortex m4 has floating point support, but only single precision. llvm-svn: 110810
2010-08-11 23:44:15 +08:00
ret double %0
}