2016-09-13 03:29:26 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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Remove a instcombine transform that (no longer?) makes sense:
// C - zext(bool) -> bool ? C - 1 : C
if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1))
if (ZI->getSrcTy()->isIntegerTy(1))
return SelectInst::Create(ZI->getOperand(0), SubOne(C), C);
This ends up forming sext i1 instructions that codegen to terrible code. e.g.
int blah(_Bool x, _Bool y) {
return (x - y) + 1;
}
=>
movzbl %dil, %eax
movzbl %sil, %ecx
shll $31, %ecx
sarl $31, %ecx
leal 1(%rax,%rcx), %eax
ret
Without the rule, llvm now generates:
movzbl %sil, %ecx
movzbl %dil, %eax
incl %eax
subl %ecx, %eax
ret
It also helps with ARM (and pretty much any target that doesn't have a sext i1 :-).
The transformation was done as part of Eli's r75531. He has given the ok to
remove it.
rdar://11748024
llvm-svn: 159230
2012-06-27 06:03:13 +08:00
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; RUN: opt < %s -instcombine -S | FileCheck %s
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2016-09-13 03:50:08 +08:00
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Remove a instcombine transform that (no longer?) makes sense:
// C - zext(bool) -> bool ? C - 1 : C
if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1))
if (ZI->getSrcTy()->isIntegerTy(1))
return SelectInst::Create(ZI->getOperand(0), SubOne(C), C);
This ends up forming sext i1 instructions that codegen to terrible code. e.g.
int blah(_Bool x, _Bool y) {
return (x - y) + 1;
}
=>
movzbl %dil, %eax
movzbl %sil, %ecx
shll $31, %ecx
sarl $31, %ecx
leal 1(%rax,%rcx), %eax
ret
Without the rule, llvm now generates:
movzbl %sil, %ecx
movzbl %dil, %eax
incl %eax
subl %ecx, %eax
ret
It also helps with ARM (and pretty much any target that doesn't have a sext i1 :-).
The transformation was done as part of Eli's r75531. He has given the ok to
remove it.
rdar://11748024
llvm-svn: 159230
2012-06-27 06:03:13 +08:00
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; rdar://11748024
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2009-07-14 06:27:52 +08:00
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Remove a instcombine transform that (no longer?) makes sense:
// C - zext(bool) -> bool ? C - 1 : C
if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1))
if (ZI->getSrcTy()->isIntegerTy(1))
return SelectInst::Create(ZI->getOperand(0), SubOne(C), C);
This ends up forming sext i1 instructions that codegen to terrible code. e.g.
int blah(_Bool x, _Bool y) {
return (x - y) + 1;
}
=>
movzbl %dil, %eax
movzbl %sil, %ecx
shll $31, %ecx
sarl $31, %ecx
leal 1(%rax,%rcx), %eax
ret
Without the rule, llvm now generates:
movzbl %sil, %ecx
movzbl %dil, %eax
incl %eax
subl %ecx, %eax
ret
It also helps with ARM (and pretty much any target that doesn't have a sext i1 :-).
The transformation was done as part of Eli's r75531. He has given the ok to
remove it.
rdar://11748024
llvm-svn: 159230
2012-06-27 06:03:13 +08:00
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define i32 @a(i1 zeroext %x, i1 zeroext %y) {
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2013-07-14 09:42:54 +08:00
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; CHECK-LABEL: @a(
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2016-09-13 03:29:26 +08:00
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; CHECK-NEXT: [[CONV3_NEG:%.*]] = sext i1 %y to i32
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; CHECK-NEXT: [[SUB:%.*]] = select i1 %x, i32 2, i32 1
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[SUB]], [[CONV3_NEG]]
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; CHECK-NEXT: ret i32 [[ADD]]
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;
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Remove a instcombine transform that (no longer?) makes sense:
// C - zext(bool) -> bool ? C - 1 : C
if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1))
if (ZI->getSrcTy()->isIntegerTy(1))
return SelectInst::Create(ZI->getOperand(0), SubOne(C), C);
This ends up forming sext i1 instructions that codegen to terrible code. e.g.
int blah(_Bool x, _Bool y) {
return (x - y) + 1;
}
=>
movzbl %dil, %eax
movzbl %sil, %ecx
shll $31, %ecx
sarl $31, %ecx
leal 1(%rax,%rcx), %eax
ret
Without the rule, llvm now generates:
movzbl %sil, %ecx
movzbl %dil, %eax
incl %eax
subl %ecx, %eax
ret
It also helps with ARM (and pretty much any target that doesn't have a sext i1 :-).
The transformation was done as part of Eli's r75531. He has given the ok to
remove it.
rdar://11748024
llvm-svn: 159230
2012-06-27 06:03:13 +08:00
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%conv = zext i1 %x to i32
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%conv3 = zext i1 %y to i32
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%conv3.neg = sub i32 0, %conv3
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%sub = add i32 %conv, 1
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%add = add i32 %sub, %conv3.neg
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ret i32 %add
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2009-07-14 06:27:52 +08:00
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}
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2016-09-13 03:29:26 +08:00
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2016-09-13 06:28:29 +08:00
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define i32 @PR30273_select(i1 %a, i1 %b) {
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; CHECK-LABEL: @PR30273_select(
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2016-09-13 03:50:08 +08:00
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 %a to i32
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; CHECK-NEXT: [[SEL1:%.*]] = select i1 %a, i32 2, i32 1
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; CHECK-NEXT: [[SEL2:%.*]] = select i1 %b, i32 [[SEL1]], i32 [[ZEXT]]
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; CHECK-NEXT: ret i32 [[SEL2]]
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;
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%zext = zext i1 %a to i32
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%sel1 = select i1 %a, i32 2, i32 1
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%sel2 = select i1 %b, i32 %sel1, i32 %zext
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ret i32 %sel2
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}
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2016-09-13 06:28:29 +08:00
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define i32 @PR30273_zext_add(i1 %a, i1 %b) {
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; CHECK-LABEL: @PR30273_zext_add(
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; CHECK-NEXT: [[CONV:%.*]] = zext i1 %a to i32
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; CHECK-NEXT: [[CONV3:%.*]] = zext i1 %b to i32
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; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV3]], [[CONV]]
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; CHECK-NEXT: ret i32 [[ADD]]
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;
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%conv = zext i1 %a to i32
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%conv3 = zext i1 %b to i32
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%add = add nuw nsw i32 %conv3, %conv
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ret i32 %add
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}
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define i32 @PR30273_three_bools(i1 %x, i1 %y, i1 %z) {
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; CHECK-LABEL: @PR30273_three_bools(
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; CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 %x to i32
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; CHECK-NEXT: [[ADD1:%.*]] = select i1 %x, i32 2, i32 1
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; CHECK-NEXT: [[SEL1:%.*]] = select i1 %y, i32 [[ADD1]], i32 [[FROMBOOL]]
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; CHECK-NEXT: [[ADD2:%.*]] = zext i1 %z to i32
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; CHECK-NEXT: [[SEL2:%.*]] = add nuw nsw i32 [[SEL1]], [[ADD2]]
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; CHECK-NEXT: ret i32 [[SEL2]]
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;
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%frombool = zext i1 %x to i32
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%add1 = add nsw i32 %frombool, 1
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%sel1 = select i1 %y, i32 %add1, i32 %frombool
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%add2 = add nsw i32 %sel1, 1
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%sel2 = select i1 %z, i32 %add2, i32 %sel1
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ret i32 %sel2
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}
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