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llvm-project/llvm/test/CodeGen/X86/bt.ll

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AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s
add PR # llvm-svn: 61427
2008-12-25 13:40:38 +08:00
; PR3253
Disable the register+memory forms of the bt instructions for now. Thanks to Eli for pointing out that these forms don't ignore the high bits of their index operands, and as such are not immediately suitable for use by isel. llvm-svn: 62194
2009-01-14 07:23:30 +08:00
; The register+memory form of the BT instruction should be usable on
; pentium4, however it is currently disabled due to the register+memory
; form having different semantics than the register+register form.
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
; Test these patterns:
; (X & (1 << N)) != 0 --> BT(X, N).
; ((X >>u N) & 1) != 0 --> BT(X, N).
; as well as several variations:
; - The second form can use an arithmetic shift.
; - Either form can use == instead of !=.
; - Either form can compare with an operand of the &
; instead of with 0.
; - The comparison can be commuted (only cases where neither
; operand is constant are included).
; - The and can be commuted.
Add a simple pattern for matching 'bt'. llvm-svn: 61426
2008-12-25 13:34:37 +08:00
define void @test2(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: test2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB0_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Add a simple pattern for matching 'bt'. llvm-svn: 61426
2008-12-25 13:34:37 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = lshr i32 %x, %n
%tmp3 = and i32 %tmp29, 1
%tmp4 = icmp eq i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Add a simple pattern for matching 'bt'. llvm-svn: 61426
2008-12-25 13:34:37 +08:00
}
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
define void @test2b(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: test2b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB1_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = lshr i32 %x, %n
%tmp3 = and i32 1, %tmp29
%tmp4 = icmp eq i32 %tmp3, 0
Revert "CodeGen: Allow small copyable blocks to "break" the CFG." This reverts commit ada6595a526d71df04988eb0a4b4fe84df398ded. This needs a simple probability check because there are some cases where it is not profitable. llvm-svn: 291695
2017-01-12 03:55:19 +08:00
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @atest2(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: atest2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB2_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = ashr i32 %x, %n
%tmp3 = and i32 %tmp29, 1
%tmp4 = icmp eq i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @atest2b(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: atest2b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB3_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = ashr i32 %x, %n
%tmp3 = and i32 1, %tmp29
%tmp4 = icmp eq i32 %tmp3, 0
Revert "CodeGen: Allow small copyable blocks to "break" the CFG." This reverts commit ada6595a526d71df04988eb0a4b4fe84df398ded. This needs a simple probability check because there are some cases where it is not profitable. llvm-svn: 291695
2017-01-12 03:55:19 +08:00
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @test3(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: test3:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB4_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x
%tmp4 = icmp eq i32 %tmp3, 0
Revert "CodeGen: Allow small copyable blocks to "break" the CFG." This reverts commit ada6595a526d71df04988eb0a4b4fe84df398ded. This needs a simple probability check because there are some cases where it is not profitable. llvm-svn: 291695
2017-01-12 03:55:19 +08:00
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @test3b(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: test3b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB5_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29
%tmp4 = icmp eq i32 %tmp3, 0
Revert "CodeGen: Allow small copyable blocks to "break" the CFG." This reverts commit ada6595a526d71df04988eb0a4b4fe84df398ded. This needs a simple probability check because there are some cases where it is not profitable. llvm-svn: 291695
2017-01-12 03:55:19 +08:00
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @testne2(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: testne2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB6_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = lshr i32 %x, %n
%tmp3 = and i32 %tmp29, 1
%tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @testne2b(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: testne2b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB7_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = lshr i32 %x, %n
%tmp3 = and i32 1, %tmp29
%tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @atestne2(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: atestne2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB8_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = ashr i32 %x, %n
%tmp3 = and i32 %tmp29, 1
%tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @atestne2b(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: atestne2b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB9_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = ashr i32 %x, %n
%tmp3 = and i32 1, %tmp29
%tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @testne3(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: testne3:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB10_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x
%tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @testne3b(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: testne3b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB11_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29
%tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @query2(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: query2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB12_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = lshr i32 %x, %n
%tmp3 = and i32 %tmp29, 1
%tmp4 = icmp eq i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @query2b(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: query2b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB13_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = lshr i32 %x, %n
%tmp3 = and i32 1, %tmp29
%tmp4 = icmp eq i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @aquery2(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: aquery2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB14_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = ashr i32 %x, %n
%tmp3 = and i32 %tmp29, 1
%tmp4 = icmp eq i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @aquery2b(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: aquery2b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB15_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = ashr i32 %x, %n
%tmp3 = and i32 1, %tmp29
%tmp4 = icmp eq i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @query3(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: query3:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB16_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x
%tmp4 = icmp eq i32 %tmp3, %tmp29
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @query3b(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: query3b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB17_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29
%tmp4 = icmp eq i32 %tmp3, %tmp29
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @query3x(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: query3x:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB18_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x
%tmp4 = icmp eq i32 %tmp29, %tmp3
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @query3bx(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: query3bx:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB19_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29
%tmp4 = icmp eq i32 %tmp29, %tmp3
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @queryne2(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: queryne2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB20_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = lshr i32 %x, %n
%tmp3 = and i32 %tmp29, 1
%tmp4 = icmp ne i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @queryne2b(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: queryne2b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB21_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = lshr i32 %x, %n
%tmp3 = and i32 1, %tmp29
%tmp4 = icmp ne i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @aqueryne2(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: aqueryne2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB22_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = ashr i32 %x, %n
%tmp3 = and i32 %tmp29, 1
%tmp4 = icmp ne i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @aqueryne2b(i32 %x, i32 %n) nounwind {
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
; CHECK-LABEL: aqueryne2b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB23_2
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = ashr i32 %x, %n
%tmp3 = and i32 1, %tmp29
%tmp4 = icmp ne i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @queryne3(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: queryne3:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB24_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x
%tmp4 = icmp ne i32 %tmp3, %tmp29
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @queryne3b(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: queryne3b:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB25_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29
%tmp4 = icmp ne i32 %tmp3, %tmp29
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @queryne3x(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: queryne3x:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB26_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x
%tmp4 = icmp ne i32 %tmp29, %tmp3
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
define void @queryne3bx(i32 %x, i32 %n) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: queryne3bx:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB27_2
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
entry:
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
%tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29
%tmp4 = icmp ne i32 %tmp29, %tmp3
br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb:
call void @foo()
ret void
UnifiedReturnBlock:
ret void
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
Add a simple pattern for matching 'bt'. llvm-svn: 61426
2008-12-25 13:34:37 +08:00
declare void @foo()
Add x86 isel lowering logic to form bit test with inverted condition. e.g. x ^ -1. Patch by David Majnemer. rdar://12755626 llvm-svn: 169339
2012-12-05 08:10:38 +08:00
define zeroext i1 @invert(i32 %flags, i32 %flag) nounwind {
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
; CHECK-LABEL: invert:
; CHECK: # BB#0:
; CHECK-NEXT: notl %edi
; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: setb %al
; CHECK-NEXT: retq
AVX-512: Fixed BT instruction selection. The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets. But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1). I added the new sequence (truncate (a >>n) to i1) to the BT pattern. Differential Revision: https://reviews.llvm.org/D22354 llvm-svn: 275950
2016-07-19 15:14:21 +08:00
;
Add x86 isel lowering logic to form bit test with inverted condition. e.g. x ^ -1. Patch by David Majnemer. rdar://12755626 llvm-svn: 169339
2012-12-05 08:10:38 +08:00
%neg = xor i32 %flags, -1
%shl = shl i32 1, %flag
%and = and i32 %shl, %neg
%tobool = icmp ne i32 %and, 0
ret i1 %tobool
}
auto-generate checks Note: I removed the checks after each jump because that's noise, but we apparently need branches rather than returning i1 to see the bt codegen in some cases. llvm-svn: 275439
2016-07-15 01:07:55 +08:00
X86: Improve BT instruction selection for 64-bit values. If a 64-bit value is tested against a bit which is known to be in the range [0..31) (modulo 64), we can use the 32-bit BT instruction, which has a slightly shorter encoding. Differential Revision: https://reviews.llvm.org/D25862 llvm-svn: 284864
2016-10-22 03:57:55 +08:00
define zeroext i1 @extend(i32 %bit, i64 %bits) {
; CHECK-LABEL: extend:
; CHECK: # BB#0:
; CHECK-NEXT: btl %edi, %esi
entry:
%and = and i32 %bit, 31
%sh_prom = zext i32 %and to i64
%shl = shl i64 1, %sh_prom
%and1 = and i64 %shl, %bits
%tobool = icmp ne i64 %and1, 0
ret i1 %tobool
}