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llvm-project/llvm/test/CodeGen/X86/avx2-arith.ll

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[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s --check-prefix=X64
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
define <4 x i64> @test_vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: test_vpaddq:
; X32: ## BB#0:
; X32-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_vpaddq:
; X64: ## BB#0:
; X64-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = add <4 x i64> %i, %j
ret <4 x i64> %x
}
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
define <8 x i32> @test_vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: test_vpaddd:
; X32: ## BB#0:
; X32-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_vpaddd:
; X64: ## BB#0:
; X64-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = add <8 x i32> %i, %j
ret <8 x i32> %x
}
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
define <16 x i16> @test_vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: test_vpaddw:
; X32: ## BB#0:
; X32-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_vpaddw:
; X64: ## BB#0:
; X64-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = add <16 x i16> %i, %j
ret <16 x i16> %x
}
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
define <32 x i8> @test_vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: test_vpaddb:
; X32: ## BB#0:
; X32-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_vpaddb:
; X64: ## BB#0:
; X64-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = add <32 x i8> %i, %j
ret <32 x i8> %x
}
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
define <4 x i64> @test_vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: test_vpsubq:
; X32: ## BB#0:
; X32-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_vpsubq:
; X64: ## BB#0:
; X64-NEXT: vpsubq %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = sub <4 x i64> %i, %j
ret <4 x i64> %x
}
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
define <8 x i32> @test_vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: test_vpsubd:
; X32: ## BB#0:
; X32-NEXT: vpsubd %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_vpsubd:
; X64: ## BB#0:
; X64-NEXT: vpsubd %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = sub <8 x i32> %i, %j
ret <8 x i32> %x
}
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
define <16 x i16> @test_vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: test_vpsubw:
; X32: ## BB#0:
; X32-NEXT: vpsubw %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_vpsubw:
; X64: ## BB#0:
; X64-NEXT: vpsubw %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = sub <16 x i16> %i, %j
ret <16 x i16> %x
}
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
define <32 x i8> @test_vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: test_vpsubb:
; X32: ## BB#0:
; X32-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_vpsubb:
; X64: ## BB#0:
; X64-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = sub <32 x i8> %i, %j
ret <32 x i8> %x
}
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
define <8 x i32> @test_vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: test_vpmulld:
; X32: ## BB#0:
; X32-NEXT: vpmulld %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_vpmulld:
; X64: ## BB#0:
; X64-NEXT: vpmulld %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = mul <8 x i32> %i, %j
ret <8 x i32> %x
}
Disambiguate function names in some CodeGen tests. (Some tests were using function names that also were names of instructions and/or doing other unusual things that were making the test not amenable to otherwise scriptable pattern matching.) No functionality change. llvm-svn: 186621
2013-07-19 06:29:15 +08:00
define <16 x i16> @test_vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: test_vpmullw:
; X32: ## BB#0:
; X32-NEXT: vpmullw %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_vpmullw:
; X64: ## BB#0:
; X64-NEXT: vpmullw %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = mul <16 x i16> %i, %j
ret <16 x i16> %x
}
[X86][AVX2] Regenerate arithmetic tests Fixed missing checks for tests that used a '-' in the name, which was messing with update_llc_test_checks.py llvm-svn: 291363
2017-01-08 04:38:36 +08:00
define <16 x i8> @mul_v16i8(<16 x i8> %i, <16 x i8> %j) nounwind readnone {
; X32-LABEL: mul_v16i8:
; X32: ## BB#0:
; X32-NEXT: vpmovsxbw %xmm1, %ymm1
; X32-NEXT: vpmovsxbw %xmm0, %ymm0
; X32-NEXT: vpmullw %ymm1, %ymm0, %ymm0
; X32-NEXT: vextracti128 $1, %ymm0, %xmm1
; X32-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
; X32-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; X32-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; X32-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: mul_v16i8:
; X64: ## BB#0:
; X64-NEXT: vpmovsxbw %xmm1, %ymm1
; X64-NEXT: vpmovsxbw %xmm0, %ymm0
; X64-NEXT: vpmullw %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
; X64-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; X64-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; X64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X64-NEXT: vzeroupper
; X64-NEXT: retq
[X86][SSE] Add v16i8/v32i8 multiplication support Patch to allow int8 vectors to be multiplied on the SSE unit instead of being scalarized. The patch sign extends the i8 lanes to i16, uses the SSE2 pmullw multiplication instruction, then packs the lower byte from each result. Differential Revision: http://reviews.llvm.org/D9115 llvm-svn: 235837
2015-04-27 15:55:46 +08:00
%x = mul <16 x i8> %i, %j
ret <16 x i8> %x
}
[X86][AVX2] Regenerate arithmetic tests Fixed missing checks for tests that used a '-' in the name, which was messing with update_llc_test_checks.py llvm-svn: 291363
2017-01-08 04:38:36 +08:00
define <32 x i8> @mul_v32i8(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
; X32-LABEL: mul_v32i8:
; X32: ## BB#0:
; X32-NEXT: vextracti128 $1, %ymm1, %xmm2
; X32-NEXT: vpmovsxbw %xmm2, %ymm2
; X32-NEXT: vextracti128 $1, %ymm0, %xmm3
; X32-NEXT: vpmovsxbw %xmm3, %ymm3
; X32-NEXT: vpmullw %ymm2, %ymm3, %ymm2
; X32-NEXT: vextracti128 $1, %ymm2, %xmm3
; X32-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
; X32-NEXT: vpshufb %xmm4, %xmm3, %xmm3
; X32-NEXT: vpshufb %xmm4, %xmm2, %xmm2
; X32-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; X32-NEXT: vpmovsxbw %xmm1, %ymm1
; X32-NEXT: vpmovsxbw %xmm0, %ymm0
; X32-NEXT: vpmullw %ymm1, %ymm0, %ymm0
; X32-NEXT: vextracti128 $1, %ymm0, %xmm1
; X32-NEXT: vpshufb %xmm4, %xmm1, %xmm1
; X32-NEXT: vpshufb %xmm4, %xmm0, %xmm0
; X32-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X32-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: mul_v32i8:
; X64: ## BB#0:
; X64-NEXT: vextracti128 $1, %ymm1, %xmm2
; X64-NEXT: vpmovsxbw %xmm2, %ymm2
; X64-NEXT: vextracti128 $1, %ymm0, %xmm3
; X64-NEXT: vpmovsxbw %xmm3, %ymm3
; X64-NEXT: vpmullw %ymm2, %ymm3, %ymm2
; X64-NEXT: vextracti128 $1, %ymm2, %xmm3
; X64-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
; X64-NEXT: vpshufb %xmm4, %xmm3, %xmm3
; X64-NEXT: vpshufb %xmm4, %xmm2, %xmm2
; X64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; X64-NEXT: vpmovsxbw %xmm1, %ymm1
; X64-NEXT: vpmovsxbw %xmm0, %ymm0
; X64-NEXT: vpmullw %ymm1, %ymm0, %ymm0
; X64-NEXT: vextracti128 $1, %ymm0, %xmm1
; X64-NEXT: vpshufb %xmm4, %xmm1, %xmm1
; X64-NEXT: vpshufb %xmm4, %xmm0, %xmm0
; X64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X64-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; X64-NEXT: retq
[X86][SSE] Add v16i8/v32i8 multiplication support Patch to allow int8 vectors to be multiplied on the SSE unit instead of being scalarized. The patch sign extends the i8 lanes to i16, uses the SSE2 pmullw multiplication instruction, then packs the lower byte from each result. Differential Revision: http://reviews.llvm.org/D9115 llvm-svn: 235837
2015-04-27 15:55:46 +08:00
%x = mul <32 x i8> %i, %j
ret <32 x i8> %x
}
[X86][AVX2] Regenerate arithmetic tests Fixed missing checks for tests that used a '-' in the name, which was messing with update_llc_test_checks.py llvm-svn: 291363
2017-01-08 04:38:36 +08:00
define <4 x i64> @mul_v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
; X32-LABEL: mul_v4i64:
; X32: ## BB#0:
; X32-NEXT: vpsrlq $32, %ymm0, %ymm2
; X32-NEXT: vpmuludq %ymm1, %ymm2, %ymm2
; X32-NEXT: vpsrlq $32, %ymm1, %ymm3
; X32-NEXT: vpmuludq %ymm3, %ymm0, %ymm3
; X32-NEXT: vpaddq %ymm2, %ymm3, %ymm2
; X32-NEXT: vpsllq $32, %ymm2, %ymm2
; X32-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
; X32-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: mul_v4i64:
; X64: ## BB#0:
; X64-NEXT: vpsrlq $32, %ymm0, %ymm2
; X64-NEXT: vpmuludq %ymm1, %ymm2, %ymm2
; X64-NEXT: vpsrlq $32, %ymm1, %ymm3
; X64-NEXT: vpmuludq %ymm3, %ymm0, %ymm3
; X64-NEXT: vpaddq %ymm2, %ymm3, %ymm2
; X64-NEXT: vpsllq $32, %ymm2, %ymm2
; X64-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
; X64-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; X64-NEXT: retq
Add AVX2 instruction lowering for add, sub, and mul. llvm-svn: 144174
2011-11-09 15:28:55 +08:00
%x = mul <4 x i64> %i, %j
ret <4 x i64> %x
}
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
2013-06-26 18:55:03 +08:00
define <8 x i32> @mul_const1(<8 x i32> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const1:
; X32: ## BB#0:
; X32-NEXT: vpaddd %ymm0, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const1:
; X64: ## BB#0:
; X64-NEXT: vpaddd %ymm0, %ymm0, %ymm0
; X64-NEXT: retq
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
2013-06-26 18:55:03 +08:00
%y = mul <8 x i32> %x, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
ret <8 x i32> %y
}
define <4 x i64> @mul_const2(<4 x i64> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const2:
; X32: ## BB#0:
; X32-NEXT: vpsllq $2, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const2:
; X64: ## BB#0:
; X64-NEXT: vpsllq $2, %ymm0, %ymm0
; X64-NEXT: retq
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
2013-06-26 18:55:03 +08:00
%y = mul <4 x i64> %x, <i64 4, i64 4, i64 4, i64 4>
ret <4 x i64> %y
}
define <16 x i16> @mul_const3(<16 x i16> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const3:
; X32: ## BB#0:
; X32-NEXT: vpsllw $3, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const3:
; X64: ## BB#0:
; X64-NEXT: vpsllw $3, %ymm0, %ymm0
; X64-NEXT: retq
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
2013-06-26 18:55:03 +08:00
%y = mul <16 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
ret <16 x i16> %y
}
define <4 x i64> @mul_const4(<4 x i64> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const4:
; X32: ## BB#0:
; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1
; X32-NEXT: vpsubq %ymm0, %ymm1, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const4:
; X64: ## BB#0:
; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1
; X64-NEXT: vpsubq %ymm0, %ymm1, %ymm0
; X64-NEXT: retq
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
2013-06-26 18:55:03 +08:00
%y = mul <4 x i64> %x, <i64 -1, i64 -1, i64 -1, i64 -1>
ret <4 x i64> %y
}
define <8 x i32> @mul_const5(<8 x i32> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const5:
; X32: ## BB#0:
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const5:
; X64: ## BB#0:
; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0
; X64-NEXT: retq
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
2013-06-26 18:55:03 +08:00
%y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %y
}
define <8 x i32> @mul_const6(<8 x i32> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const6:
; X32: ## BB#0:
; X32-NEXT: vpmulld LCPI18_0, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const6:
; X64: ## BB#0:
; X64-NEXT: vpmulld {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
2013-06-26 18:55:03 +08:00
%y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 2, i32 0, i32 2, i32 0, i32 0>
ret <8 x i32> %y
}
define <8 x i64> @mul_const7(<8 x i64> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const7:
; X32: ## BB#0:
; X32-NEXT: vpaddq %ymm0, %ymm0, %ymm0
; X32-NEXT: vpaddq %ymm1, %ymm1, %ymm1
; X32-NEXT: retl
;
; X64-LABEL: mul_const7:
; X64: ## BB#0:
; X64-NEXT: vpaddq %ymm0, %ymm0, %ymm0
; X64-NEXT: vpaddq %ymm1, %ymm1, %ymm1
; X64-NEXT: retq
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
2013-06-26 18:55:03 +08:00
%y = mul <8 x i64> %x, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
ret <8 x i64> %y
}
define <8 x i16> @mul_const8(<8 x i16> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const8:
; X32: ## BB#0:
; X32-NEXT: vpsllw $3, %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const8:
; X64: ## BB#0:
; X64-NEXT: vpsllw $3, %xmm0, %xmm0
; X64-NEXT: retq
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
2013-06-26 18:55:03 +08:00
%y = mul <8 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
ret <8 x i16> %y
}
define <8 x i32> @mul_const9(<8 x i32> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const9:
; X32: ## BB#0:
; X32-NEXT: movl $2, %eax
; X32-NEXT: vmovd %eax, %xmm1
; X32-NEXT: vpmulld %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const9:
; X64: ## BB#0:
; X64-NEXT: movl $2, %eax
; X64-NEXT: vmovd %eax, %xmm1
; X64-NEXT: vpmulld %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
2013-06-26 18:55:03 +08:00
%y = mul <8 x i32> %x, <i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %y
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
}
DAGCombiner: Don't fold vector muls with constants that look like a splat of a power of 2 but differ in bit width. PR17283. llvm-svn: 191000
2013-09-19 21:28:20 +08:00
[X86][AVX2] Regenerate arithmetic tests Fixed missing checks for tests that used a '-' in the name, which was messing with update_llc_test_checks.py llvm-svn: 291363
2017-01-08 04:38:36 +08:00
; %x * 0x01010101
DAGCombiner: Don't fold vector muls with constants that look like a splat of a power of 2 but differ in bit width. PR17283. llvm-svn: 191000
2013-09-19 21:28:20 +08:00
define <4 x i32> @mul_const10(<4 x i32> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const10:
; X32: ## BB#0:
; X32-NEXT: vpbroadcastd LCPI22_0, %xmm1
; X32-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const10:
; X64: ## BB#0:
; X64-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
; X64-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; X64-NEXT: retq
DAGCombiner: Don't fold vector muls with constants that look like a splat of a power of 2 but differ in bit width. PR17283. llvm-svn: 191000
2013-09-19 21:28:20 +08:00
%m = mul <4 x i32> %x, <i32 16843009, i32 16843009, i32 16843009, i32 16843009>
ret <4 x i32> %m
}
[X86][AVX2] Regenerate arithmetic tests Fixed missing checks for tests that used a '-' in the name, which was messing with update_llc_test_checks.py llvm-svn: 291363
2017-01-08 04:38:36 +08:00
; %x * 0x80808080
DAGCombiner: Don't fold vector muls with constants that look like a splat of a power of 2 but differ in bit width. PR17283. llvm-svn: 191000
2013-09-19 21:28:20 +08:00
define <4 x i32> @mul_const11(<4 x i32> %x) {
[X86][AVX2] Regenerate and add 32-bit tests to core tests llvm-svn: 283666
2016-10-09 02:36:57 +08:00
; X32-LABEL: mul_const11:
; X32: ## BB#0:
; X32-NEXT: vpbroadcastd LCPI23_0, %xmm1
; X32-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const11:
; X64: ## BB#0:
; X64-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
; X64-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; X64-NEXT: retq
DAGCombiner: Don't fold vector muls with constants that look like a splat of a power of 2 but differ in bit width. PR17283. llvm-svn: 191000
2013-09-19 21:28:20 +08:00
%m = mul <4 x i32> %x, <i32 2155905152, i32 2155905152, i32 2155905152, i32 2155905152>
ret <4 x i32> %m
}