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llvm-project/llvm/test/CodeGen/AArch64/arm64-regress-interphase-sh...

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[AARCH64] Enable AARCH64 lit tests on windows dev machines As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows This will hopefully help stop cases where windows developers break the aarch64 target Differential Revision: https://reviews.llvm.org/D22191 llvm-svn: 275973
2016-07-19 21:35:11 +08:00
; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
ARM64: add regression test for r205519. llvm-svn: 205520
2014-04-03 17:36:05 +08:00
; This is mostly a "don't assert" test. The type of the RHS of a shift depended
; on the phase of legalization, which led to the creation of an unexpected and
; unselectable "rotr" node: (i32 (rotr i32, i64)).
Revert r191049/r191059 as it can produce wrong code (see PR17975). It has already been reverted on the 3.4 branch in r196521. llvm-svn: 206311
2014-04-16 02:34:24 +08:00
; FIXME: This test is xfailed because it relies on an optimization that has
; been reverted (see PR17975).
; XFAIL: *
ARM64: add regression test for r205519. llvm-svn: 205520
2014-04-03 17:36:05 +08:00
define void @foo(i64* nocapture %d) {
; CHECK-LABEL: foo:
; CHECK: rorv
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp = load i64, i64* undef, align 8
ARM64: add regression test for r205519. llvm-svn: 205520
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%sub397 = sub i64 0, %tmp
%and398 = and i64 %sub397, 4294967295
%shr404 = lshr i64 %and398, 0
%or405 = or i64 0, %shr404
%xor406 = xor i64 %or405, 0
%xor417 = xor i64 0, %xor406
%xor428 = xor i64 0, %xor417
%sub430 = sub i64 %xor417, 0
%and431 = and i64 %sub430, 4294967295
%and432 = and i64 %xor428, 31
%sub433 = sub i64 32, %and432
%shl434 = shl i64 %and431, %sub433
%shr437 = lshr i64 %and431, %and432
%or438 = or i64 %shl434, %shr437
%xor439 = xor i64 %or438, %xor428
%sub441 = sub i64 %xor439, 0
store i64 %sub441, i64* %d, align 8
ret void
}