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llvm-project/llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll

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Fix test to require Asserts since it uses debug output. llvm-svn: 266448
2016-04-16 00:09:00 +08:00
; REQUIRES: asserts
[AArch64] Add MMOs to callee-save load/store instructions. Summary: Without MMOs, the callee-save load/store instructions were treated as volatile by the MI post-RA scheduler and AArch64LoadStoreOptimizer. Reviewers: t.p.northover, mcrosier Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17661 llvm-svn: 266439
2016-04-15 23:16:19 +08:00
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll requires +Asserts. llvm-svn: 266443
2016-04-15 23:37:27 +08:00
; REQUIRES: asserts
[AArch64] Add MMOs to callee-save load/store instructions. Summary: Without MMOs, the callee-save load/store instructions were treated as volatile by the MI post-RA scheduler and AArch64LoadStoreOptimizer. Reviewers: t.p.northover, mcrosier Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17661 llvm-svn: 266439
2016-04-15 23:16:19 +08:00
@G = external global [0 x i32], align 4
; Check that MMOs are added to epilogue calle-save restore loads so
; that the store to G is not considered dependant on the callee-save
; loads.
;
; CHECK: Before post-MI-sched:
; CHECK-LABEL: # Machine code for function test1:
; CHECK: SU(2): STRWui %WZR
; CHECK: SU(3): %X21<def>, %X20<def> = LDPXi %SP
; CHECK: Predecessors:
ScheduleDAG: Match enum names when printing sdep kinds It is less confusing to have the same names in the debug print as the enum members. llvm-svn: 282273
2016-09-24 02:28:31 +08:00
; CHECK-NEXT: out SU(0)
; CHECK-NEXT: out SU(0)
; CHECK-NEXT: ord SU(0)
[AArch64] Add MMOs to callee-save load/store instructions. Summary: Without MMOs, the callee-save load/store instructions were treated as volatile by the MI post-RA scheduler and AArch64LoadStoreOptimizer. Reviewers: t.p.northover, mcrosier Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17661 llvm-svn: 266439
2016-04-15 23:16:19 +08:00
; CHECK-NEXT: Successors:
define void @test1() {
entry:
tail call void asm sideeffect "nop", "~{x20},~{x21},~{x22},~{x23}"() nounwind
store i32 0, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @G, i64 0, i64 0), align 4
ret void
}