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llvm-project/llvm/test/MC/ARM/invalid-special-reg.s

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[ARM] Fix bash-ism in test llvm-svn: 296610
2017-03-01 19:11:06 +08:00
@ RUN: not llvm-mc -triple armv7a--none-eabi < %s 2>&1 | FileCheck %s
@ RUN: not llvm-mc -triple thumbv7a--none-eabi < %s 2>&1 | FileCheck %s
[ARM] Fix parsing of special register masks This parsing code was incorrectly checking for invalid characters, so an invalid instruction like: msr spsr_w, r0 would be emitted as: msr spsr_cxsf, r0 Differential revision: https://reviews.llvm.org/D30462 llvm-svn: 296607
2017-03-01 18:51:04 +08:00
msr apsr_c, r0
@ CHECK: invalid operand for instruction
[ARM] Use new assembler diags for ARM This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
2017-10-03 18:26:11 +08:00
msr cpsr_w, r0
[ARM] Fix parsing of special register masks This parsing code was incorrectly checking for invalid characters, so an invalid instruction like: msr spsr_w, r0 would be emitted as: msr spsr_cxsf, r0 Differential revision: https://reviews.llvm.org/D30462 llvm-svn: 296607
2017-03-01 18:51:04 +08:00
@ CHECK: invalid operand for instruction
[ARM] Use new assembler diags for ARM This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
2017-10-03 18:26:11 +08:00
msr cpsr_cc, r0
[ARM] Fix parsing of special register masks This parsing code was incorrectly checking for invalid characters, so an invalid instruction like: msr spsr_w, r0 would be emitted as: msr spsr_cxsf, r0 Differential revision: https://reviews.llvm.org/D30462 llvm-svn: 296607
2017-03-01 18:51:04 +08:00
@ CHECK: invalid operand for instruction
[ARM] Use new assembler diags for ARM This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
2017-10-03 18:26:11 +08:00
msr xpsr_c, r0
[ARM] Fix parsing of special register masks This parsing code was incorrectly checking for invalid characters, so an invalid instruction like: msr spsr_w, r0 would be emitted as: msr spsr_cxsf, r0 Differential revision: https://reviews.llvm.org/D30462 llvm-svn: 296607
2017-03-01 18:51:04 +08:00
@ CHECK: invalid operand for instruction