2013-04-30 08:14:27 +08:00
|
|
|
//===----- R600Packetizer.cpp - VLIW packetizer ---------------------------===//
|
|
|
|
//
|
2019-01-19 16:50:56 +08:00
|
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2013-04-30 08:14:27 +08:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
/// \file
|
|
|
|
/// This pass implements instructions packetization for R600. It unsets isLast
|
|
|
|
/// bit of instructions inside a bundle and substitutes src register with
|
|
|
|
/// PreviousVector when applicable.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2013-05-24 01:10:37 +08:00
|
|
|
#include "AMDGPU.h"
|
2014-06-13 09:32:00 +08:00
|
|
|
#include "AMDGPUSubtarget.h"
|
2013-05-24 01:10:37 +08:00
|
|
|
#include "R600InstrInfo.h"
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
Summary:
MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction
and register defintions, which are huge so we only want to include
them where needed.
This will also make it easier if we want to split the R600 and GCN
definitions into separate tablegenerated files.
I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h
because it uses some enums from the header to initialize default values
for the SIMachineFunction class, so I ended up having to remove includes of
SIMachineFunctionInfo.h from headers too.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46272
llvm-svn: 332930
2018-05-22 10:03:23 +08:00
|
|
|
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
|
2013-04-30 08:14:27 +08:00
|
|
|
#include "llvm/CodeGen/DFAPacketizer.h"
|
|
|
|
#include "llvm/CodeGen/MachineDominators.h"
|
2013-05-24 01:10:37 +08:00
|
|
|
#include "llvm/CodeGen/MachineFunctionPass.h"
|
2013-04-30 08:14:27 +08:00
|
|
|
#include "llvm/CodeGen/MachineLoopInfo.h"
|
2013-05-24 01:10:37 +08:00
|
|
|
#include "llvm/CodeGen/Passes.h"
|
2013-04-30 08:14:27 +08:00
|
|
|
#include "llvm/CodeGen/ScheduleDAG.h"
|
2017-06-06 19:49:48 +08:00
|
|
|
#include "llvm/Support/Debug.h"
|
2013-05-24 01:10:37 +08:00
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2013-04-30 08:14:27 +08:00
|
|
|
|
2013-05-24 01:10:37 +08:00
|
|
|
using namespace llvm;
|
|
|
|
|
2014-04-22 10:41:26 +08:00
|
|
|
#define DEBUG_TYPE "packets"
|
|
|
|
|
2013-05-24 01:10:37 +08:00
|
|
|
namespace {
|
2013-04-30 08:14:27 +08:00
|
|
|
|
|
|
|
class R600Packetizer : public MachineFunctionPass {
|
|
|
|
|
|
|
|
public:
|
|
|
|
static char ID;
|
2017-05-19 01:21:13 +08:00
|
|
|
R600Packetizer() : MachineFunctionPass(ID) {}
|
2013-04-30 08:14:27 +08:00
|
|
|
|
2014-04-29 15:57:24 +08:00
|
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
2013-04-30 08:14:27 +08:00
|
|
|
AU.setPreservesCFG();
|
|
|
|
AU.addRequired<MachineDominatorTree>();
|
|
|
|
AU.addPreserved<MachineDominatorTree>();
|
|
|
|
AU.addRequired<MachineLoopInfo>();
|
|
|
|
AU.addPreserved<MachineLoopInfo>();
|
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
|
|
}
|
|
|
|
|
2016-10-01 10:56:57 +08:00
|
|
|
StringRef getPassName() const override { return "R600 Packetizer"; }
|
2013-04-30 08:14:27 +08:00
|
|
|
|
2014-04-29 15:57:24 +08:00
|
|
|
bool runOnMachineFunction(MachineFunction &Fn) override;
|
2013-04-30 08:14:27 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
class R600PacketizerList : public VLIWPacketizerList {
|
|
|
|
private:
|
|
|
|
const R600InstrInfo *TII;
|
|
|
|
const R600RegisterInfo &TRI;
|
2013-09-05 03:53:46 +08:00
|
|
|
bool VLIW5;
|
|
|
|
bool ConsideredInstUsesAlreadyWrittenVectorElement;
|
2013-04-30 08:14:27 +08:00
|
|
|
|
2016-02-28 03:09:00 +08:00
|
|
|
unsigned getSlot(const MachineInstr &MI) const {
|
|
|
|
return TRI.getHWRegChan(MI.getOperand(0).getReg());
|
2013-04-30 08:14:27 +08:00
|
|
|
}
|
|
|
|
|
2013-05-03 05:52:55 +08:00
|
|
|
/// \returns register to PV chan mapping for bundle/single instructions that
|
2014-01-25 01:20:08 +08:00
|
|
|
/// immediately precedes I.
|
2013-05-03 05:52:55 +08:00
|
|
|
DenseMap<unsigned, unsigned> getPreviousVector(MachineBasicBlock::iterator I)
|
|
|
|
const {
|
|
|
|
DenseMap<unsigned, unsigned> Result;
|
2013-04-30 08:14:27 +08:00
|
|
|
I--;
|
|
|
|
if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
|
|
|
|
return Result;
|
2016-02-23 05:30:15 +08:00
|
|
|
MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
|
2013-04-30 08:14:27 +08:00
|
|
|
if (I->isBundle())
|
|
|
|
BI++;
|
2013-09-05 03:53:46 +08:00
|
|
|
int LastDstChan = -1;
|
2013-05-03 05:52:55 +08:00
|
|
|
do {
|
2013-09-05 03:53:46 +08:00
|
|
|
bool isTrans = false;
|
2016-02-28 03:09:00 +08:00
|
|
|
int BISlot = getSlot(*BI);
|
2013-09-05 03:53:46 +08:00
|
|
|
if (LastDstChan >= BISlot)
|
|
|
|
isTrans = true;
|
|
|
|
LastDstChan = BISlot;
|
2016-02-23 10:46:52 +08:00
|
|
|
if (TII->isPredicated(*BI))
|
2013-05-03 05:52:55 +08:00
|
|
|
continue;
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write);
|
2013-06-03 23:56:12 +08:00
|
|
|
if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
|
2013-05-03 05:52:55 +08:00
|
|
|
continue;
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst);
|
2013-06-28 23:46:59 +08:00
|
|
|
if (DstIdx == -1) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
unsigned Dst = BI->getOperand(DstIdx).getReg();
|
2016-06-30 08:01:54 +08:00
|
|
|
if (isTrans || TII->isTransOnly(*BI)) {
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
Result[Dst] = R600::PS;
|
2013-06-30 03:32:43 +08:00
|
|
|
continue;
|
|
|
|
}
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
if (BI->getOpcode() == R600::DOT4_r600 ||
|
|
|
|
BI->getOpcode() == R600::DOT4_eg) {
|
|
|
|
Result[Dst] = R600::PV_X;
|
2013-05-03 05:52:55 +08:00
|
|
|
continue;
|
|
|
|
}
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
if (Dst == R600::OQAP) {
|
2013-06-28 23:47:08 +08:00
|
|
|
continue;
|
|
|
|
}
|
2013-05-03 05:52:55 +08:00
|
|
|
unsigned PVReg = 0;
|
|
|
|
switch (TRI.getHWRegChan(Dst)) {
|
|
|
|
case 0:
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
PVReg = R600::PV_X;
|
2013-05-03 05:52:55 +08:00
|
|
|
break;
|
|
|
|
case 1:
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
PVReg = R600::PV_Y;
|
2013-05-03 05:52:55 +08:00
|
|
|
break;
|
|
|
|
case 2:
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
PVReg = R600::PV_Z;
|
2013-05-03 05:52:55 +08:00
|
|
|
break;
|
|
|
|
case 3:
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
PVReg = R600::PV_W;
|
2013-05-03 05:52:55 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Invalid Chan");
|
|
|
|
}
|
|
|
|
Result[Dst] = PVReg;
|
|
|
|
} while ((++BI)->isBundledWithPred());
|
2013-04-30 08:14:27 +08:00
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
2016-02-28 03:09:00 +08:00
|
|
|
void substitutePV(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PVs)
|
2013-05-03 05:52:55 +08:00
|
|
|
const {
|
2013-06-26 05:22:18 +08:00
|
|
|
unsigned Ops[] = {
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
R600::OpName::src0,
|
|
|
|
R600::OpName::src1,
|
|
|
|
R600::OpName::src2
|
2013-04-30 08:14:27 +08:00
|
|
|
};
|
|
|
|
for (unsigned i = 0; i < 3; i++) {
|
2016-02-28 03:09:00 +08:00
|
|
|
int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]);
|
2013-04-30 08:14:27 +08:00
|
|
|
if (OperandIdx < 0)
|
|
|
|
continue;
|
2016-02-28 03:09:00 +08:00
|
|
|
unsigned Src = MI.getOperand(OperandIdx).getReg();
|
2013-05-03 05:52:55 +08:00
|
|
|
const DenseMap<unsigned, unsigned>::const_iterator It = PVs.find(Src);
|
|
|
|
if (It != PVs.end())
|
2016-02-28 03:09:00 +08:00
|
|
|
MI.getOperand(OperandIdx).setReg(It->second);
|
2013-04-30 08:14:27 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
public:
|
|
|
|
// Ctor.
|
2016-06-24 14:30:11 +08:00
|
|
|
R600PacketizerList(MachineFunction &MF, const R600Subtarget &ST,
|
|
|
|
MachineLoopInfo &MLI)
|
2015-12-15 04:35:13 +08:00
|
|
|
: VLIWPacketizerList(MF, MLI, nullptr),
|
2016-06-24 14:30:11 +08:00
|
|
|
TII(ST.getInstrInfo()),
|
2014-08-05 05:25:23 +08:00
|
|
|
TRI(TII->getRegisterInfo()) {
|
2016-06-24 14:30:11 +08:00
|
|
|
VLIW5 = !ST.hasCaymanISA();
|
2013-09-05 03:53:46 +08:00
|
|
|
}
|
2013-04-30 08:14:27 +08:00
|
|
|
|
|
|
|
// initPacketizerState - initialize some internal flags.
|
2014-04-29 15:57:24 +08:00
|
|
|
void initPacketizerState() override {
|
2013-09-05 03:53:46 +08:00
|
|
|
ConsideredInstUsesAlreadyWrittenVectorElement = false;
|
|
|
|
}
|
2013-04-30 08:14:27 +08:00
|
|
|
|
|
|
|
// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
|
2016-02-28 03:09:00 +08:00
|
|
|
bool ignorePseudoInstruction(const MachineInstr &MI,
|
2015-12-15 02:54:44 +08:00
|
|
|
const MachineBasicBlock *MBB) override {
|
2013-04-30 08:14:27 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// isSoloInstruction - return true if instruction MI can not be packetized
|
|
|
|
// with any other instruction, which means that MI itself is a packet.
|
2016-02-28 03:09:00 +08:00
|
|
|
bool isSoloInstruction(const MachineInstr &MI) override {
|
|
|
|
if (TII->isVector(MI))
|
2013-04-30 08:14:27 +08:00
|
|
|
return true;
|
2016-02-28 03:09:00 +08:00
|
|
|
if (!TII->isALUInstr(MI.getOpcode()))
|
2013-04-30 08:14:27 +08:00
|
|
|
return true;
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
if (MI.getOpcode() == R600::GROUP_BARRIER)
|
2013-06-28 23:46:59 +08:00
|
|
|
return true;
|
2013-08-01 03:31:41 +08:00
|
|
|
// XXX: This can be removed once the packetizer properly handles all the
|
|
|
|
// LDS instruction group restrictions.
|
2016-03-03 07:00:21 +08:00
|
|
|
return TII->isLDSInstr(MI.getOpcode());
|
2013-04-30 08:14:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
|
|
|
|
// together.
|
2014-04-29 15:57:24 +08:00
|
|
|
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override {
|
2013-04-30 08:14:27 +08:00
|
|
|
MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
|
2016-02-28 03:09:00 +08:00
|
|
|
if (getSlot(*MII) == getSlot(*MIJ))
|
2013-09-05 03:53:46 +08:00
|
|
|
ConsideredInstUsesAlreadyWrittenVectorElement = true;
|
2013-04-30 08:14:27 +08:00
|
|
|
// Does MII and MIJ share the same pred_sel ?
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel),
|
|
|
|
OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel);
|
2013-04-30 08:14:27 +08:00
|
|
|
unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
|
|
|
|
PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0;
|
|
|
|
if (PredI != PredJ)
|
|
|
|
return false;
|
|
|
|
if (SUJ->isSucc(SUI)) {
|
|
|
|
for (unsigned i = 0, e = SUJ->Succs.size(); i < e; ++i) {
|
|
|
|
const SDep &Dep = SUJ->Succs[i];
|
|
|
|
if (Dep.getSUnit() != SUI)
|
|
|
|
continue;
|
|
|
|
if (Dep.getKind() == SDep::Anti)
|
|
|
|
continue;
|
|
|
|
if (Dep.getKind() == SDep::Output)
|
|
|
|
if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
|
|
|
|
continue;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2013-10-23 02:19:10 +08:00
|
|
|
|
2016-06-30 08:01:54 +08:00
|
|
|
bool ARDef =
|
|
|
|
TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ);
|
|
|
|
bool ARUse =
|
|
|
|
TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ);
|
2013-10-23 02:19:10 +08:00
|
|
|
|
2016-03-03 07:00:21 +08:00
|
|
|
return !ARDef || !ARUse;
|
2013-04-30 08:14:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// isLegalToPruneDependencies - Is it legal to prune dependece between SUI
|
|
|
|
// and SUJ.
|
2014-04-29 15:57:24 +08:00
|
|
|
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override {
|
|
|
|
return false;
|
|
|
|
}
|
2013-04-30 08:14:27 +08:00
|
|
|
|
|
|
|
void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last);
|
2013-04-30 08:14:27 +08:00
|
|
|
MI->getOperand(LastOp).setImm(Bit);
|
|
|
|
}
|
|
|
|
|
2016-02-28 03:09:00 +08:00
|
|
|
bool isBundlableWithCurrentPMI(MachineInstr &MI,
|
2013-06-30 03:32:43 +08:00
|
|
|
const DenseMap<unsigned, unsigned> &PV,
|
|
|
|
std::vector<R600InstrInfo::BankSwizzle> &BS,
|
|
|
|
bool &isTransSlot) {
|
2016-06-30 08:01:54 +08:00
|
|
|
isTransSlot = TII->isTransOnly(MI);
|
2013-09-05 03:53:46 +08:00
|
|
|
assert (!isTransSlot || VLIW5);
|
|
|
|
|
|
|
|
// Is the dst reg sequence legal ?
|
|
|
|
if (!isTransSlot && !CurrentPacketMIs.empty()) {
|
2016-02-28 03:09:00 +08:00
|
|
|
if (getSlot(MI) <= getSlot(*CurrentPacketMIs.back())) {
|
|
|
|
if (ConsideredInstUsesAlreadyWrittenVectorElement &&
|
2016-06-30 08:01:54 +08:00
|
|
|
!TII->isVectorOnly(MI) && VLIW5) {
|
2013-09-05 03:53:46 +08:00
|
|
|
isTransSlot = true;
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG({
|
2016-02-28 03:09:00 +08:00
|
|
|
dbgs() << "Considering as Trans Inst :";
|
|
|
|
MI.dump();
|
|
|
|
});
|
2013-09-05 03:53:46 +08:00
|
|
|
}
|
|
|
|
else
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2013-06-30 03:32:43 +08:00
|
|
|
|
|
|
|
// Are the Constants limitations met ?
|
2016-02-28 03:09:00 +08:00
|
|
|
CurrentPacketMIs.push_back(&MI);
|
2013-06-30 03:32:43 +08:00
|
|
|
if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) {
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG({
|
2013-04-30 08:14:27 +08:00
|
|
|
dbgs() << "Couldn't pack :\n";
|
2016-02-28 03:09:00 +08:00
|
|
|
MI.dump();
|
2013-04-30 08:14:27 +08:00
|
|
|
dbgs() << "with the following packets :\n";
|
|
|
|
for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
|
|
|
|
CurrentPacketMIs[i]->dump();
|
|
|
|
dbgs() << "\n";
|
|
|
|
}
|
|
|
|
dbgs() << "because of Consts read limitations\n";
|
2016-02-28 03:09:00 +08:00
|
|
|
});
|
2013-06-30 03:32:43 +08:00
|
|
|
CurrentPacketMIs.pop_back();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Is there a BankSwizzle set that meet Read Port limitations ?
|
|
|
|
if (!TII->fitsReadPortLimitations(CurrentPacketMIs,
|
|
|
|
PV, BS, isTransSlot)) {
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG({
|
2013-04-30 08:14:27 +08:00
|
|
|
dbgs() << "Couldn't pack :\n";
|
2016-02-28 03:09:00 +08:00
|
|
|
MI.dump();
|
2013-04-30 08:14:27 +08:00
|
|
|
dbgs() << "with the following packets :\n";
|
|
|
|
for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
|
|
|
|
CurrentPacketMIs[i]->dump();
|
|
|
|
dbgs() << "\n";
|
|
|
|
}
|
|
|
|
dbgs() << "because of Read port limitations\n";
|
2016-02-28 03:09:00 +08:00
|
|
|
});
|
2013-06-30 03:32:43 +08:00
|
|
|
CurrentPacketMIs.pop_back();
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-11-18 19:04:02 +08:00
|
|
|
// We cannot read LDS source registers from the Trans slot.
|
2016-06-30 08:01:54 +08:00
|
|
|
if (isTransSlot && TII->readsLDSSrcReg(MI))
|
2013-09-12 10:55:06 +08:00
|
|
|
return false;
|
|
|
|
|
2013-06-30 03:32:43 +08:00
|
|
|
CurrentPacketMIs.pop_back();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-02-28 03:09:00 +08:00
|
|
|
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override {
|
2013-06-30 03:32:43 +08:00
|
|
|
MachineBasicBlock::iterator FirstInBundle =
|
2016-02-28 03:09:00 +08:00
|
|
|
CurrentPacketMIs.empty() ? &MI : CurrentPacketMIs.front();
|
2013-06-30 03:32:43 +08:00
|
|
|
const DenseMap<unsigned, unsigned> &PV =
|
|
|
|
getPreviousVector(FirstInBundle);
|
|
|
|
std::vector<R600InstrInfo::BankSwizzle> BS;
|
|
|
|
bool isTransSlot;
|
|
|
|
|
|
|
|
if (isBundlableWithCurrentPMI(MI, PV, BS, isTransSlot)) {
|
2013-05-18 00:50:02 +08:00
|
|
|
for (unsigned i = 0, e = CurrentPacketMIs.size(); i < e; i++) {
|
|
|
|
MachineInstr *MI = CurrentPacketMIs[i];
|
2013-06-30 03:32:43 +08:00
|
|
|
unsigned Op = TII->getOperandIdx(MI->getOpcode(),
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
R600::OpName::bank_swizzle);
|
2013-06-30 03:32:43 +08:00
|
|
|
MI->getOperand(Op).setImm(BS[i]);
|
2013-05-18 00:50:02 +08:00
|
|
|
}
|
2016-02-28 03:09:00 +08:00
|
|
|
unsigned Op =
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle);
|
2016-02-28 03:09:00 +08:00
|
|
|
MI.getOperand(Op).setImm(BS.back());
|
2013-06-30 03:32:43 +08:00
|
|
|
if (!CurrentPacketMIs.empty())
|
|
|
|
setIsLastBit(CurrentPacketMIs.back(), 0);
|
|
|
|
substitutePV(MI, PV);
|
|
|
|
MachineBasicBlock::iterator It = VLIWPacketizerList::addToPacket(MI);
|
|
|
|
if (isTransSlot) {
|
2014-03-02 20:27:27 +08:00
|
|
|
endPacket(std::next(It)->getParent(), std::next(It));
|
2013-06-30 03:32:43 +08:00
|
|
|
}
|
|
|
|
return It;
|
2013-05-18 00:50:02 +08:00
|
|
|
}
|
2016-02-28 03:09:00 +08:00
|
|
|
endPacket(MI.getParent(), MI);
|
2016-06-30 08:01:54 +08:00
|
|
|
if (TII->isTransOnly(MI))
|
2013-09-05 03:53:46 +08:00
|
|
|
return MI;
|
2013-04-30 08:14:27 +08:00
|
|
|
return VLIWPacketizerList::addToPacket(MI);
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
|
2016-06-24 14:30:11 +08:00
|
|
|
const R600Subtarget &ST = Fn.getSubtarget<R600Subtarget>();
|
|
|
|
const R600InstrInfo *TII = ST.getInstrInfo();
|
|
|
|
|
2013-04-30 08:14:27 +08:00
|
|
|
MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
|
|
|
|
|
|
|
|
// Instantiate the packetizer.
|
2016-06-24 14:30:11 +08:00
|
|
|
R600PacketizerList Packetizer(Fn, ST, MLI);
|
2013-04-30 08:14:27 +08:00
|
|
|
|
|
|
|
// DFA state table should not be empty.
|
|
|
|
assert(Packetizer.getResourceTracker() && "Empty DFA table!");
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
assert(Packetizer.getResourceTracker()->getInstrItins());
|
2013-04-30 08:14:27 +08:00
|
|
|
|
2016-06-03 02:37:16 +08:00
|
|
|
if (Packetizer.getResourceTracker()->getInstrItins()->isEmpty())
|
|
|
|
return false;
|
|
|
|
|
2013-04-30 08:14:27 +08:00
|
|
|
//
|
|
|
|
// Loop over all basic blocks and remove KILL pseudo-instructions
|
|
|
|
// These instructions confuse the dependence analysis. Consider:
|
|
|
|
// D0 = ... (Insn 0)
|
|
|
|
// R0 = KILL R0, D0 (Insn 1)
|
|
|
|
// R0 = ... (Insn 2)
|
|
|
|
// Here, Insn 1 will result in the dependence graph not emitting an output
|
|
|
|
// dependence between Insn 0 and Insn 2. This can lead to incorrect
|
|
|
|
// packetization
|
|
|
|
//
|
|
|
|
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
|
|
|
|
MBB != MBBe; ++MBB) {
|
|
|
|
MachineBasicBlock::iterator End = MBB->end();
|
|
|
|
MachineBasicBlock::iterator MI = MBB->begin();
|
|
|
|
while (MI != End) {
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
if (MI->isKill() || MI->getOpcode() == R600::IMPLICIT_DEF ||
|
|
|
|
(MI->getOpcode() == R600::CF_ALU && !MI->getOperand(8).getImm())) {
|
2013-04-30 08:14:27 +08:00
|
|
|
MachineBasicBlock::iterator DeleteMI = MI;
|
|
|
|
++MI;
|
|
|
|
MBB->erase(DeleteMI);
|
|
|
|
End = MBB->end();
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
++MI;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Loop over all of the basic blocks.
|
|
|
|
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
|
|
|
|
MBB != MBBe; ++MBB) {
|
|
|
|
// Find scheduling regions and schedule / packetize each region.
|
|
|
|
unsigned RemainingCount = MBB->size();
|
|
|
|
for(MachineBasicBlock::iterator RegionEnd = MBB->end();
|
|
|
|
RegionEnd != MBB->begin();) {
|
|
|
|
// The next region starts above the previous region. Look backward in the
|
|
|
|
// instruction stream until we find the nearest boundary.
|
|
|
|
MachineBasicBlock::iterator I = RegionEnd;
|
|
|
|
for(;I != MBB->begin(); --I, --RemainingCount) {
|
2016-06-30 08:01:54 +08:00
|
|
|
if (TII->isSchedulingBoundary(*std::prev(I), &*MBB, Fn))
|
2013-04-30 08:14:27 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
I = MBB->begin();
|
|
|
|
|
|
|
|
// Skip empty scheduling regions.
|
|
|
|
if (I == RegionEnd) {
|
2014-03-02 20:27:27 +08:00
|
|
|
RegionEnd = std::prev(RegionEnd);
|
2013-04-30 08:14:27 +08:00
|
|
|
--RemainingCount;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// Skip regions with one instruction.
|
2014-03-02 20:27:27 +08:00
|
|
|
if (I == std::prev(RegionEnd)) {
|
|
|
|
RegionEnd = std::prev(RegionEnd);
|
2013-04-30 08:14:27 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2015-10-14 04:07:10 +08:00
|
|
|
Packetizer.PacketizeMIs(&*MBB, &*I, RegionEnd);
|
2013-04-30 08:14:27 +08:00
|
|
|
RegionEnd = I;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2013-05-24 01:10:37 +08:00
|
|
|
} // end anonymous namespace
|
2013-04-30 08:14:27 +08:00
|
|
|
|
2017-08-03 06:19:45 +08:00
|
|
|
INITIALIZE_PASS_BEGIN(R600Packetizer, DEBUG_TYPE,
|
|
|
|
"R600 Packetizer", false, false)
|
|
|
|
INITIALIZE_PASS_END(R600Packetizer, DEBUG_TYPE,
|
|
|
|
"R600 Packetizer", false, false)
|
|
|
|
|
|
|
|
char R600Packetizer::ID = 0;
|
|
|
|
|
|
|
|
char &llvm::R600PacketizerID = R600Packetizer::ID;
|
|
|
|
|
2017-05-19 01:21:13 +08:00
|
|
|
llvm::FunctionPass *llvm::createR600Packetizer() {
|
|
|
|
return new R600Packetizer();
|
2013-04-30 08:14:27 +08:00
|
|
|
}
|