2018-10-31 03:24:51 +08:00
|
|
|
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj \
|
2020-07-20 15:39:14 +08:00
|
|
|
# RUN: | llvm-readobj --unwind - | FileCheck %s
|
2019-08-07 20:41:38 +08:00
|
|
|
# RUN: llc -o - %s -mtriple=aarch64-windows -run-pass=aarch64-ldst-opt \
|
|
|
|
|
# RUN: | FileCheck %s --check-prefix=CHECK-LDSTOPT
|
2018-10-27 14:13:06 +08:00
|
|
|
# This test case checks the basic validity of the .xdata section. It's
|
|
|
|
|
# documented at:
|
|
|
|
|
# https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
|
|
|
|
|
|
[AArch64] Generate and parse SEH assembly directives
This ensures that you get the same output regardless if generating
code directly to an object file or if generating assembly and
assembling that.
Add implementations of the EmitARM64WinCFI*() methods in
AArch64TargetAsmStreamer, and fill in one blank in MCAsmStreamer.
Add corresponding directive handlers in AArch64AsmParser and
COFFAsmParser.
Some SEH directive names have been picked to match the prior art
for SEH assembly directives for x86_64, e.g. the spelling of
".seh_startepilogue" matching the preexisting ".seh_endprologue".
For the directives for saving registers, the exact spelling
from the arm64 documentation is picked, e.g. ".seh_save_reg" (to follow
that naming for all the other ones, e.g. ".seh_save_fregp_x"), while
the corresponding one for x86_64 is plain ".seh_savereg" without the
second underscore.
Directives in the epilogues have the same names as in prologues,
e.g. .seh_savereg, even though the registers are restored, not
saved, at that point.
Differential Revision: https://reviews.llvm.org/D86529
2020-08-07 17:44:48 +08:00
|
|
|
# Also test the generated assembler SEH directives.
|
|
|
|
|
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=asm \
|
|
|
|
|
# RUN: | FileCheck %s --check-prefix=ASM
|
|
|
|
|
|
2018-10-27 14:13:06 +08:00
|
|
|
# We expect to see the following in the .xdata section:
|
|
|
|
|
|
|
|
|
|
# CHECK: ExceptionData {
|
2019-08-07 20:41:38 +08:00
|
|
|
# CHECK-NEXT: FunctionLength: 96
|
2018-10-27 14:13:06 +08:00
|
|
|
# CHECK-NEXT: Version: 0
|
|
|
|
|
# CHECK-NEXT: ExceptionData: No
|
|
|
|
|
# CHECK-NEXT: EpiloguePacked: No
|
|
|
|
|
# CHECK-NEXT: EpilogueScopes: 1
|
|
|
|
|
# CHECK-NEXT: ByteCodeLength: 28
|
|
|
|
|
# CHECK-NEXT: Prologue [
|
|
|
|
|
# CHECK-NEXT: 0xc808 ; stp x19, x20, [sp, #64]
|
|
|
|
|
# CHECK-NEXT: 0xd0c7 ; str x22, [sp, #56]
|
|
|
|
|
# CHECK-NEXT: 0xd086 ; str x21, [sp, #48]
|
|
|
|
|
# CHECK-NEXT: 0xc904 ; stp x23, x24, [sp, #32]
|
|
|
|
|
# CHECK-NEXT: 0xc982 ; stp x25, x26, [sp, #16]
|
|
|
|
|
# CHECK-NEXT: 0xce09 ; stp x27, x28, [sp, #-80]!
|
|
|
|
|
# CHECK-NEXT: 0xe4 ; end
|
|
|
|
|
# CHECK-NEXT: ]
|
|
|
|
|
# CHECK-NEXT: EpilogueScopes [
|
|
|
|
|
# CHECK-NEXT: EpilogueScope {
|
2019-08-07 20:41:38 +08:00
|
|
|
# CHECK-NEXT: StartOffset: 16
|
2018-10-27 14:13:06 +08:00
|
|
|
# CHECK-NEXT: EpilogueStartIndex: 13
|
|
|
|
|
# CHECK-NEXT: Opcodes [
|
|
|
|
|
# CHECK-NEXT: 0xc808 ; ldp x19, x20, [sp, #64]
|
|
|
|
|
# CHECK-NEXT: 0xd086 ; ldr x21, [sp, #48]
|
|
|
|
|
# CHECK-NEXT: 0xe3 ; nop
|
|
|
|
|
# CHECK-NEXT: 0xd0c7 ; ldr x22, [sp, #56]
|
|
|
|
|
# CHECK-NEXT: 0xc904 ; ldp x23, x24, [sp, #32]
|
|
|
|
|
# CHECK-NEXT: 0xc982 ; ldp x25, x26, [sp, #16]
|
|
|
|
|
# CHECK-NEXT: 0xce09 ; ldp x27, x28, [sp], #80
|
|
|
|
|
# CHECK-NEXT: 0xe4 ; end
|
|
|
|
|
# CHECK-NEXT: ]
|
|
|
|
|
# CHECK-NEXT: }
|
|
|
|
|
# CHECK-NEXT: ]
|
|
|
|
|
# CHECK-NEXT: }
|
2019-08-07 20:41:38 +08:00
|
|
|
|
|
|
|
|
# Check that the load-store optimizer does not merge the two
|
|
|
|
|
# callee-saved stores in the prologue.
|
|
|
|
|
# CHECK-LDSTOPT: name: test
|
|
|
|
|
# CHECK-LDSTOPT: frame-setup STRXui killed $x21, $sp, 6
|
|
|
|
|
# CHECK-LDSTOPT: frame-setup STRXui killed $x22, $sp, 7
|
[AArch64] Generate and parse SEH assembly directives
This ensures that you get the same output regardless if generating
code directly to an object file or if generating assembly and
assembling that.
Add implementations of the EmitARM64WinCFI*() methods in
AArch64TargetAsmStreamer, and fill in one blank in MCAsmStreamer.
Add corresponding directive handlers in AArch64AsmParser and
COFFAsmParser.
Some SEH directive names have been picked to match the prior art
for SEH assembly directives for x86_64, e.g. the spelling of
".seh_startepilogue" matching the preexisting ".seh_endprologue".
For the directives for saving registers, the exact spelling
from the arm64 documentation is picked, e.g. ".seh_save_reg" (to follow
that naming for all the other ones, e.g. ".seh_save_fregp_x"), while
the corresponding one for x86_64 is plain ".seh_savereg" without the
second underscore.
Directives in the epilogues have the same names as in prologues,
e.g. .seh_savereg, even though the registers are restored, not
saved, at that point.
Differential Revision: https://reviews.llvm.org/D86529
2020-08-07 17:44:48 +08:00
|
|
|
|
|
|
|
|
# ASM-LABEL: test:
|
|
|
|
|
# ASM: .seh_proc test
|
|
|
|
|
# ASM: .seh_save_regp_x x27, 80
|
|
|
|
|
# ASM: .seh_save_regp x25, 16
|
|
|
|
|
# ASM: .seh_save_regp x23, 32
|
|
|
|
|
# ASM: .seh_save_reg x21, 48
|
|
|
|
|
# ASM: .seh_save_reg x22, 56
|
|
|
|
|
# ASM: .seh_save_regp x19, 64
|
|
|
|
|
# ASM: .seh_endprologue
|
|
|
|
|
|
|
|
|
|
# ASM: .seh_startepilogue
|
|
|
|
|
# ASM: .seh_save_regp x19, 64
|
|
|
|
|
# ASM: .seh_save_reg x21, 48
|
|
|
|
|
# ASM: .seh_nop
|
|
|
|
|
# ASM: .seh_save_reg x22, 56
|
|
|
|
|
# ASM: .seh_save_regp x23, 32
|
|
|
|
|
# ASM: .seh_save_regp x25, 16
|
|
|
|
|
# ASM: .seh_save_regp_x x27, 80
|
|
|
|
|
# ASM: .seh_endepilogue
|
|
|
|
|
|
|
|
|
|
# ASM: .seh_endfunclet
|
|
|
|
|
# ASM: .seh_handlerdata
|
|
|
|
|
# ASM: .text
|
|
|
|
|
# ASM: .seh_endproc
|
|
|
|
|
|
2018-10-27 14:13:06 +08:00
|
|
|
...
|
|
|
|
|
---
|
|
|
|
|
name: test
|
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
2019-09-11 19:16:48 +08:00
|
|
|
alignment: 4
|
2018-10-27 14:13:06 +08:00
|
|
|
tracksRegLiveness: true
|
|
|
|
|
hasWinCFI: true
|
|
|
|
|
liveins:
|
|
|
|
|
- { reg: '$w0' }
|
|
|
|
|
frameInfo:
|
|
|
|
|
stackSize: 80
|
|
|
|
|
maxAlignment: 8
|
|
|
|
|
maxCallFrameSize: 0
|
|
|
|
|
hasOpaqueSPAdjustment: true
|
|
|
|
|
stack:
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
|
2018-10-27 14:13:06 +08:00
|
|
|
callee-saved-register: '$x19' }
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 8, stack-id: default,
|
2018-10-27 14:13:06 +08:00
|
|
|
callee-saved-register: '$x20' }
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 2, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default,
|
2018-10-27 14:13:06 +08:00
|
|
|
callee-saved-register: '$x21' }
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 3, type: spill-slot, offset: -32, size: 8, alignment: 8, stack-id: default,
|
2018-10-27 14:13:06 +08:00
|
|
|
callee-saved-register: '$x22' }
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 4, type: spill-slot, offset: -40, size: 8, alignment: 8, stack-id: default,
|
2018-10-27 14:13:06 +08:00
|
|
|
callee-saved-register: '$x23' }
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 5, type: spill-slot, offset: -48, size: 8, alignment: 8, stack-id: default,
|
2018-10-27 14:13:06 +08:00
|
|
|
callee-saved-register: '$x24' }
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 6, type: spill-slot, offset: -56, size: 8, alignment: 8, stack-id: default,
|
2018-10-27 14:13:06 +08:00
|
|
|
callee-saved-register: '$x25' }
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 7, type: spill-slot, offset: -64, size: 8, alignment: 8, stack-id: default,
|
2018-10-27 14:13:06 +08:00
|
|
|
callee-saved-register: '$x26' }
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 8, type: spill-slot, offset: -72, size: 8, alignment: 8, stack-id: default,
|
2018-10-27 14:13:06 +08:00
|
|
|
callee-saved-register: '$x27' }
|
2019-06-17 17:13:29 +08:00
|
|
|
- { id: 9, type: spill-slot, offset: -80, size: 8, alignment: 8, stack-id: default,
|
2018-10-27 14:13:06 +08:00
|
|
|
callee-saved-register: '$x28' }
|
|
|
|
|
body: |
|
|
|
|
|
bb.0.entry:
|
|
|
|
|
liveins: $x0, $x1, $x27, $x28, $x25, $x26, $x23, $x24, $x21, $x22, $x19, $x20
|
|
|
|
|
early-clobber $sp = frame-setup STPXpre killed $x27, killed $x28, $sp, -10 :: (store 8 into %stack.8), (store 8 into %stack.9)
|
|
|
|
|
frame-setup SEH_SaveRegP_X 27, 28, -80
|
|
|
|
|
frame-setup STPXi killed $x25, killed $x26, $sp, 2 :: (store 8 into %stack.6), (store 8 into %stack.7)
|
|
|
|
|
frame-setup SEH_SaveRegP 25, 26, 16
|
|
|
|
|
frame-setup STPXi killed $x23, killed $x24, $sp, 4 :: (store 8 into %stack.4), (store 8 into %stack.5)
|
|
|
|
|
frame-setup SEH_SaveRegP 23, 24, 32
|
|
|
|
|
frame-setup STRXui killed $x21, $sp, 6 :: (store 8 into %stack.2)
|
|
|
|
|
frame-setup SEH_SaveReg 21, 48
|
|
|
|
|
frame-setup STRXui killed $x22, $sp, 7 :: (store 8 into %stack.3)
|
|
|
|
|
frame-setup SEH_SaveReg 22, 56
|
|
|
|
|
frame-setup STPXi killed $x19, killed $x20, $sp, 8 :: (store 8 into %stack.0), (store 8 into %stack.1)
|
|
|
|
|
frame-setup SEH_SaveRegP 19, 20, 64
|
|
|
|
|
frame-setup SEH_PrologEnd
|
|
|
|
|
$x19 = ADDXrr $x0, killed $x1
|
|
|
|
|
$x20 = ADDXrr $x19, killed $x0
|
|
|
|
|
$x21 = ADDXrr $x20, killed $x19
|
|
|
|
|
$x22 = ADDXrr $x21, killed $x20
|
|
|
|
|
$x23 = ADDXrr $x22, killed $x21
|
|
|
|
|
$x24 = ADDXrr $x23, killed $x22
|
|
|
|
|
$x25 = ADDXrr $x24, killed $x23
|
|
|
|
|
$x26 = ADDXrr $x25, killed $x24
|
|
|
|
|
$x27 = ADDXrr $x26, killed $x25
|
|
|
|
|
$x28 = ADDXrr $x27, killed $x26
|
|
|
|
|
frame-destroy SEH_EpilogStart
|
|
|
|
|
$x19, $x20 = frame-destroy LDPXi $sp, 8 :: (load 8 from %stack.0), (load 8 from %stack.1)
|
|
|
|
|
frame-destroy SEH_SaveRegP 19, 20, 64
|
|
|
|
|
$x21 = frame-destroy LDRXui $sp, 6 :: (load 8 from %stack.2)
|
|
|
|
|
frame-destroy SEH_SaveReg 21, 48
|
|
|
|
|
$x0 = COPY $x28
|
|
|
|
|
frame-destroy SEH_Nop
|
|
|
|
|
$x21 = frame-destroy LDRXui $sp, 6 :: (load 8 from %stack.2)
|
|
|
|
|
frame-destroy SEH_SaveReg 22, 56
|
|
|
|
|
$x23, $x24 = frame-destroy LDPXi $sp, 4 :: (load 8 from %stack.4), (load 8 from %stack.5)
|
|
|
|
|
frame-destroy SEH_SaveRegP 23, 24, 32
|
|
|
|
|
$x25, $x26 = frame-destroy LDPXi $sp, 2 :: (load 8 from %stack.6), (load 8 from %stack.7)
|
|
|
|
|
frame-destroy SEH_SaveRegP 25, 26, 16
|
|
|
|
|
early-clobber $sp, $x27, $x28 = frame-destroy LDPXpost $sp, 10 :: (load 8 from %stack.8), (load 8 from %stack.9)
|
|
|
|
|
frame-destroy SEH_SaveRegP_X 27, 28, -80
|
|
|
|
|
frame-destroy SEH_EpilogEnd
|
|
|
|
|
RET_ReallyLR implicit $x0
|
|
|
|
|
|
|
|
|
|
...
|