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llvm-project/clang/test/Preprocessor/x86_target_features.c

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Convert test to FileCheck. llvm-svn: 185645
2013-07-04 23:08:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=core2 -msse4 -x c -E -dM -o - %s | FileCheck --check-prefix=SSE4 %s
More x86 target feature support. - Apologies for the extremely gross code duplication, I want to get this working and then decide how to get this information out of the back end. - This replaces -m[no-]sse4[12] by -m[no-]sse4, it appears gcc doesn't distinguish them? - -msse, etc. now properly disable/enable related features. - Don't always define __SSE3__... - The main missing functionality bit here is that we don't initialize the features based on the CPU for all -march options. llvm-svn: 71117
2009-05-07 05:07:50 +08:00
Convert test to FileCheck. llvm-svn: 185645
2013-07-04 23:08:20 +08:00
// SSE4: #define __SSE2_MATH__ 1
// SSE4: #define __SSE2__ 1
// SSE4: #define __SSE3__ 1
// SSE4: #define __SSE4_1__ 1
// SSE4: #define __SSE4_2__ 1
// SSE4: #define __SSE_MATH__ 1
// SSE4: #define __SSE__ 1
// SSE4: #define __SSSE3__ 1
More x86 target feature support. - Apologies for the extremely gross code duplication, I want to get this working and then decide how to get this information out of the back end. - This replaces -m[no-]sse4[12] by -m[no-]sse4, it appears gcc doesn't distinguish them? - -msse, etc. now properly disable/enable related features. - Don't always define __SSE3__... - The main missing functionality bit here is that we don't initialize the features based on the CPU for all -march options. llvm-svn: 71117
2009-05-07 05:07:50 +08:00
Make the msse4/mno-sse4 flags aliases of the maximum sse values they enable/disable. This fixes two things: a) sse4 isn't actually a target feature, don't treat it as one. b) we weren't correctly disabling sse4.1 when we'd pass -mno-sse4 after enabling it, thus passing preprocessor directives and (soon) passing the function attribute as well when we shouldn't. llvm-svn: 233223
2015-03-26 06:09:26 +08:00
// RUN: %clang -target i386-unknown-unknown -march=core2 -msse4.1 -mno-sse4 -x c -E -dM -o - %s | FileCheck --check-prefix=NOSSE4 %s
// NOSSE4-NOT: #define __SSE4_1__ 1
Convert test to FileCheck. llvm-svn: 185645
2013-07-04 23:08:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=core2 -msse4 -mno-sse2 -x c -E -dM -o - %s | FileCheck --check-prefix=SSE %s
Handle -march for the LLVM recognized cpu names. - x86 target feature handling should not be feature complete, even if the code quality is lacking. llvm-svn: 71123
2009-05-07 05:56:32 +08:00
Convert test to FileCheck. llvm-svn: 185645
2013-07-04 23:08:20 +08:00
// SSE-NOT: #define __SSE2_MATH__ 1
// SSE-NOT: #define __SSE2__ 1
// SSE-NOT: #define __SSE3__ 1
// SSE-NOT: #define __SSE4_1__ 1
// SSE-NOT: #define __SSE4_2__ 1
// SSE: #define __SSE_MATH__ 1
// SSE: #define __SSE__ 1
// SSE-NOT: #define __SSSE3__ 1
More x86 target feature support. - Apologies for the extremely gross code duplication, I want to get this working and then decide how to get this information out of the back end. - This replaces -m[no-]sse4[12] by -m[no-]sse4, it appears gcc doesn't distinguish them? - -msse, etc. now properly disable/enable related features. - Don't always define __SSE3__... - The main missing functionality bit here is that we don't initialize the features based on the CPU for all -march options. llvm-svn: 71117
2009-05-07 05:07:50 +08:00
Convert test to FileCheck. llvm-svn: 185645
2013-07-04 23:08:20 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentium-m -x c -E -dM -o - %s | FileCheck --check-prefix=SSE2 %s
More x86 target feature support. - Apologies for the extremely gross code duplication, I want to get this working and then decide how to get this information out of the back end. - This replaces -m[no-]sse4[12] by -m[no-]sse4, it appears gcc doesn't distinguish them? - -msse, etc. now properly disable/enable related features. - Don't always define __SSE3__... - The main missing functionality bit here is that we don't initialize the features based on the CPU for all -march options. llvm-svn: 71117
2009-05-07 05:07:50 +08:00
Convert test to FileCheck. llvm-svn: 185645
2013-07-04 23:08:20 +08:00
// SSE2: #define __SSE2_MATH__ 1
// SSE2: #define __SSE2__ 1
// SSE2-NOT: #define __SSE3__ 1
// SSE2-NOT: #define __SSE4_1__ 1
// SSE2-NOT: #define __SSE4_2__ 1
// SSE2: #define __SSE_MATH__ 1
// SSE2: #define __SSE__ 1
// SSE2-NOT: #define __SSSE3__ 1
Centralize the logic for handling -m* options and fix pr16943. This moves the logic for handling -mfoo -mno-foo from the driver to -cc1. It also changes -cc1 to apply the options in order, fixing pr16943. The handling of -mno-mmx -msse is now an explicit special case. llvm-svn: 188817
2013-08-21 02:57:55 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentium-m -mno-sse -mavx -x c -E -dM -o - %s | FileCheck --check-prefix=AVX %s
// AVX: #define __AVX__ 1
// AVX: #define __SSE2_MATH__ 1
// AVX: #define __SSE2__ 1
// AVX: #define __SSE3__ 1
// AVX: #define __SSE4_1__ 1
// AVX: #define __SSE4_2__ 1
// AVX: #define __SSE_MATH__ 1
// AVX: #define __SSE__ 1
// AVX: #define __SSSE3__ 1
Don't disable SSE4A when disabling AVX. Thanks for Craig Topper for noticing it. llvm-svn: 188902
2013-08-21 21:28:02 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentium-m -mxop -mno-avx -x c -E -dM -o - %s | FileCheck --check-prefix=SSE4A %s
// SSE4A: #define __SSE2_MATH__ 1
// SSE4A: #define __SSE2__ 1
// SSE4A: #define __SSE3__ 1
// SSE4A: #define __SSE4A__ 1
// SSE4A: #define __SSE4_1__ 1
// SSE4A: #define __SSE4_2__ 1
// SSE4A: #define __SSE_MATH__ 1
// SSE4A: #define __SSE__ 1
// SSE4A: #define __SSSE3__ 1
Add test cases for avx512 feature flags. Fix typo in avx512pf options. llvm-svn: 188984
2013-08-22 12:32:55 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512f -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512F %s
// AVX512F: #define __AVX2__ 1
// AVX512F: #define __AVX512F__ 1
// AVX512F: #define __AVX__ 1
// AVX512F: #define __SSE2_MATH__ 1
// AVX512F: #define __SSE2__ 1
// AVX512F: #define __SSE3__ 1
// AVX512F: #define __SSE4_1__ 1
// AVX512F: #define __SSE4_2__ 1
// AVX512F: #define __SSE_MATH__ 1
// AVX512F: #define __SSE__ 1
// AVX512F: #define __SSSE3__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512cd -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512CD %s
// AVX512CD: #define __AVX2__ 1
// AVX512CD: #define __AVX512CD__ 1
// AVX512CD: #define __AVX512F__ 1
// AVX512CD: #define __AVX__ 1
// AVX512CD: #define __SSE2_MATH__ 1
// AVX512CD: #define __SSE2__ 1
// AVX512CD: #define __SSE3__ 1
// AVX512CD: #define __SSE4_1__ 1
// AVX512CD: #define __SSE4_2__ 1
// AVX512CD: #define __SSE_MATH__ 1
// AVX512CD: #define __SSE__ 1
// AVX512CD: #define __SSSE3__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512er -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512ER %s
// AVX512ER: #define __AVX2__ 1
// AVX512ER: #define __AVX512ER__ 1
// AVX512ER: #define __AVX512F__ 1
// AVX512ER: #define __AVX__ 1
// AVX512ER: #define __SSE2_MATH__ 1
// AVX512ER: #define __SSE2__ 1
// AVX512ER: #define __SSE3__ 1
// AVX512ER: #define __SSE4_1__ 1
// AVX512ER: #define __SSE4_2__ 1
// AVX512ER: #define __SSE_MATH__ 1
// AVX512ER: #define __SSE__ 1
// AVX512ER: #define __SSSE3__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512pf -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512PF %s
// AVX512PF: #define __AVX2__ 1
// AVX512PF: #define __AVX512F__ 1
// AVX512PF: #define __AVX512PF__ 1
// AVX512PF: #define __AVX__ 1
// AVX512PF: #define __SSE2_MATH__ 1
// AVX512PF: #define __SSE2__ 1
// AVX512PF: #define __SSE3__ 1
// AVX512PF: #define __SSE4_1__ 1
// AVX512PF: #define __SSE4_2__ 1
// AVX512PF: #define __SSE_MATH__ 1
// AVX512PF: #define __SSE__ 1
// AVX512PF: #define __SSSE3__ 1
[SKX] Enabling SKX target (Skylake server chip) a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
2014-07-30 21:53:40 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512dq -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512DQ %s
// AVX512DQ: #define __AVX2__ 1
// AVX512DQ: #define __AVX512DQ__ 1
// AVX512DQ: #define __AVX512F__ 1
// AVX512DQ: #define __AVX__ 1
// AVX512DQ: #define __SSE2_MATH__ 1
// AVX512DQ: #define __SSE2__ 1
// AVX512DQ: #define __SSE3__ 1
// AVX512DQ: #define __SSE4_1__ 1
// AVX512DQ: #define __SSE4_2__ 1
// AVX512DQ: #define __SSE_MATH__ 1
// AVX512DQ: #define __SSE__ 1
// AVX512DQ: #define __SSSE3__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bw -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512BW %s
// AVX512BW: #define __AVX2__ 1
// AVX512BW: #define __AVX512BW__ 1
// AVX512BW: #define __AVX512F__ 1
// AVX512BW: #define __AVX__ 1
// AVX512BW: #define __SSE2_MATH__ 1
// AVX512BW: #define __SSE2__ 1
// AVX512BW: #define __SSE3__ 1
// AVX512BW: #define __SSE4_1__ 1
// AVX512BW: #define __SSE4_2__ 1
// AVX512BW: #define __SSE_MATH__ 1
// AVX512BW: #define __SSE__ 1
// AVX512BW: #define __SSSE3__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vl -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512VL %s
// AVX512VL: #define __AVX2__ 1
// AVX512VL: #define __AVX512F__ 1
// AVX512VL: #define __AVX512VL__ 1
// AVX512VL: #define __AVX__ 1
// AVX512VL: #define __SSE2_MATH__ 1
// AVX512VL: #define __SSE2__ 1
// AVX512VL: #define __SSE3__ 1
// AVX512VL: #define __SSE4_1__ 1
// AVX512VL: #define __SSE4_2__ 1
// AVX512VL: #define __SSE_MATH__ 1
// AVX512VL: #define __SSE__ 1
// AVX512VL: #define __SSSE3__ 1
Add test cases for avx512 feature flags. Fix typo in avx512pf options. llvm-svn: 188984
2013-08-22 12:32:55 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512pf -mno-avx512f -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512F2 %s
// AVX512F2: #define __AVX2__ 1
// AVX512F2-NOT: #define __AVX512F__ 1
// AVX512F2-NOT: #define __AVX512PF__ 1
// AVX512F2: #define __AVX__ 1
// AVX512F2: #define __SSE2_MATH__ 1
// AVX512F2: #define __SSE2__ 1
// AVX512F2: #define __SSE3__ 1
// AVX512F2: #define __SSE4_1__ 1
// AVX512F2: #define __SSE4_2__ 1
// AVX512F2: #define __SSE_MATH__ 1
// AVX512F2: #define __SSE__ 1
// AVX512F2: #define __SSSE3__ 1
Separate popcnt and sse4.2 feature control somewhat to match gcc behavior. Enabling sse4.2 will implicitly enable popcnt unless popcnt is explicitly disabled. Disabling sse4.2 will not disable popcnt if popcnt is explicitly enabled. llvm-svn: 190387
2013-09-10 14:55:47 +08:00
[X86] Disabling avx512f should also disable avx512vbmi and avx512ifma. Enabling avx512vbmi or avx512ifma should enable avx512f. Add command line switches and header defines for avx512ifma and avx512vbmi. llvm-svn: 262201
2016-02-29 14:51:38 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512ifma -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512IFMA %s
// AVX512IFMA: #define __AVX2__ 1
// AVX512IFMA: #define __AVX512F__ 1
// AVX512IFMA: #define __AVX512IFMA__ 1
// AVX512IFMA: #define __AVX__ 1
// AVX512IFMA: #define __SSE2_MATH__ 1
// AVX512IFMA: #define __SSE2__ 1
// AVX512IFMA: #define __SSE3__ 1
// AVX512IFMA: #define __SSE4_1__ 1
// AVX512IFMA: #define __SSE4_2__ 1
// AVX512IFMA: #define __SSE_MATH__ 1
// AVX512IFMA: #define __SSE__ 1
// AVX512IFMA: #define __SSSE3__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vbmi -x c -E -dM -o - %s | FileCheck --check-prefix=AVX512VBMI %s
// AVX512VBMI: #define __AVX2__ 1
// AVX512VBMI: #define __AVX512F__ 1
// AVX512VBMI: #define __AVX512VBMI__ 1
// AVX512VBMI: #define __AVX__ 1
// AVX512VBMI: #define __SSE2_MATH__ 1
// AVX512VBMI: #define __SSE2__ 1
// AVX512VBMI: #define __SSE3__ 1
// AVX512VBMI: #define __SSE4_1__ 1
// AVX512VBMI: #define __SSE4_2__ 1
// AVX512VBMI: #define __SSE_MATH__ 1
// AVX512VBMI: #define __SSE__ 1
// AVX512VBMI: #define __SSSE3__ 1
Separate popcnt and sse4.2 feature control somewhat to match gcc behavior. Enabling sse4.2 will implicitly enable popcnt unless popcnt is explicitly disabled. Disabling sse4.2 will not disable popcnt if popcnt is explicitly enabled. llvm-svn: 190387
2013-09-10 14:55:47 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -msse4.2 -x c -E -dM -o - %s | FileCheck --check-prefix=SSE42POPCNT %s
// SSE42POPCNT: #define __POPCNT__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-popcnt -msse4.2 -x c -E -dM -o - %s | FileCheck --check-prefix=SSE42NOPOPCNT %s
// SSE42NOPOPCNT-NOT: #define __POPCNT__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mpopcnt -mno-sse4.2 -x c -E -dM -o - %s | FileCheck --check-prefix=NOSSE42POPCNT %s
// NOSSE42POPCNT: #define __POPCNT__ 1
Fix a bug where -msse followed by -mno-sse would leave MMX enabled. llvm-svn: 190496
2013-09-11 14:48:53 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -msse -x c -E -dM -o - %s | FileCheck --check-prefix=SSEMMX %s
// SSEMMX: #define __MMX__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -msse -mno-sse -x c -E -dM -o - %s | FileCheck --check-prefix=SSENOSSEMMX %s
// SSENOSSEMMX-NOT: #define __MMX__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -msse -mno-mmx -x c -E -dM -o - %s | FileCheck --check-prefix=SSENOMMX %s
// SSENOMMX-NOT: #define __MMX__ 1
Make F16C feature imply AVX. Matches GCC behavior. llvm-svn: 190776
2013-09-16 12:54:13 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mf16c -x c -E -dM -o - %s | FileCheck --check-prefix=F16C %s
// F16C: #define __AVX__ 1
// F16C: #define __F16C__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mf16c -mno-avx -x c -E -dM -o - %s | FileCheck --check-prefix=F16CNOAVX %s
// F16CNOAVX-NOT: #define __AVX__ 1
// F16CNOAVX-NOT: #define __F16C__ 1
Disabling sse2 should disable aes and pclmul support. llvm-svn: 190977
2013-09-19 08:01:05 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mpclmul -x c -E -dM -o - %s | FileCheck --check-prefix=PCLMUL %s
// PCLMUL: #define __PCLMUL__ 1
// PCLMUL: #define __SSE2__ 1
// PCLMUL-NOT: #define __SSE3__ 1
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mpclmul -mno-sse2 -x c -E -dM -o - %s | FileCheck --check-prefix=PCLMULNOSSE2 %s
// PCLMULNOSSE2-NOT: #define __PCLMUL__ 1
// PCLMULNOSSE2-NOT: #define __SSE2__ 1
// PCLMULNOSSE2-NOT: #define __SSE3__ 1
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -maes -x c -E -dM -o - %s | FileCheck --check-prefix=AES %s
// AES: #define __AES__ 1
// AES: #define __SSE2__ 1
// AES-NOT: #define __SSE3__ 1
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -maes -mno-sse2 -x c -E -dM -o - %s | FileCheck --check-prefix=AESNOSSE2 %s
// AESNOSSE2-NOT: #define __AES__ 1
// AESNOSSE2-NOT: #define __SSE2__ 1
// AESNOSSE2-NOT: #define __SSE3__ 1
Add C intrinsics for Intel SHA Extensions Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is enabled. SHA implies SSE2, which is needed for the __m128i type. Also add the -msha/-mno-sha option. llvm-svn: 190999
2013-09-19 21:22:04 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -msha -x c -E -dM -o - %s | FileCheck --check-prefix=SHA %s
// SHA: #define __SHA__ 1
// SHA: #define __SSE2__ 1
// SHA-NOT: #define __SSE3__ 1
Fix broken RUN lines llvm-svn: 201475
2014-02-16 15:28:32 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -msha -mno-sha -x c -E -dM -o - %s | FileCheck --check-prefix=SHANOSHA %s
Add C intrinsics for Intel SHA Extensions Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is enabled. SHA implies SSE2, which is needed for the __m128i type. Also add the -msha/-mno-sha option. llvm-svn: 190999
2013-09-19 21:22:04 +08:00
// SHANOSHA-NOT: #define __SHA__ 1
// SHANOSHA-NOT: #define __SSE2__ 1
Fix broken RUN lines llvm-svn: 201475
2014-02-16 15:28:32 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -msha -mno-sse2 -x c -E -dM -o - %s | FileCheck --check-prefix=SHANOSSE2 %s
Add C intrinsics for Intel SHA Extensions Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is enabled. SHA implies SSE2, which is needed for the __m128i type. Also add the -msha/-mno-sha option. llvm-svn: 190999
2013-09-19 21:22:04 +08:00
Fix broken RUN lines llvm-svn: 201475
2014-02-16 15:28:32 +08:00
// SHANOSSE2-NOT: #define __SHA__ 1
// SHANOSSE2-NOT: #define __SSE2__ 1
// SHANOSSE2-NOT: #define __SSE3__ 1
Adding -mtbm and -mno-tbm command line options to the clang front end for the x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is enabled. Otherwise there should be no functionality change to existing features. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693 llvm-svn: 191326
2013-09-25 03:00:58 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mtbm -x c -E -dM -o - %s | FileCheck --check-prefix=TBM %s
// TBM: #define __TBM__ 1
// RUN: %clang -target i386-unknown-unknown -march=bdver2 -mno-tbm -x c -E -dM -o - %s | FileCheck --check-prefix=NOTBM %s
// NOTBM-NOT: #define __TBM__ 1
Add support for -mcx16, and predefine __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 when it is enabled. Also enable it on the same architectures that GCC does. llvm-svn: 192045
2013-10-06 04:14:27 +08:00
// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck --check-prefix=MCX16 %s
// MCX16: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
Enabling 3DNow! prefetch instruction support for a few AMD processors in the clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
2013-10-17 03:07:02 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -x c -E -dM -o - %s | FileCheck --check-prefix=PRFCHW %s
// PRFCHW: #define __PRFCHW__ 1
// RUN: %clang -target i386-unknown-unknown -march=btver2 -mno-prfchw -x c -E -dM -o - %s | FileCheck --check-prefix=NOPRFCHW %s
// NOPRFCHW-NOT: #define __PRFCHW__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -m3dnow -x c -E -dM -o - %s | FileCheck --check-prefix=3DNOWPRFCHW %s
// 3DNOWPRFCHW: #define __PRFCHW__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-prfchw -m3dnow -x c -E -dM -o - %s | FileCheck --check-prefix=3DNOWNOPRFCHW %s
// 3DNOWNOPRFCHW-NOT: #define __PRFCHW__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -mno-3dnow -x c -E -dM -o - %s | FileCheck --check-prefix=NO3DNOWPRFCHW %s
// NO3DNOWPRFCHW: #define __PRFCHW__ 1
[x86] Enable broadwell target in clang. Added -madx option llvm-svn: 218116
2014-09-19 17:53:48 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -madx -x c -E -dM -o - %s | FileCheck --check-prefix=ADX %s
// ADX: #define __ADX__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mrdseed -x c -E -dM -o - %s | FileCheck --check-prefix=RDSEED %s
// RDSEED: #define __RDSEED__ 1
[X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
2015-10-15 13:23:38 +08:00
// RUN: %clang -target i386-unknown-unknown -march=atom -mxsave -x c -E -dM -o - %s | FileCheck --check-prefix=XSAVE %s
// XSAVE: #define __XSAVE__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mxsaveopt -x c -E -dM -o - %s | FileCheck --check-prefix=XSAVEOPT %s
// XSAVEOPT: #define __XSAVEOPT__ 1
// XSAVEOPT: #define __XSAVE__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mxsavec -x c -E -dM -o - %s | FileCheck --check-prefix=XSAVEC %s
// XSAVEC: #define __XSAVEC__ 1
// XSAVEC: #define __XSAVE__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mxsaves -x c -E -dM -o - %s | FileCheck --check-prefix=XSAVES %s
// XSAVES: #define __XSAVES__ 1
// XSAVES: #define __XSAVE__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mxsaveopt -mno-xsave -x c -E -dM -o - %s | FileCheck --check-prefix=NOXSAVE %s
// NOXSAVE-NOT: #define __XSAVEOPT__ 1
// NOXSAVE-NOT: #define __XSAVE__ 1