llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir

# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s
# REQUIRES: global-isel

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64-apple-ios"
  define void @test_vector_add() {
  entry:
    ret void
  }
...

---
name:            test_vector_add
isSSA:           true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body: |
  bb.0.entry:
    liveins: %q0, %q1, %q2, %q3
    ; CHECK-LABEL: name: test_vector_add
    ; CHECK-DAG: [[LHS_LO:%.*]](128), [[LHS_HI:%.*]](128) = G_EXTRACT { <2 x s64> } %0, 0, 128
    ; CHECK-DAG: [[RHS_LO:%.*]](128), [[RHS_HI:%.*]](128) = G_EXTRACT { <2 x s64> } %1, 0, 128
    ; CHECK: [[RES_LO:%.*]](128) = G_ADD { <2 x s64> } [[LHS_LO]], [[RHS_LO]]
    ; CHECK: [[RES_HI:%.*]](128) = G_ADD { <2 x s64> } [[LHS_HI]], [[RHS_HI]]
    ; CHECK: %2(256) = G_SEQUENCE { <4 x s64> } [[RES_LO]], [[RES_HI]]

    %0(256) = G_SEQUENCE { <4 x s64> } %q0, %q1
    %1(256) = G_SEQUENCE { <4 x s64> } %q2, %q3
    %2(256) = G_ADD { <4 x s64> } %0, %1
    %q0, %q1 = G_EXTRACT { <2 x s64> } %2, 0, 128
...