2015-11-24 05:33:58 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
2016-10-10 14:25:42 +08:00
|
|
|
; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
|
|
|
|
; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
|
|
|
|
; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512vl,avx512bw | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
|
2014-12-06 09:31:07 +08:00
|
|
|
|
|
|
|
define <8 x i16> @test_llvm_x86_sse41_pmovsxbw(<16 x i8>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbw:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovsxbw (%rdi), %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovsxbw:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <16 x i8>, <16 x i8>* %a, align 1
|
2015-09-23 16:48:33 +08:00
|
|
|
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
%3 = sext <8 x i8> %2 to <8 x i16>
|
|
|
|
ret <8 x i16> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @test_llvm_x86_sse41_pmovsxbd(<16 x i8>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbd:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovsxbd (%rdi), %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovsxbd:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <16 x i8>, <16 x i8>* %a, align 1
|
2015-09-23 16:48:33 +08:00
|
|
|
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
%3 = sext <4 x i8> %2 to <4 x i32>
|
|
|
|
ret <4 x i32> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <2 x i64> @test_llvm_x86_sse41_pmovsxbq(<16 x i8>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovsxbq (%rdi), %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovsxbq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <16 x i8>, <16 x i8>* %a, align 1
|
2015-09-23 16:48:33 +08:00
|
|
|
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
|
|
|
|
%3 = sext <2 x i8> %2 to <2 x i64>
|
|
|
|
ret <2 x i64> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @test_llvm_x86_sse41_pmovsxwd(<8 x i16>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwd:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovsxwd (%rdi), %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovsxwd:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <8 x i16>, <8 x i16>* %a, align 1
|
2015-09-23 16:48:33 +08:00
|
|
|
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
%3 = sext <4 x i16> %2 to <4 x i32>
|
|
|
|
ret <4 x i32> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <2 x i64> @test_llvm_x86_sse41_pmovsxwq(<8 x i16>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovsxwq (%rdi), %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovsxwq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <8 x i16>, <8 x i16>* %a, align 1
|
2015-09-23 16:48:33 +08:00
|
|
|
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
|
|
|
|
%3 = sext <2 x i16> %2 to <2 x i64>
|
|
|
|
ret <2 x i64> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <2 x i64> @test_llvm_x86_sse41_pmovsxdq(<4 x i32>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovsxdq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovsxdq (%rdi), %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovsxdq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovsxdq (%rdi), %xmm0
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <4 x i32>, <4 x i32>* %a, align 1
|
2015-09-23 16:48:33 +08:00
|
|
|
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
|
|
|
|
%3 = sext <2 x i32> %2 to <2 x i64>
|
|
|
|
ret <2 x i64> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i16> @test_llvm_x86_sse41_pmovzxbw(<16 x i8>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbw:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovzxbw:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <16 x i8>, <16 x i8>* %a, align 1
|
2016-05-29 02:03:41 +08:00
|
|
|
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
%3 = zext <8 x i8> %2 to <8 x i16>
|
|
|
|
ret <8 x i16> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @test_llvm_x86_sse41_pmovzxbd(<16 x i8>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbd:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovzxbd:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <16 x i8>, <16 x i8>* %a, align 1
|
2016-05-29 02:03:41 +08:00
|
|
|
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
%3 = zext <4 x i8> %2 to <4 x i32>
|
|
|
|
ret <4 x i32> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <2 x i64> @test_llvm_x86_sse41_pmovzxbq(<16 x i8>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovzxbq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <16 x i8>, <16 x i8>* %a, align 1
|
2016-05-29 02:03:41 +08:00
|
|
|
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
|
|
|
|
%3 = zext <2 x i8> %2 to <2 x i64>
|
|
|
|
ret <2 x i64> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @test_llvm_x86_sse41_pmovzxwd(<8 x i16>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwd:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovzxwd:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <8 x i16>, <8 x i16>* %a, align 1
|
2016-05-29 02:03:41 +08:00
|
|
|
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
%3 = zext <4 x i16> %2 to <4 x i32>
|
|
|
|
ret <4 x i32> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <2 x i64> @test_llvm_x86_sse41_pmovzxwq(<8 x i16>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovzxwq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <8 x i16>, <8 x i16>* %a, align 1
|
2016-05-29 02:03:41 +08:00
|
|
|
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
|
|
|
|
%3 = zext <2 x i16> %2 to <2 x i64>
|
|
|
|
ret <2 x i64> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
define <2 x i64> @test_llvm_x86_sse41_pmovzxdq(<4 x i32>* %a) {
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-LABEL: test_llvm_x86_sse41_pmovzxdq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_llvm_x86_sse41_pmovzxdq:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: ## %bb.0:
|
2015-10-25 19:55:10 +08:00
|
|
|
; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
|
|
|
|
; AVX-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%1 = load <4 x i32>, <4 x i32>* %a, align 1
|
2016-05-29 02:03:41 +08:00
|
|
|
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
|
|
|
|
%3 = zext <2 x i32> %2 to <2 x i64>
|
|
|
|
ret <2 x i64> %3
|
2014-12-06 09:31:07 +08:00
|
|
|
}
|