2017-05-21 19:13:56 +08:00
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# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
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# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
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2017-05-01 14:30:16 +08:00
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--- |
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2017-07-10 17:07:34 +08:00
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define i8 @test_zext_i1toi8(i1 %a) {
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%r = zext i1 %a to i8
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ret i8 %r
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}
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define i16 @test_zext_i1toi16(i1 %a) {
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%r = zext i1 %a to i16
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ret i16 %r
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}
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2017-05-10 14:52:58 +08:00
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define i32 @test_zext_i1(i1 %a) {
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%r = zext i1 %a to i32
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ret i32 %r
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}
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2017-05-01 14:30:16 +08:00
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define i32 @test_zext_i8(i8 %val) {
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%r = zext i8 %val to i32
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ret i32 %r
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}
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define i32 @test_zext_i16(i16 %val) {
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%r = zext i16 %val to i32
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ret i32 %r
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}
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define i32 @test_sext_i8(i8 %val) {
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%r = sext i8 %val to i32
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ret i32 %r
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}
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define i32 @test_sext_i16(i16 %val) {
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%r = sext i16 %val to i32
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ret i32 %r
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}
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2017-09-11 17:41:13 +08:00
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define void @test_anyext_i1toi8() { ret void }
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define void @test_anyext_i1toi16() { ret void }
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define void @test_anyext_i1toi32() { ret void }
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define void @test_anyext_i8toi16() { ret void }
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define void @test_anyext_i8toi32() { ret void }
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define void @test_anyext_i16toi32() { ret void }
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2017-07-10 17:07:34 +08:00
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...
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---
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name: test_zext_i1toi8
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# ALL-LABEL: name: test_zext_i1toi8
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' }
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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2017-10-25 02:04:54 +08:00
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# ALL: %0:gr8 = COPY %dil
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# ALL-NEXT: %1:gr8 = AND8ri %0, 1, implicit-def %eflags
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2017-07-10 17:07:34 +08:00
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# ALL-NEXT: %al = COPY %1
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# ALL-NEXT: RET 0, implicit %al
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi
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%0(s1) = COPY %edi
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%1(s8) = G_ZEXT %0(s1)
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%al = COPY %1(s8)
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RET 0, implicit %al
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...
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---
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name: test_zext_i1toi16
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# ALL-LABEL: name: test_zext_i1toi16
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
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# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' }
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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2017-10-25 02:04:54 +08:00
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# ALL: %0:gr8 = COPY %dil
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2017-11-07 05:46:06 +08:00
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# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit
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2017-10-25 02:04:54 +08:00
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# ALL-NEXT: %1:gr16 = AND16ri8 %2, 1, implicit-def %eflags
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2017-07-10 17:07:34 +08:00
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# ALL-NEXT: %ax = COPY %1
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# ALL-NEXT: RET 0, implicit %ax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi
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%0(s1) = COPY %edi
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%1(s16) = G_ZEXT %0(s1)
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%ax = COPY %1(s16)
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RET 0, implicit %ax
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2017-05-10 14:52:58 +08:00
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...
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---
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name: test_zext_i1
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# ALL-LABEL: name: test_zext_i1
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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2017-06-06 16:16:19 +08:00
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# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
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2017-05-10 14:52:58 +08:00
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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2017-10-25 02:04:54 +08:00
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# ALL: %0:gr8 = COPY %dil
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2017-11-07 05:46:06 +08:00
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# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit
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2017-10-25 02:04:54 +08:00
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# ALL-NEXT: %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags
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2017-05-10 14:52:58 +08:00
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi
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%0(s1) = COPY %edi
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%1(s32) = G_ZEXT %0(s1)
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%eax = COPY %1(s32)
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RET 0, implicit %eax
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2017-05-01 14:30:16 +08:00
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...
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---
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name: test_zext_i8
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# ALL-LABEL: name: test_zext_i8
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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2017-06-06 16:16:19 +08:00
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# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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2017-05-01 14:30:16 +08:00
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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2017-10-25 02:04:54 +08:00
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# ALL: %0:gr8 = COPY %dil
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# ALL-NEXT: %1:gr32 = MOVZX32rr8 %0
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2017-05-01 14:30:16 +08:00
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi
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2017-09-17 16:30:42 +08:00
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%0(s8) = COPY %dil
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2017-05-01 14:30:16 +08:00
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%1(s32) = G_ZEXT %0(s8)
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%eax = COPY %1(s32)
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RET 0, implicit %eax
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...
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---
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name: test_zext_i16
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# ALL-LABEL: name: test_zext_i16
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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2017-06-06 16:16:19 +08:00
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# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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2017-05-01 14:30:16 +08:00
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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2017-10-25 02:04:54 +08:00
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# ALL: %0:gr16 = COPY %di
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# ALL-NEXT: %1:gr32 = MOVZX32rr16 %0
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2017-05-01 14:30:16 +08:00
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi
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2017-09-17 16:30:42 +08:00
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%0(s16) = COPY %di
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2017-05-01 14:30:16 +08:00
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%1(s32) = G_ZEXT %0(s16)
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%eax = COPY %1(s32)
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RET 0, implicit %eax
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...
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---
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name: test_sext_i8
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# ALL-LABEL: name: test_sext_i8
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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2017-06-06 16:16:19 +08:00
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# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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2017-05-01 14:30:16 +08:00
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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2017-10-25 02:04:54 +08:00
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# ALL: %0:gr8 = COPY %dil
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# ALL-NEXT: %1:gr32 = MOVSX32rr8 %0
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2017-05-01 14:30:16 +08:00
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi
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2017-09-17 16:30:42 +08:00
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%0(s8) = COPY %dil
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2017-05-01 14:30:16 +08:00
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%1(s32) = G_SEXT %0(s8)
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%eax = COPY %1(s32)
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RET 0, implicit %eax
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...
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---
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name: test_sext_i16
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# ALL-LABEL: name: test_sext_i16
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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2017-06-06 16:16:19 +08:00
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# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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2017-05-01 14:30:16 +08:00
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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2017-10-25 02:04:54 +08:00
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# ALL: %0:gr16 = COPY %di
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# ALL-NEXT: %1:gr32 = MOVSX32rr16 %0
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2017-05-01 14:30:16 +08:00
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi
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2017-09-17 16:30:42 +08:00
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%0(s16) = COPY %di
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2017-05-01 14:30:16 +08:00
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%1(s32) = G_SEXT %0(s16)
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%eax = COPY %1(s32)
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RET 0, implicit %eax
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...
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2017-09-11 17:41:13 +08:00
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---
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name: test_anyext_i1toi8
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# ALL-LABEL: name: test_anyext_i1toi8
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alignment: 4
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legalized: true
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regBankSelected: true
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# X32: registers:
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# X32-NEXT: - { id: 0, class: gr32_abcd, preferred-register: '' }
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# X32-NEXT: - { id: 1, class: gr8, preferred-register: '' }
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# X32-NEXT: - { id: 2, class: gr8, preferred-register: '' }
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#
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# X64: registers:
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# X64-NEXT: - { id: 0, class: gr32, preferred-register: '' }
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# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' }
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# X64-NEXT: - { id: 2, class: gr8, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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2017-10-25 02:04:54 +08:00
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# X32: %0:gr32_abcd = COPY %edi
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# X64: %0:gr32 = COPY %edi
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# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
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# ALL-NEXT: %2:gr8 = COPY %1
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2017-09-11 17:41:13 +08:00
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# ALL-NEXT: %al = COPY %2
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# ALL-NEXT: RET 0, implicit %al
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi
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%0(s32) = COPY %edi
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%1(s1) = G_TRUNC %0(s32)
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%2(s8) = G_ANYEXT %1(s1)
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%al = COPY %2(s8)
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RET 0, implicit %al
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...
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---
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name: test_anyext_i1toi16
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# ALL-LABEL: name: test_anyext_i1toi16
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alignment: 4
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legalized: true
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regBankSelected: true
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# X32: registers:
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# X32-NEXT: - { id: 0, class: gr32_abcd, preferred-register: '' }
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# X32-NEXT: - { id: 1, class: gr8, preferred-register: '' }
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# X32-NEXT: - { id: 2, class: gr16, preferred-register: '' }
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#
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# X64: registers:
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# X64-NEXT: - { id: 0, class: gr32, preferred-register: '' }
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# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' }
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# X64-NEXT: - { id: 2, class: gr16, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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2017-10-25 02:04:54 +08:00
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# X32: %0:gr32_abcd = COPY %edi
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# X64: %0:gr32 = COPY %edi
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# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
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2017-11-07 05:46:06 +08:00
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# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
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2017-09-11 17:41:13 +08:00
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# ALL-NEXT: %ax = COPY %2
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# ALL-NEXT: RET 0, implicit %ax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi
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%0(s32) = COPY %edi
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%1(s1) = G_TRUNC %0(s32)
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%2(s16) = G_ANYEXT %1(s1)
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%ax = COPY %2(s16)
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RET 0, implicit %ax
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...
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---
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name: test_anyext_i1toi32
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# ALL-LABEL: name: test_anyext_i1toi32
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alignment: 4
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|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
# X32: registers:
|
|
|
|
# X32-NEXT: - { id: 0, class: gr32_abcd, preferred-register: '' }
|
|
|
|
# X32-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
|
|
|
# X32-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
|
|
|
#
|
|
|
|
# X64: registers:
|
|
|
|
# X64-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
|
|
|
# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
|
|
|
# X64-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
- { id: 2, class: gpr }
|
2017-10-25 02:04:54 +08:00
|
|
|
# X32: %0:gr32_abcd = COPY %edi
|
|
|
|
# X64: %0:gr32 = COPY %edi
|
|
|
|
# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
|
2017-11-07 05:46:06 +08:00
|
|
|
# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
|
2017-09-11 17:41:13 +08:00
|
|
|
# ALL-NEXT: %eax = COPY %2
|
|
|
|
# ALL-NEXT: RET 0, implicit %eax
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %edi
|
|
|
|
|
|
|
|
%0(s32) = COPY %edi
|
|
|
|
%1(s1) = G_TRUNC %0(s32)
|
|
|
|
%2(s32) = G_ANYEXT %1(s1)
|
|
|
|
%eax = COPY %2(s32)
|
|
|
|
RET 0, implicit %eax
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_anyext_i8toi16
|
|
|
|
# ALL-LABEL: name: test_anyext_i8toi16
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
# X32: registers:
|
|
|
|
# X32-NEXT: - { id: 0, class: gr32_abcd, preferred-register: '' }
|
|
|
|
# X32-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
|
|
|
# X32-NEXT: - { id: 2, class: gr16, preferred-register: '' }
|
|
|
|
#
|
|
|
|
# X64: registers:
|
|
|
|
# X64-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
|
|
|
# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
|
|
|
# X64-NEXT: - { id: 2, class: gr16, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
- { id: 2, class: gpr }
|
2017-10-25 02:04:54 +08:00
|
|
|
# X32: %0:gr32_abcd = COPY %edi
|
|
|
|
# X64: %0:gr32 = COPY %edi
|
|
|
|
# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
|
2017-11-07 05:46:06 +08:00
|
|
|
# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
|
2017-09-11 17:41:13 +08:00
|
|
|
# ALL-NEXT: %ax = COPY %2
|
|
|
|
# ALL-NEXT: RET 0, implicit %ax
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %edi
|
|
|
|
|
|
|
|
%0(s32) = COPY %edi
|
|
|
|
%1(s8) = G_TRUNC %0(s32)
|
|
|
|
%2(s16) = G_ANYEXT %1(s8)
|
|
|
|
%ax = COPY %2(s16)
|
|
|
|
RET 0, implicit %ax
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_anyext_i8toi32
|
|
|
|
# ALL-LABEL: name: test_anyext_i8toi32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
# X32: registers:
|
|
|
|
# X32-NEXT: - { id: 0, class: gr32_abcd, preferred-register: '' }
|
|
|
|
# X32-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
|
|
|
# X32-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
|
|
|
#
|
|
|
|
# X64: registers:
|
|
|
|
# X64-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
|
|
|
# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
|
|
|
# X64-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
- { id: 2, class: gpr }
|
2017-10-25 02:04:54 +08:00
|
|
|
# X32: %0:gr32_abcd = COPY %edi
|
|
|
|
# X64: %0:gr32 = COPY %edi
|
|
|
|
# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
|
|
|
|
# ALL-NEXT: %2:gr32 = MOVZX32rr8 %1
|
2017-09-11 17:41:13 +08:00
|
|
|
# ALL-NEXT: %eax = COPY %2
|
|
|
|
# ALL-NEXT: RET 0, implicit %eax
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %edi
|
|
|
|
|
|
|
|
%0(s32) = COPY %edi
|
|
|
|
%1(s8) = G_TRUNC %0(s32)
|
|
|
|
%2(s32) = G_ANYEXT %1(s8)
|
|
|
|
%eax = COPY %2(s32)
|
|
|
|
RET 0, implicit %eax
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_anyext_i16toi32
|
|
|
|
# ALL-LABEL: name: test_anyext_i16toi32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: true
|
|
|
|
# ALL: registers:
|
|
|
|
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
|
|
|
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
|
|
|
|
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: gpr }
|
|
|
|
- { id: 1, class: gpr }
|
|
|
|
- { id: 2, class: gpr }
|
2017-10-25 02:04:54 +08:00
|
|
|
# ALL: %0:gr32 = COPY %edi
|
|
|
|
# ALL-NEXT: %1:gr16 = COPY %0.sub_16bit
|
2017-11-07 05:46:06 +08:00
|
|
|
# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_16bit
|
2017-09-11 17:41:13 +08:00
|
|
|
# ALL-NEXT: %eax = COPY %2
|
|
|
|
# ALL-NEXT: RET 0, implicit %eax
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %edi
|
|
|
|
|
|
|
|
%0(s32) = COPY %edi
|
|
|
|
%1(s16) = G_TRUNC %0(s32)
|
|
|
|
%2(s32) = G_ANYEXT %1(s16)
|
|
|
|
%eax = COPY %2(s32)
|
|
|
|
RET 0, implicit %eax
|
|
|
|
...
|