2013-05-07 00:15:19 +08:00
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//===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2013-05-07 00:15:19 +08:00
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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2016-10-20 16:27:16 +08:00
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//===----------------------------------------------------------------------===//
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2016-10-31 22:33:29 +08:00
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// SystemZ subtarget features
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2016-10-20 16:27:16 +08:00
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//===----------------------------------------------------------------------===//
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2016-10-31 22:33:29 +08:00
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include "SystemZFeatures.td"
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//===----------------------------------------------------------------------===//
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// SystemZ subtarget scheduling models
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//===----------------------------------------------------------------------===//
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2016-10-20 16:27:16 +08:00
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include "SystemZSchedule.td"
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2013-05-07 00:15:19 +08:00
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//===----------------------------------------------------------------------===//
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2016-10-31 22:33:29 +08:00
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// SystemZ supported processors
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2013-05-07 00:15:19 +08:00
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//===----------------------------------------------------------------------===//
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2013-07-20 00:09:03 +08:00
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include "SystemZProcessors.td"
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2013-05-07 00:15:19 +08:00
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//===----------------------------------------------------------------------===//
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// Register file description
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//===----------------------------------------------------------------------===//
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include "SystemZRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Calling convention description
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//===----------------------------------------------------------------------===//
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include "SystemZCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Instruction descriptions
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//===----------------------------------------------------------------------===//
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include "SystemZOperators.td"
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include "SystemZOperands.td"
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include "SystemZPatterns.td"
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include "SystemZInstrFormats.td"
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include "SystemZInstrInfo.td"
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2015-05-06 03:23:40 +08:00
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include "SystemZInstrVector.td"
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2015-05-06 03:28:34 +08:00
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include "SystemZInstrFP.td"
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2017-05-30 18:13:23 +08:00
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include "SystemZInstrHFP.td"
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2017-05-30 18:15:16 +08:00
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include "SystemZInstrDFP.td"
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2017-07-01 04:43:40 +08:00
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include "SystemZInstrSystem.td"
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2013-05-07 00:15:19 +08:00
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2017-12-05 19:24:39 +08:00
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def SystemZInstrInfo : InstrInfo { let guessInstructionProperties = 0; }
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2013-05-07 00:15:19 +08:00
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//===----------------------------------------------------------------------===//
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// Assembly parser
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//===----------------------------------------------------------------------===//
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def SystemZAsmParser : AsmParser {
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let ShouldEmitMatchRegisterName = 0;
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}
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//===----------------------------------------------------------------------===//
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// Top-level target declaration
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//===----------------------------------------------------------------------===//
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def SystemZ : Target {
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let InstructionSet = SystemZInstrInfo;
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let AssemblyParsers = [SystemZAsmParser];
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[MachineOperand][Target] MachineOperand::isRenamable semantics changes
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers. This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.
Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).
Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.
Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.
Clear the IsRenamable bit when changing an operand's register value.
Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.
Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.
Reviewers: qcolombet, MatzeB
Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D43042
llvm-svn: 325931
2018-02-24 02:25:08 +08:00
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let AllowRegisterRenaming = 1;
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2013-05-07 00:15:19 +08:00
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}
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