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llvm-project/llvm/lib/Target/Mips/MipsTargetStreamer.h

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Add a MCTargetStreamer interface. This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
2013-10-08 21:08:17 +08:00
//===-- MipsTargetStreamer.h - Mips Target Streamer ------------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef MIPSTARGETSTREAMER_H
#define MIPSTARGETSTREAMER_H
[Mips] MipsTargetStreamer refactoring. No functionality changes. llvm-svn: 195057
2013-11-19 07:55:27 +08:00
#include "llvm/MC/MCELFStreamer.h"
Re-commit: [mips] Implement .ent, .end, .frame, .mask and .fmask. Patch by Matheus Almeida and Toma Tabacu The lld test failure on the previous attempt to commit was caused by the addition of the .pdr section causing the offsets it was checking to change. This has been fixed by removing the .ent/.end directives from that test since they weren't really needed. llvm-svn: 215535
2014-08-13 18:07:34 +08:00
#include "llvm/MC/MCRegisterInfo.h"
Add a MCTargetStreamer interface. This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
2013-10-08 21:08:17 +08:00
#include "llvm/MC/MCStreamer.h"
[mips] Improve encapsulation of the .MIPS.abiflags implementation and limit scope of related enums Summary: Follow on to r212519 to improve the encapsulation and limit the scope of the enums. Also merged two very similar parser functions, fixed a bug where ASE's were not being reported, and marked CPR1's as being 128-bit when MSA is enabled. Differential Revision: http://reviews.llvm.org/D4384 llvm-svn: 212522
2014-07-08 18:11:38 +08:00
#include "MCTargetDesc/MipsABIFlagsSection.h"
Add a MCTargetStreamer interface. This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
2013-10-08 21:08:17 +08:00
namespace llvm {
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
[mips] Fixed struct/class mismatch introduced in r212522. Clang emits a warning about this. llvm-svn: 212528
2014-07-08 21:13:42 +08:00
struct MipsABIFlagsSection;
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
Add a MCTargetStreamer interface. This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
2013-10-08 21:08:17 +08:00
class MipsTargetStreamer : public MCTargetStreamer {
public:
Construct the MCStreamer before constructing the MCTargetStreamer. This has a few advantages: * Only targets that use a MCTargetStreamer have to worry about it. * There is never a MCTargetStreamer without a MCStreamer, so we can use a reference. * A MCTargetStreamer can talk to the MCStreamer in its constructor. llvm-svn: 200129
2014-01-26 14:06:37 +08:00
MipsTargetStreamer(MCStreamer &S);
[Mips] Add a target streamer when creating a null streamer. Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
2014-06-24 03:43:40 +08:00
virtual void emitDirectiveSetMicroMips();
virtual void emitDirectiveSetNoMicroMips();
virtual void emitDirectiveSetMips16();
virtual void emitDirectiveSetNoMips16();
Convert some easy uses of EmitRawText to TargetStreamer methods. llvm-svn: 200122
2014-01-26 13:06:48 +08:00
[Mips] Add a target streamer when creating a null streamer. Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
2014-06-24 03:43:40 +08:00
virtual void emitDirectiveSetReorder();
virtual void emitDirectiveSetNoReorder();
virtual void emitDirectiveSetMacro();
virtual void emitDirectiveSetNoMacro();
[mips] Add assembler support for .set msa/nomsa directive. Summary: These directives are used to toggle whether the assembler accepts MSA-specific instructions or not. Patch by Matheus Almeida and Toma Tabacu. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4783 llvm-svn: 215099
2014-08-07 20:03:36 +08:00
virtual void emitDirectiveSetMsa();
virtual void emitDirectiveSetNoMsa();
[Mips] Add a target streamer when creating a null streamer. Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
2014-06-24 03:43:40 +08:00
virtual void emitDirectiveSetAt();
virtual void emitDirectiveSetNoAt();
virtual void emitDirectiveEnd(StringRef Name);
Convert some easy uses of EmitRawText to TargetStreamer methods. llvm-svn: 200122
2014-01-26 13:06:48 +08:00
[Mips] Add a target streamer when creating a null streamer. Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
2014-06-24 03:43:40 +08:00
virtual void emitDirectiveEnt(const MCSymbol &Symbol);
virtual void emitDirectiveAbiCalls();
virtual void emitDirectiveNaN2008();
virtual void emitDirectiveNaNLegacy();
virtual void emitDirectiveOptionPic0();
virtual void emitDirectiveOptionPic2();
Print .frame via the target streamer. llvm-svn: 200186
2014-01-27 11:53:56 +08:00
virtual void emitFrame(unsigned StackReg, unsigned StackSize,
[Mips] Add a target streamer when creating a null streamer. Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
2014-06-24 03:43:40 +08:00
unsigned ReturnReg);
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff);
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff);
This patch implements .set mips32r2 directive and sets appropriate feature bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202807
2014-03-04 17:54:09 +08:00
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
virtual void emitDirectiveSetMips1();
virtual void emitDirectiveSetMips2();
virtual void emitDirectiveSetMips3();
virtual void emitDirectiveSetMips4();
virtual void emitDirectiveSetMips5();
virtual void emitDirectiveSetMips32();
[Mips] Add a target streamer when creating a null streamer. Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
2014-06-24 03:43:40 +08:00
virtual void emitDirectiveSetMips32R2();
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
virtual void emitDirectiveSetMips32R6();
[Mips] Add a target streamer when creating a null streamer. Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
2014-06-24 03:43:40 +08:00
virtual void emitDirectiveSetMips64();
virtual void emitDirectiveSetMips64R2();
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
virtual void emitDirectiveSetMips64R6();
[Mips] Add a target streamer when creating a null streamer. Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
2014-06-24 03:43:40 +08:00
virtual void emitDirectiveSetDsp();
[mips] Add support for .cpload. Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
2014-04-30 19:28:42 +08:00
// PIC support
[Mips] Add a target streamer when creating a null streamer. Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
2014-06-24 03:43:40 +08:00
virtual void emitDirectiveCpload(unsigned RegNo);
[mips] Move expansion of .cpsetup to target streamer. Summary: There are two functional changes: 1) The directive is not expanded for the ASM->ASM code path. 2) If PIC is not set, there's no expansion for the ASM->OBJ code path (same behaviour as GAS). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3482 llvm-svn: 207741
2014-05-01 18:24:46 +08:00
virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
[Mips] Add a target streamer when creating a null streamer. Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
2014-06-24 03:43:40 +08:00
const MCSymbol &Sym, bool IsReg);
[mips] Add support for -modd-spreg/-mno-odd-spreg Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
2014-07-10 21:38:23 +08:00
/// Emit a '.module fp=value' directive using the given values.
/// Updates the .MIPS.abiflags section
virtual void emitDirectiveModuleFP(MipsABIFlagsSection::FpABIKind Value,
bool Is32BitABI) {
ABIFlagsSection.setFpABI(Value, Is32BitABI);
[mips] Improve encapsulation of the .MIPS.abiflags implementation and limit scope of related enums Summary: Follow on to r212519 to improve the encapsulation and limit the scope of the enums. Also merged two very similar parser functions, fixed a bug where ASE's were not being reported, and marked CPR1's as being 128-bit when MSA is enabled. Differential Revision: http://reviews.llvm.org/D4384 llvm-svn: 212522
2014-07-08 18:11:38 +08:00
}
[mips] Add support for -modd-spreg/-mno-odd-spreg Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
2014-07-10 21:38:23 +08:00
/// Emit a '.module fp=value' directive using the current values of the
/// .MIPS.abiflags section.
void emitDirectiveModuleFP() {
emitDirectiveModuleFP(ABIFlagsSection.getFpABI(),
ABIFlagsSection.Is32BitABI);
}
virtual void emitDirectiveModuleOddSPReg(bool Enabled, bool IsO32ABI);
virtual void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value){};
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
virtual void emitMipsAbiFlags(){};
void setCanHaveModuleDir(bool Can) { canHaveModuleDirective = Can; }
bool getCanHaveModuleDir() { return canHaveModuleDirective; }
// This method enables template classes to set internal abi flags
// structure values.
template <class PredicateLibrary>
void updateABIInfo(const PredicateLibrary &P) {
[mips] Improve encapsulation of the .MIPS.abiflags implementation and limit scope of related enums Summary: Follow on to r212519 to improve the encapsulation and limit the scope of the enums. Also merged two very similar parser functions, fixed a bug where ASE's were not being reported, and marked CPR1's as being 128-bit when MSA is enabled. Differential Revision: http://reviews.llvm.org/D4384 llvm-svn: 212522
2014-07-08 18:11:38 +08:00
ABIFlagsSection.setAllFromPredicates(P);
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
}
[mips] Improve encapsulation of the .MIPS.abiflags implementation and limit scope of related enums Summary: Follow on to r212519 to improve the encapsulation and limit the scope of the enums. Also merged two very similar parser functions, fixed a bug where ASE's were not being reported, and marked CPR1's as being 128-bit when MSA is enabled. Differential Revision: http://reviews.llvm.org/D4384 llvm-svn: 212522
2014-07-08 18:11:38 +08:00
MipsABIFlagsSection &getABIFlagsSection() { return ABIFlagsSection; }
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
protected:
[mips] Improve encapsulation of the .MIPS.abiflags implementation and limit scope of related enums Summary: Follow on to r212519 to improve the encapsulation and limit the scope of the enums. Also merged two very similar parser functions, fixed a bug where ASE's were not being reported, and marked CPR1's as being 128-bit when MSA is enabled. Differential Revision: http://reviews.llvm.org/D4384 llvm-svn: 212522
2014-07-08 18:11:38 +08:00
MipsABIFlagsSection ABIFlagsSection;
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
Re-commit: [mips] Implement .ent, .end, .frame, .mask and .fmask. Patch by Matheus Almeida and Toma Tabacu The lld test failure on the previous attempt to commit was caused by the addition of the .pdr section causing the offsets it was checking to change. This has been fixed by removing the .ent/.end directives from that test since they weren't really needed. llvm-svn: 215535
2014-08-13 18:07:34 +08:00
bool GPRInfoSet;
unsigned GPRBitMask;
int GPROffset;
bool FPRInfoSet;
unsigned FPRBitMask;
int FPROffset;
bool FrameInfoSet;
int FrameOffset;
unsigned FrameReg;
unsigned ReturnReg;
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
private:
bool canHaveModuleDirective;
Add a MCTargetStreamer interface. This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
2013-10-08 21:08:17 +08:00
};
[Mips] MipsTargetStreamer refactoring. No functionality changes. llvm-svn: 195057
2013-11-19 07:55:27 +08:00
// This part is for ascii assembly output
class MipsTargetAsmStreamer : public MipsTargetStreamer {
reverts 195057 per request llvm-svn: 195152
2013-11-20 04:53:28 +08:00
formatted_raw_ostream &OS;
[Mips] MipsTargetStreamer refactoring. No functionality changes. llvm-svn: 195057
2013-11-19 07:55:27 +08:00
public:
Construct the MCStreamer before constructing the MCTargetStreamer. This has a few advantages: * Only targets that use a MCTargetStreamer have to worry about it. * There is never a MCTargetStreamer without a MCStreamer, so we can use a reference. * A MCTargetStreamer can talk to the MCStreamer in its constructor. llvm-svn: 200129
2014-01-26 14:06:37 +08:00
MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
void emitDirectiveSetMicroMips() override;
void emitDirectiveSetNoMicroMips() override;
void emitDirectiveSetMips16() override;
void emitDirectiveSetNoMips16() override;
void emitDirectiveSetReorder() override;
void emitDirectiveSetNoReorder() override;
void emitDirectiveSetMacro() override;
void emitDirectiveSetNoMacro() override;
[mips] Add assembler support for .set msa/nomsa directive. Summary: These directives are used to toggle whether the assembler accepts MSA-specific instructions or not. Patch by Matheus Almeida and Toma Tabacu. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4783 llvm-svn: 215099
2014-08-07 20:03:36 +08:00
void emitDirectiveSetMsa() override;
void emitDirectiveSetNoMsa() override;
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
void emitDirectiveSetAt() override;
void emitDirectiveSetNoAt() override;
void emitDirectiveEnd(StringRef Name) override;
void emitDirectiveEnt(const MCSymbol &Symbol) override;
void emitDirectiveAbiCalls() override;
void emitDirectiveNaN2008() override;
void emitDirectiveNaNLegacy() override;
void emitDirectiveOptionPic0() override;
void emitDirectiveOptionPic2() override;
void emitFrame(unsigned StackReg, unsigned StackSize,
unsigned ReturnReg) override;
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
void emitDirectiveSetMips1() override;
void emitDirectiveSetMips2() override;
void emitDirectiveSetMips3() override;
void emitDirectiveSetMips4() override;
void emitDirectiveSetMips5() override;
void emitDirectiveSetMips32() override;
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
void emitDirectiveSetMips32R2() override;
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
void emitDirectiveSetMips32R6() override;
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
void emitDirectiveSetMips64() override;
void emitDirectiveSetMips64R2() override;
[mips] Add assembler support for '.set mipsX'. Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 llvm-svn: 214709
2014-08-04 20:20:00 +08:00
void emitDirectiveSetMips64R6() override;
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
void emitDirectiveSetDsp() override;
[mips] Add support for .cpload. Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
2014-04-30 19:28:42 +08:00
// PIC support
virtual void emitDirectiveCpload(unsigned RegNo);
[mips] Move expansion of .cpsetup to target streamer. Summary: There are two functional changes: 1) The directive is not expanded for the ASM->ASM code path. 2) If PIC is not set, there's no expansion for the ASM->OBJ code path (same behaviour as GAS). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3482 llvm-svn: 207741
2014-05-01 18:24:46 +08:00
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
const MCSymbol &Sym, bool IsReg) override;
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
// ABI Flags
[mips] Add support for -modd-spreg/-mno-odd-spreg Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
2014-07-10 21:38:23 +08:00
void emitDirectiveModuleFP(MipsABIFlagsSection::FpABIKind Value,
bool Is32BitABI) override;
void emitDirectiveModuleOddSPReg(bool Enabled, bool IsO32ABI) override;
void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value) override;
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
void emitMipsAbiFlags() override;
[Mips] MipsTargetStreamer refactoring. No functionality changes. llvm-svn: 195057
2013-11-19 07:55:27 +08:00
};
// This part is for ELF object output
class MipsTargetELFStreamer : public MipsTargetStreamer {
Replace .mips_hack_stocg with ".set micromips" and ".set nomicromips". This matches what gnu as does and implementing this is easier than arguing about it. llvm-svn: 199181
2014-01-14 12:25:13 +08:00
bool MicroMipsEnabled;
Remove another hasRawTextSupport. To remove this one simply move the end of file logic from the asm printer to the target mc streamer. This removes the last call to hasRawTextSupport from lib/Target. llvm-svn: 200590
2014-02-01 07:10:26 +08:00
const MCSubtargetInfo &STI;
[mips] Add support for '.option pic2'. The directive '.option pic2' enables PIC from assembly source. At the moment none of the macros/directives check the PIC bit but that's going to be fixed relatively soon. For example, the expansion of macros like 'la' depend on the relocation model. llvm-svn: 204803
2014-03-26 21:40:29 +08:00
bool Pic;
[Mips] TargetStreamer Support for .set mips16. This patch updates .set mips16 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that the assembler uses for both ELF and ASCII output for these directives. llvm-svn: 199851
2014-01-23 07:08:42 +08:00
[Mips] MipsTargetStreamer refactoring. No functionality changes. llvm-svn: 195057
2013-11-19 07:55:27 +08:00
public:
Replace .mips_hack_stocg with ".set micromips" and ".set nomicromips". This matches what gnu as does and implementing this is easier than arguing about it. llvm-svn: 199181
2014-01-14 12:25:13 +08:00
bool isMicroMipsEnabled() const { return MicroMipsEnabled; }
[Mips] MipsTargetStreamer refactoring. No functionality changes. llvm-svn: 195057
2013-11-19 07:55:27 +08:00
MCELFStreamer &getStreamer();
Implement the missing bits corresponding to .mips_hack_elf_flags. These were: * noreorder handling on the target object streamer and asm parser. * setting the initial flag bits based on the enabled features. * setting the elf header flag for micromips It is *really* depressing I am the one doing this instead of someone at mips actually taking the time to understand the infrastructure. llvm-svn: 200138
2014-01-26 14:57:13 +08:00
MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
Replace .mips_hack_stocg with ".set micromips" and ".set nomicromips". This matches what gnu as does and implementing this is easier than arguing about it. llvm-svn: 199181
2014-01-14 12:25:13 +08:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
void emitLabel(MCSymbol *Symbol) override;
void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override;
Switch all uses of LLVM_OVERRIDE to just use 'override' directly. llvm-svn: 202621
2014-03-02 17:09:27 +08:00
void finish() override;
Replace .mips_hack_stocg with ".set micromips" and ".set nomicromips". This matches what gnu as does and implementing this is easier than arguing about it. llvm-svn: 199181
2014-01-14 12:25:13 +08:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
2014-04-29 15:58:02 +08:00
void emitDirectiveSetMicroMips() override;
void emitDirectiveSetNoMicroMips() override;
void emitDirectiveSetMips16() override;
void emitDirectiveSetNoReorder() override;
void emitDirectiveEnd(StringRef Name) override;
void emitDirectiveEnt(const MCSymbol &Symbol) override;
void emitDirectiveAbiCalls() override;
void emitDirectiveNaN2008() override;
void emitDirectiveNaNLegacy() override;
void emitDirectiveOptionPic0() override;
void emitDirectiveOptionPic2() override;
void emitFrame(unsigned StackReg, unsigned StackSize,
unsigned ReturnReg) override;
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
[mips] Add support for .cpload. Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
2014-04-30 19:28:42 +08:00
// PIC support
virtual void emitDirectiveCpload(unsigned RegNo);
[mips] Move expansion of .cpsetup to target streamer. Summary: There are two functional changes: 1) The directive is not expanded for the ASM->ASM code path. 2) If PIC is not set, there's no expansion for the ASM->OBJ code path (same behaviour as GAS). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3482 llvm-svn: 207741
2014-05-01 18:24:46 +08:00
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
const MCSymbol &Sym, bool IsReg) override;
[mips] Add support for .cpload. Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
2014-04-30 19:28:42 +08:00
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
// ABI Flags
[mips] Add support for -modd-spreg/-mno-odd-spreg Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
2014-07-10 21:38:23 +08:00
void emitDirectiveModuleOddSPReg(bool Enabled, bool IsO32ABI) override;
Mips.abiflags is a new implicitly generated section that will be present on all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
2014-07-08 16:59:22 +08:00
void emitMipsAbiFlags() override;
[mips] Add support for .cpload. Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
2014-04-30 19:28:42 +08:00
protected:
bool isO32() const { return STI.getFeatureBits() & Mips::FeatureO32; }
bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
[Mips] MipsTargetStreamer refactoring. No functionality changes. llvm-svn: 195057
2013-11-19 07:55:27 +08:00
};
Add a MCTargetStreamer interface. This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
2013-10-08 21:08:17 +08:00
}
#endif