2017-12-06 00:04:45 +08:00
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//===- AArch64ErrataFix.cpp -----------------------------------------------===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2017-12-06 00:04:45 +08:00
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//
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//===----------------------------------------------------------------------===//
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// This file implements Section Patching for the purpose of working around
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2019-09-16 17:38:38 +08:00
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// the AArch64 Cortex-53 errata 843419 that affects r0p0, r0p1, r0p2 and r0p4
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// versions of the core.
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//
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// The general principle is that an erratum sequence of one or
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2017-12-06 00:04:45 +08:00
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// more instructions is detected in the instruction stream, one of the
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// instructions in the sequence is replaced with a branch to a patch sequence
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// of replacement instructions. At the end of the replacement sequence the
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// patch branches back to the instruction stream.
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// This technique is only suitable for fixing an erratum when:
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// - There is a set of necessary conditions required to trigger the erratum that
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// can be detected at static link time.
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// - There is a set of replacement instructions that can be used to remove at
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// least one of the necessary conditions that trigger the erratum.
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// - We can overwrite an instruction in the erratum sequence with a branch to
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// the replacement sequence.
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// - We can place the replacement sequence within range of the branch.
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//===----------------------------------------------------------------------===//
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#include "AArch64ErrataFix.h"
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#include "Config.h"
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#include "LinkerScript.h"
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#include "OutputSections.h"
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#include "Relocations.h"
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2017-12-10 00:56:18 +08:00
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#include "Symbols.h"
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2017-12-06 00:04:45 +08:00
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#include "SyntheticSections.h"
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#include "Target.h"
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2017-12-10 00:56:18 +08:00
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#include "lld/Common/Memory.h"
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2018-03-01 01:38:19 +08:00
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#include "lld/Common/Strings.h"
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2017-12-06 00:04:45 +08:00
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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using namespace llvm;
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using namespace llvm::ELF;
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using namespace llvm::object;
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2018-01-24 03:26:52 +08:00
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using namespace llvm::support;
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2017-12-06 00:04:45 +08:00
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using namespace llvm::support::endian;
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2020-05-15 13:18:58 +08:00
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using namespace lld;
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using namespace lld::elf;
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2017-12-06 00:04:45 +08:00
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// Helper functions to identify instructions and conditions needed to trigger
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// the Cortex-A53-843419 erratum.
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// ADRP
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// | 1 | immlo (2) | 1 | 0 0 0 0 | immhi (19) | Rd (5) |
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static bool isADRP(uint32_t instr) {
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return (instr & 0x9f000000) == 0x90000000;
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}
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// Load and store bit patterns from ARMv8-A ARM ARM.
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// Instructions appear in order of appearance starting from table in
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// C4.1.3 Loads and Stores.
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2019-10-29 09:41:38 +08:00
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// All loads and stores have 1 (at bit position 27), (0 at bit position 25).
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2017-12-06 00:04:45 +08:00
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// | op0 x op1 (2) | 1 op2 0 op3 (2) | x | op4 (5) | xxxx | op5 (2) | x (10) |
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static bool isLoadStoreClass(uint32_t instr) {
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return (instr & 0x0a000000) == 0x08000000;
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}
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// LDN/STN multiple no offset
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// | 0 Q 00 | 1100 | 0 L 00 | 0000 | opcode (4) | size (2) | Rn (5) | Rt (5) |
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// LDN/STN multiple post-indexed
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// | 0 Q 00 | 1100 | 1 L 0 | Rm (5)| opcode (4) | size (2) | Rn (5) | Rt (5) |
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// L == 0 for stores.
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// Utility routine to decode opcode field of LDN/STN multiple structure
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// instructions to find the ST1 instructions.
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// opcode == 0010 ST1 4 registers.
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// opcode == 0110 ST1 3 registers.
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// opcode == 0111 ST1 1 register.
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// opcode == 1010 ST1 2 registers.
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static bool isST1MultipleOpcode(uint32_t instr) {
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return (instr & 0x0000f000) == 0x00002000 ||
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(instr & 0x0000f000) == 0x00006000 ||
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(instr & 0x0000f000) == 0x00007000 ||
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(instr & 0x0000f000) == 0x0000a000;
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}
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static bool isST1Multiple(uint32_t instr) {
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return (instr & 0xbfff0000) == 0x0c000000 && isST1MultipleOpcode(instr);
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}
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// Writes to Rn (writeback).
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static bool isST1MultiplePost(uint32_t instr) {
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return (instr & 0xbfe00000) == 0x0c800000 && isST1MultipleOpcode(instr);
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}
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// LDN/STN single no offset
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// | 0 Q 00 | 1101 | 0 L R 0 | 0000 | opc (3) S | size (2) | Rn (5) | Rt (5)|
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// LDN/STN single post-indexed
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// | 0 Q 00 | 1101 | 1 L R | Rm (5) | opc (3) S | size (2) | Rn (5) | Rt (5)|
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// L == 0 for stores
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// Utility routine to decode opcode field of LDN/STN single structure
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// instructions to find the ST1 instructions.
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// R == 0 for ST1 and ST3, R == 1 for ST2 and ST4.
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// opcode == 000 ST1 8-bit.
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// opcode == 010 ST1 16-bit.
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// opcode == 100 ST1 32 or 64-bit (Size determines which).
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static bool isST1SingleOpcode(uint32_t instr) {
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return (instr & 0x0040e000) == 0x00000000 ||
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(instr & 0x0040e000) == 0x00004000 ||
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(instr & 0x0040e000) == 0x00008000;
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}
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static bool isST1Single(uint32_t instr) {
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return (instr & 0xbfff0000) == 0x0d000000 && isST1SingleOpcode(instr);
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}
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// Writes to Rn (writeback).
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static bool isST1SinglePost(uint32_t instr) {
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return (instr & 0xbfe00000) == 0x0d800000 && isST1SingleOpcode(instr);
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}
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static bool isST1(uint32_t instr) {
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return isST1Multiple(instr) || isST1MultiplePost(instr) ||
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isST1Single(instr) || isST1SinglePost(instr);
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}
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// Load/store exclusive
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// | size (2) 00 | 1000 | o2 L o1 | Rs (5) | o0 | Rt2 (5) | Rn (5) | Rt (5) |
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// L == 0 for Stores.
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static bool isLoadStoreExclusive(uint32_t instr) {
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return (instr & 0x3f000000) == 0x08000000;
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}
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static bool isLoadExclusive(uint32_t instr) {
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return (instr & 0x3f400000) == 0x08400000;
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}
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// Load register literal
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// | opc (2) 01 | 1 V 00 | imm19 | Rt (5) |
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static bool isLoadLiteral(uint32_t instr) {
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return (instr & 0x3b000000) == 0x18000000;
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}
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// Load/store no-allocate pair
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// (offset)
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// | opc (2) 10 | 1 V 00 | 0 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
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// L == 0 for stores.
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// Never writes to register
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static bool isSTNP(uint32_t instr) {
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return (instr & 0x3bc00000) == 0x28000000;
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}
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// Load/store register pair
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// (post-indexed)
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// | opc (2) 10 | 1 V 00 | 1 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
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// L == 0 for stores, V == 0 for Scalar, V == 1 for Simd/FP
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// Writes to Rn.
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static bool isSTPPost(uint32_t instr) {
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return (instr & 0x3bc00000) == 0x28800000;
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}
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// (offset)
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// | opc (2) 10 | 1 V 01 | 0 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
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static bool isSTPOffset(uint32_t instr) {
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return (instr & 0x3bc00000) == 0x29000000;
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}
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// (pre-index)
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// | opc (2) 10 | 1 V 01 | 1 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
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// Writes to Rn.
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static bool isSTPPre(uint32_t instr) {
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return (instr & 0x3bc00000) == 0x29800000;
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}
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static bool isSTP(uint32_t instr) {
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return isSTPPost(instr) || isSTPOffset(instr) || isSTPPre(instr);
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}
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// Load/store register (unscaled immediate)
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// | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 00 | Rn (5) | Rt (5) |
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// V == 0 for Scalar, V == 1 for Simd/FP.
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static bool isLoadStoreUnscaled(uint32_t instr) {
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return (instr & 0x3b000c00) == 0x38000000;
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}
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// Load/store register (immediate post-indexed)
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// | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 01 | Rn (5) | Rt (5) |
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static bool isLoadStoreImmediatePost(uint32_t instr) {
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return (instr & 0x3b200c00) == 0x38000400;
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}
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// Load/store register (unprivileged)
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// | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 10 | Rn (5) | Rt (5) |
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static bool isLoadStoreUnpriv(uint32_t instr) {
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return (instr & 0x3b200c00) == 0x38000800;
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}
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// Load/store register (immediate pre-indexed)
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// | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 11 | Rn (5) | Rt (5) |
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static bool isLoadStoreImmediatePre(uint32_t instr) {
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return (instr & 0x3b200c00) == 0x38000c00;
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}
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// Load/store register (register offset)
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// | size (2) 11 | 1 V 00 | opc (2) 1 | Rm (5) | option (3) S | 10 | Rn | Rt |
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static bool isLoadStoreRegisterOff(uint32_t instr) {
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return (instr & 0x3b200c00) == 0x38200800;
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}
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// Load/store register (unsigned immediate)
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// | size (2) 11 | 1 V 01 | opc (2) | imm12 | Rn (5) | Rt (5) |
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static bool isLoadStoreRegisterUnsigned(uint32_t instr) {
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return (instr & 0x3b000000) == 0x39000000;
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}
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// Rt is always in bit position 0 - 4.
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static uint32_t getRt(uint32_t instr) { return (instr & 0x1f); }
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// Rn is always in bit position 5 - 9.
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static uint32_t getRn(uint32_t instr) { return (instr >> 5) & 0x1f; }
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// C4.1.2 Branches, Exception Generating and System instructions
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// | op0 (3) 1 | 01 op1 (4) | x (22) |
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// op0 == 010 101 op1 == 0xxx Conditional Branch.
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// op0 == 110 101 op1 == 1xxx Unconditional Branch Register.
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// op0 == x00 101 op1 == xxxx Unconditional Branch immediate.
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// op0 == x01 101 op1 == 0xxx Compare and branch immediate.
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// op0 == x01 101 op1 == 1xxx Test and branch immediate.
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static bool isBranch(uint32_t instr) {
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return ((instr & 0xfe000000) == 0xd6000000) || // Cond branch.
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((instr & 0xfe000000) == 0x54000000) || // Uncond branch reg.
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((instr & 0x7c000000) == 0x14000000) || // Uncond branch imm.
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((instr & 0x7c000000) == 0x34000000); // Compare and test branch.
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}
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static bool isV8SingleRegisterNonStructureLoadStore(uint32_t instr) {
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return isLoadStoreUnscaled(instr) || isLoadStoreImmediatePost(instr) ||
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isLoadStoreUnpriv(instr) || isLoadStoreImmediatePre(instr) ||
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isLoadStoreRegisterOff(instr) || isLoadStoreRegisterUnsigned(instr);
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}
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// Note that this function refers to v8.0 only and does not include the
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// additional load and store instructions added for in later revisions of
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// the architecture such as the Atomic memory operations introduced
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// in v8.1.
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static bool isV8NonStructureLoad(uint32_t instr) {
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if (isLoadExclusive(instr))
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return true;
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if (isLoadLiteral(instr))
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return true;
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else if (isV8SingleRegisterNonStructureLoadStore(instr)) {
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// For Load and Store single register, Loads are derived from a
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// combination of the Size, V and Opc fields.
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uint32_t size = (instr >> 30) & 0xff;
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uint32_t v = (instr >> 26) & 0x1;
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uint32_t opc = (instr >> 22) & 0x3;
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// For the load and store instructions that we are decoding.
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// Opc == 0 are all stores.
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// Opc == 1 with a couple of exceptions are loads. The exceptions are:
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// Size == 00 (0), V == 1, Opc == 10 (2) which is a store and
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// Size == 11 (3), V == 0, Opc == 10 (2) which is a prefetch.
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return opc != 0 && !(size == 0 && v == 1 && opc == 2) &&
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!(size == 3 && v == 0 && opc == 2);
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}
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return false;
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}
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// The following decode instructions are only complete up to the instructions
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// needed for errata 843419.
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// Instruction with writeback updates the index register after the load/store.
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static bool hasWriteback(uint32_t instr) {
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return isLoadStoreImmediatePre(instr) || isLoadStoreImmediatePost(instr) ||
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isSTPPre(instr) || isSTPPost(instr) || isST1SinglePost(instr) ||
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isST1MultiplePost(instr);
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}
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// For the load and store class of instructions, a load can write to the
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// destination register, a load and a store can write to the base register when
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// the instruction has writeback.
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static bool doesLoadStoreWriteToReg(uint32_t instr, uint32_t reg) {
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return (isV8NonStructureLoad(instr) && getRt(instr) == reg) ||
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(hasWriteback(instr) && getRn(instr) == reg);
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}
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// Scanner for Cortex-A53 errata 843419
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// Full details are available in the Cortex A53 MPCore revision 0 Software
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// Developers Errata Notice (ARM-EPM-048406).
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//
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// The instruction sequence that triggers the erratum is common in compiled
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// AArch64 code, however it is sensitive to the offset of the sequence within
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// a 4k page. This means that by scanning and fixing the patch after we have
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// assigned addresses we only need to disassemble and fix instances of the
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// sequence in the range of affected offsets.
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//
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// In summary the erratum conditions are a series of 4 instructions:
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// 1.) An ADRP instruction that writes to register Rn with low 12 bits of
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// address of instruction either 0xff8 or 0xffc.
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// 2.) A load or store instruction that can be:
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// - A single register load or store, of either integer or vector registers.
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// - An STP or STNP, of either integer or vector registers.
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// - An Advanced SIMD ST1 store instruction.
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// - Must not write to Rn, but may optionally read from it.
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// 3.) An optional instruction that is not a branch and does not write to Rn.
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// 4.) A load or store from the Load/store register (unsigned immediate) class
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// that uses Rn as the base address register.
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|
//
|
|
|
|
// Note that we do not attempt to scan for Sequence 2 as described in the
|
|
|
|
// Software Developers Errata Notice as this has been assessed to be extremely
|
|
|
|
// unlikely to occur in compiled code. This matches gold and ld.bfd behavior.
|
|
|
|
|
|
|
|
// Return true if the Instruction sequence Adrp, Instr2, and Instr4 match
|
|
|
|
// the erratum sequence. The Adrp, Instr2 and Instr4 correspond to 1.), 2.),
|
|
|
|
// and 4.) in the Scanner for Cortex-A53 errata comment above.
|
|
|
|
static bool is843419ErratumSequence(uint32_t instr1, uint32_t instr2,
|
|
|
|
uint32_t instr4) {
|
|
|
|
if (!isADRP(instr1))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
uint32_t rn = getRt(instr1);
|
|
|
|
return isLoadStoreClass(instr2) &&
|
|
|
|
(isLoadStoreExclusive(instr2) || isLoadLiteral(instr2) ||
|
|
|
|
isV8SingleRegisterNonStructureLoadStore(instr2) || isSTP(instr2) ||
|
|
|
|
isSTNP(instr2) || isST1(instr2)) &&
|
|
|
|
!doesLoadStoreWriteToReg(instr2, rn) &&
|
|
|
|
isLoadStoreRegisterUnsigned(instr4) && getRn(instr4) == rn;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Scan the instruction sequence starting at Offset Off from the base of
|
2019-09-17 17:49:30 +08:00
|
|
|
// InputSection isec. We update Off in this function rather than in the caller
|
|
|
|
// as we can skip ahead much further into the section when we know how many
|
2017-12-06 00:04:45 +08:00
|
|
|
// instructions we've scanned.
|
2019-09-17 17:49:30 +08:00
|
|
|
// Return the offset of the load or store instruction in isec that we want to
|
2017-12-06 00:04:45 +08:00
|
|
|
// patch or 0 if no patch required.
|
|
|
|
static uint64_t scanCortexA53Errata843419(InputSection *isec, uint64_t &off,
|
|
|
|
uint64_t limit) {
|
2018-03-24 08:35:11 +08:00
|
|
|
uint64_t isecAddr = isec->getVA(0);
|
2017-12-06 00:04:45 +08:00
|
|
|
|
2019-09-17 17:49:30 +08:00
|
|
|
// Advance Off so that (isecAddr + Off) modulo 0x1000 is at least 0xff8.
|
2017-12-06 00:04:45 +08:00
|
|
|
uint64_t initialPageOff = (isecAddr + off) & 0xfff;
|
|
|
|
if (initialPageOff < 0xff8)
|
|
|
|
off += 0xff8 - initialPageOff;
|
|
|
|
|
|
|
|
bool optionalAllowed = limit - off > 12;
|
|
|
|
if (off >= limit || limit - off < 12) {
|
|
|
|
// Need at least 3 4-byte sized instructions to trigger erratum.
|
|
|
|
off = limit;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t patchOff = 0;
|
Avoid unnecessary buffer allocation and memcpy for compressed sections.
Previously, we uncompress all compressed sections before doing anything.
That works, and that is conceptually simple, but that could results in
a waste of CPU time and memory if uncompressed sections are then
discarded or just copied to the output buffer.
In particular, if .debug_gnu_pub{names,types} are compressed and if no
-gdb-index option is given, we wasted CPU and memory because we
uncompress them into newly allocated bufers and then memcpy the buffers
to the output buffer. That temporary buffer was redundant.
This patch changes how to uncompress sections. Now, compressed sections
are uncompressed lazily. To do that, `Data` member of `InputSectionBase`
is now hidden from outside, and `data()` accessor automatically expands
an compressed buffer if necessary.
If no one calls `data()`, then `writeTo()` directly uncompresses
compressed data into the output buffer. That eliminates the redundant
memory allocation and redundant memcpy.
This patch significantly reduces memory consumption (20 GiB max RSS to
15 Gib) for an executable whose .debug_gnu_pub{names,types} are in total
5 GiB in an uncompressed form.
Differential Revision: https://reviews.llvm.org/D52917
llvm-svn: 343979
2018-10-09 00:58:59 +08:00
|
|
|
const uint8_t *buf = isec->data().begin();
|
2018-01-24 03:26:52 +08:00
|
|
|
const ulittle32_t *instBuf = reinterpret_cast<const ulittle32_t *>(buf + off);
|
2017-12-06 00:04:45 +08:00
|
|
|
uint32_t instr1 = *instBuf++;
|
|
|
|
uint32_t instr2 = *instBuf++;
|
|
|
|
uint32_t instr3 = *instBuf++;
|
|
|
|
if (is843419ErratumSequence(instr1, instr2, instr3)) {
|
|
|
|
patchOff = off + 8;
|
|
|
|
} else if (optionalAllowed && !isBranch(instr3)) {
|
|
|
|
uint32_t instr4 = *instBuf++;
|
|
|
|
if (is843419ErratumSequence(instr1, instr2, instr4))
|
|
|
|
patchOff = off + 12;
|
|
|
|
}
|
|
|
|
if (((isecAddr + off) & 0xfff) == 0xff8)
|
|
|
|
off += 4;
|
|
|
|
else
|
|
|
|
off += 0xffc;
|
|
|
|
return patchOff;
|
|
|
|
}
|
|
|
|
|
2020-05-15 13:18:58 +08:00
|
|
|
class elf::Patch843419Section : public SyntheticSection {
|
2017-12-15 18:32:34 +08:00
|
|
|
public:
|
|
|
|
Patch843419Section(InputSection *p, uint64_t off);
|
|
|
|
|
|
|
|
void writeTo(uint8_t *buf) override;
|
|
|
|
|
|
|
|
size_t getSize() const override { return 8; }
|
|
|
|
|
|
|
|
uint64_t getLDSTAddr() const;
|
|
|
|
|
2019-12-09 19:07:54 +08:00
|
|
|
static bool classof(const SectionBase *d) {
|
|
|
|
return d->kind() == InputSectionBase::Synthetic && d->name == ".text.patch";
|
|
|
|
}
|
|
|
|
|
2017-12-15 18:32:34 +08:00
|
|
|
// The Section we are patching.
|
|
|
|
const InputSection *patchee;
|
2019-09-17 17:49:30 +08:00
|
|
|
// The offset of the instruction in the patchee section we are patching.
|
2017-12-15 18:32:34 +08:00
|
|
|
uint64_t patcheeOffset;
|
|
|
|
// A label for the start of the Patch that we can use as a relocation target.
|
|
|
|
Symbol *patchSym;
|
|
|
|
};
|
|
|
|
|
2019-09-09 19:22:27 +08:00
|
|
|
Patch843419Section::Patch843419Section(InputSection *p, uint64_t off)
|
2017-12-15 18:32:34 +08:00
|
|
|
: SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 4,
|
|
|
|
".text.patch"),
|
|
|
|
patchee(p), patcheeOffset(off) {
|
|
|
|
this->parent = p->getParent();
|
|
|
|
patchSym = addSyntheticLocal(
|
|
|
|
saver.save("__CortexA53843419_" + utohexstr(getLDSTAddr())), STT_FUNC, 0,
|
2017-12-20 07:59:35 +08:00
|
|
|
getSize(), *this);
|
|
|
|
addSyntheticLocal(saver.save("$x"), STT_NOTYPE, 0, 0, *this);
|
2017-12-15 18:32:34 +08:00
|
|
|
}
|
|
|
|
|
2019-09-09 19:22:27 +08:00
|
|
|
uint64_t Patch843419Section::getLDSTAddr() const {
|
2018-03-24 08:35:11 +08:00
|
|
|
return patchee->getVA(patcheeOffset);
|
2017-12-15 18:32:34 +08:00
|
|
|
}
|
|
|
|
|
2019-09-09 19:22:27 +08:00
|
|
|
void Patch843419Section::writeTo(uint8_t *buf) {
|
2017-12-15 18:32:34 +08:00
|
|
|
// Copy the instruction that we will be replacing with a branch in the
|
2019-09-17 17:49:30 +08:00
|
|
|
// patchee Section.
|
Avoid unnecessary buffer allocation and memcpy for compressed sections.
Previously, we uncompress all compressed sections before doing anything.
That works, and that is conceptually simple, but that could results in
a waste of CPU time and memory if uncompressed sections are then
discarded or just copied to the output buffer.
In particular, if .debug_gnu_pub{names,types} are compressed and if no
-gdb-index option is given, we wasted CPU and memory because we
uncompress them into newly allocated bufers and then memcpy the buffers
to the output buffer. That temporary buffer was redundant.
This patch changes how to uncompress sections. Now, compressed sections
are uncompressed lazily. To do that, `Data` member of `InputSectionBase`
is now hidden from outside, and `data()` accessor automatically expands
an compressed buffer if necessary.
If no one calls `data()`, then `writeTo()` directly uncompresses
compressed data into the output buffer. That eliminates the redundant
memory allocation and redundant memcpy.
This patch significantly reduces memory consumption (20 GiB max RSS to
15 Gib) for an executable whose .debug_gnu_pub{names,types} are in total
5 GiB in an uncompressed form.
Differential Revision: https://reviews.llvm.org/D52917
llvm-svn: 343979
2018-10-09 00:58:59 +08:00
|
|
|
write32le(buf, read32le(patchee->data().begin() + patcheeOffset));
|
2017-12-15 18:32:34 +08:00
|
|
|
|
2019-09-17 17:49:30 +08:00
|
|
|
// Apply any relocation transferred from the original patchee section.
|
2020-08-10 23:57:19 +08:00
|
|
|
relocateAlloc(buf, buf + getSize());
|
2017-12-15 18:32:34 +08:00
|
|
|
|
|
|
|
// Return address is the next instruction after the one we have just copied.
|
|
|
|
uint64_t s = getLDSTAddr() + 4;
|
|
|
|
uint64_t p = patchSym->getVA() + 4;
|
2020-01-23 13:39:16 +08:00
|
|
|
target->relocateNoSym(buf + 4, R_AARCH64_JUMP26, s - p);
|
2017-12-15 18:32:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void AArch64Err843419Patcher::init() {
|
|
|
|
// The AArch64 ABI permits data in executable sections. We must avoid scanning
|
|
|
|
// this data as if it were instructions to avoid false matches. We use the
|
|
|
|
// mapping symbols in the InputObjects to identify this data, caching the
|
2019-07-16 13:50:45 +08:00
|
|
|
// results in sectionMap so we don't have to recalculate it each pass.
|
2017-12-15 18:32:34 +08:00
|
|
|
|
|
|
|
// The ABI Section 4.5.4 Mapping symbols; defines local symbols that describe
|
|
|
|
// half open intervals [Symbol Value, Next Symbol Value) of code and data
|
|
|
|
// within sections. If there is no next symbol then the half open interval is
|
|
|
|
// [Symbol Value, End of section). The type, code or data, is determined by
|
|
|
|
// the mapping symbol name, $x for code, $d for data.
|
2017-12-06 00:04:45 +08:00
|
|
|
auto isCodeMapSymbol = [](const Symbol *b) {
|
|
|
|
return b->getName() == "$x" || b->getName().startswith("$x.");
|
|
|
|
};
|
|
|
|
auto isDataMapSymbol = [](const Symbol *b) {
|
|
|
|
return b->getName() == "$d" || b->getName().startswith("$d.");
|
|
|
|
};
|
|
|
|
|
|
|
|
// Collect mapping symbols for every executable InputSection.
|
|
|
|
for (InputFile *file : objectFiles) {
|
|
|
|
auto *f = cast<ObjFile<ELF64LE>>(file);
|
|
|
|
for (Symbol *b : f->getLocalSymbols()) {
|
|
|
|
auto *def = dyn_cast<Defined>(b);
|
|
|
|
if (!def)
|
|
|
|
continue;
|
|
|
|
if (!isCodeMapSymbol(def) && !isDataMapSymbol(def))
|
|
|
|
continue;
|
2018-09-13 23:49:13 +08:00
|
|
|
if (auto *sec = dyn_cast_or_null<InputSection>(def->section))
|
2017-12-06 00:04:45 +08:00
|
|
|
if (sec->flags & SHF_EXECINSTR)
|
|
|
|
sectionMap[sec].push_back(def);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// For each InputSection make sure the mapping symbols are in sorted in
|
|
|
|
// ascending order and free from consecutive runs of mapping symbols with
|
|
|
|
// the same type. For example we must remove the redundant $d.1 from $x.0
|
|
|
|
// $d.0 $d.1 $x.1.
|
|
|
|
for (auto &kv : sectionMap) {
|
|
|
|
std::vector<const Defined *> &mapSyms = kv.second;
|
2019-04-23 10:42:06 +08:00
|
|
|
llvm::stable_sort(mapSyms, [](const Defined *a, const Defined *b) {
|
|
|
|
return a->value < b->value;
|
|
|
|
});
|
2017-12-06 00:04:45 +08:00
|
|
|
mapSyms.erase(
|
|
|
|
std::unique(mapSyms.begin(), mapSyms.end(),
|
|
|
|
[=](const Defined *a, const Defined *b) {
|
2019-09-17 17:49:30 +08:00
|
|
|
return isCodeMapSymbol(a) == isCodeMapSymbol(b);
|
2017-12-06 00:04:45 +08:00
|
|
|
}),
|
|
|
|
mapSyms.end());
|
2019-09-17 17:49:30 +08:00
|
|
|
// Always start with a Code Mapping Symbol.
|
|
|
|
if (!mapSyms.empty() && !isCodeMapSymbol(mapSyms.front()))
|
|
|
|
mapSyms.erase(mapSyms.begin());
|
2017-12-06 00:04:45 +08:00
|
|
|
}
|
2017-12-15 18:32:34 +08:00
|
|
|
initialized = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Insert the PatchSections we have created back into the
|
|
|
|
// InputSectionDescription. As inserting patches alters the addresses of
|
|
|
|
// InputSections that follow them, we try and place the patches after all the
|
|
|
|
// executable sections, although we may need to insert them earlier if the
|
|
|
|
// InputSectionDescription is larger than the maximum branch range.
|
|
|
|
void AArch64Err843419Patcher::insertPatches(
|
|
|
|
InputSectionDescription &isd, std::vector<Patch843419Section *> &patches) {
|
|
|
|
uint64_t isecLimit;
|
|
|
|
uint64_t prevIsecLimit = isd.sections.front()->outSecOff;
|
2018-08-20 17:37:50 +08:00
|
|
|
uint64_t patchUpperBound = prevIsecLimit + target->getThunkSectionSpacing();
|
2018-12-18 04:15:12 +08:00
|
|
|
uint64_t outSecAddr = isd.sections.front()->getParent()->addr;
|
2017-12-15 18:32:34 +08:00
|
|
|
|
2019-07-16 13:50:45 +08:00
|
|
|
// Set the outSecOff of patches to the place where we want to insert them.
|
2017-12-15 18:32:34 +08:00
|
|
|
// We use a similar strategy to Thunk placement. Place patches roughly
|
|
|
|
// every multiple of maximum branch range.
|
|
|
|
auto patchIt = patches.begin();
|
|
|
|
auto patchEnd = patches.end();
|
|
|
|
for (const InputSection *isec : isd.sections) {
|
|
|
|
isecLimit = isec->outSecOff + isec->getSize();
|
|
|
|
if (isecLimit > patchUpperBound) {
|
|
|
|
while (patchIt != patchEnd) {
|
2018-12-18 04:15:12 +08:00
|
|
|
if ((*patchIt)->getLDSTAddr() - outSecAddr >= prevIsecLimit)
|
2017-12-15 18:32:34 +08:00
|
|
|
break;
|
|
|
|
(*patchIt)->outSecOff = prevIsecLimit;
|
|
|
|
++patchIt;
|
|
|
|
}
|
2018-08-20 17:37:50 +08:00
|
|
|
patchUpperBound = prevIsecLimit + target->getThunkSectionSpacing();
|
2017-12-06 00:04:45 +08:00
|
|
|
}
|
2017-12-15 18:32:34 +08:00
|
|
|
prevIsecLimit = isecLimit;
|
|
|
|
}
|
|
|
|
for (; patchIt != patchEnd; ++patchIt) {
|
|
|
|
(*patchIt)->outSecOff = isecLimit;
|
2017-12-06 00:04:45 +08:00
|
|
|
}
|
|
|
|
|
2019-09-09 19:22:27 +08:00
|
|
|
// Merge all patch sections. We use the outSecOff assigned above to
|
2017-12-15 18:32:34 +08:00
|
|
|
// determine the insertion point. This is ok as we only merge into an
|
|
|
|
// InputSectionDescription once per pass, and at the end of the pass
|
2019-07-16 13:50:45 +08:00
|
|
|
// assignAddresses() will recalculate all the outSecOff values.
|
2017-12-15 18:32:34 +08:00
|
|
|
std::vector<InputSection *> tmp;
|
|
|
|
tmp.reserve(isd.sections.size() + patches.size());
|
|
|
|
auto mergeCmp = [](const InputSection *a, const InputSection *b) {
|
2019-09-17 17:49:30 +08:00
|
|
|
if (a->outSecOff != b->outSecOff)
|
|
|
|
return a->outSecOff < b->outSecOff;
|
|
|
|
return isa<Patch843419Section>(a) && !isa<Patch843419Section>(b);
|
2017-12-15 18:32:34 +08:00
|
|
|
};
|
|
|
|
std::merge(isd.sections.begin(), isd.sections.end(), patches.begin(),
|
|
|
|
patches.end(), std::back_inserter(tmp), mergeCmp);
|
|
|
|
isd.sections = std::move(tmp);
|
|
|
|
}
|
|
|
|
|
2019-07-16 13:50:45 +08:00
|
|
|
// Given an erratum sequence that starts at address adrpAddr, with an
|
|
|
|
// instruction that we need to patch at patcheeOffset from the start of
|
2019-09-17 17:49:30 +08:00
|
|
|
// InputSection isec, create a Patch843419 Section and add it to the
|
2017-12-15 18:32:34 +08:00
|
|
|
// Patches that we need to insert.
|
|
|
|
static void implementPatch(uint64_t adrpAddr, uint64_t patcheeOffset,
|
|
|
|
InputSection *isec,
|
|
|
|
std::vector<Patch843419Section *> &patches) {
|
|
|
|
// There may be a relocation at the same offset that we are patching. There
|
2018-11-27 18:17:35 +08:00
|
|
|
// are four cases that we need to consider.
|
2017-12-15 18:32:34 +08:00
|
|
|
// Case 1: R_AARCH64_JUMP26 branch relocation. We have already patched this
|
|
|
|
// instance of the erratum on a previous patch and altered the relocation. We
|
|
|
|
// have nothing more to do.
|
2018-11-27 18:17:35 +08:00
|
|
|
// Case 2: A TLS Relaxation R_RELAX_TLS_IE_TO_LE. In this case the ADRP that
|
|
|
|
// we read will be transformed into a MOVZ later so we actually don't match
|
|
|
|
// the sequence and have nothing more to do.
|
|
|
|
// Case 3: A load/store register (unsigned immediate) class relocation. There
|
2017-12-15 18:32:34 +08:00
|
|
|
// are two of these R_AARCH_LD64_ABS_LO12_NC and R_AARCH_LD64_GOT_LO12_NC and
|
|
|
|
// they are both absolute. We need to add the same relocation to the patch,
|
|
|
|
// and replace the relocation with a R_AARCH_JUMP26 branch relocation.
|
2018-11-27 18:17:35 +08:00
|
|
|
// Case 4: No relocation. We must create a new R_AARCH64_JUMP26 branch
|
2017-12-15 18:32:34 +08:00
|
|
|
// relocation at the offset.
|
2019-03-30 00:21:16 +08:00
|
|
|
auto relIt = llvm::find_if(isec->relocations, [=](const Relocation &r) {
|
|
|
|
return r.offset == patcheeOffset;
|
|
|
|
});
|
2018-11-27 18:17:35 +08:00
|
|
|
if (relIt != isec->relocations.end() &&
|
|
|
|
(relIt->type == R_AARCH64_JUMP26 || relIt->expr == R_RELAX_TLS_IE_TO_LE))
|
2017-12-15 18:32:34 +08:00
|
|
|
return;
|
|
|
|
|
2018-02-09 08:15:12 +08:00
|
|
|
log("detected cortex-a53-843419 erratum sequence starting at " +
|
|
|
|
utohexstr(adrpAddr) + " in unpatched output.");
|
2017-12-15 18:32:34 +08:00
|
|
|
|
|
|
|
auto *ps = make<Patch843419Section>(isec, patcheeOffset);
|
|
|
|
patches.push_back(ps);
|
|
|
|
|
|
|
|
auto makeRelToPatch = [](uint64_t offset, Symbol *patchSym) {
|
|
|
|
return Relocation{R_PC, R_AARCH64_JUMP26, offset, 0, patchSym};
|
|
|
|
};
|
2017-12-06 00:04:45 +08:00
|
|
|
|
2017-12-15 18:32:34 +08:00
|
|
|
if (relIt != isec->relocations.end()) {
|
|
|
|
ps->relocations.push_back(
|
|
|
|
{relIt->expr, relIt->type, 0, relIt->addend, relIt->sym});
|
|
|
|
*relIt = makeRelToPatch(patcheeOffset, ps->patchSym);
|
|
|
|
} else
|
|
|
|
isec->relocations.push_back(makeRelToPatch(patcheeOffset, ps->patchSym));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Scan all the instructions in InputSectionDescription, for each instance of
|
|
|
|
// the erratum sequence create a Patch843419Section. We return the list of
|
2019-09-17 17:49:30 +08:00
|
|
|
// Patch843419Sections that need to be applied to the InputSectionDescription.
|
2017-12-15 18:32:34 +08:00
|
|
|
std::vector<Patch843419Section *>
|
|
|
|
AArch64Err843419Patcher::patchInputSectionDescription(
|
|
|
|
InputSectionDescription &isd) {
|
|
|
|
std::vector<Patch843419Section *> patches;
|
|
|
|
for (InputSection *isec : isd.sections) {
|
|
|
|
// LLD doesn't use the erratum sequence in SyntheticSections.
|
|
|
|
if (isa<SyntheticSection>(isec))
|
|
|
|
continue;
|
2019-07-16 13:50:45 +08:00
|
|
|
// Use sectionMap to make sure we only scan code and not inline data.
|
2017-12-15 18:32:34 +08:00
|
|
|
// We have already sorted MapSyms in ascending order and removed consecutive
|
|
|
|
// mapping symbols of the same type. Our range of executable instructions to
|
2019-07-16 13:50:45 +08:00
|
|
|
// scan is therefore [codeSym->value, dataSym->value) or [codeSym->value,
|
2017-12-15 18:32:34 +08:00
|
|
|
// section size).
|
|
|
|
std::vector<const Defined *> &mapSyms = sectionMap[isec];
|
|
|
|
|
2019-09-17 17:49:30 +08:00
|
|
|
auto codeSym = mapSyms.begin();
|
2017-12-15 18:32:34 +08:00
|
|
|
while (codeSym != mapSyms.end()) {
|
|
|
|
auto dataSym = std::next(codeSym);
|
|
|
|
uint64_t off = (*codeSym)->value;
|
|
|
|
uint64_t limit =
|
Avoid unnecessary buffer allocation and memcpy for compressed sections.
Previously, we uncompress all compressed sections before doing anything.
That works, and that is conceptually simple, but that could results in
a waste of CPU time and memory if uncompressed sections are then
discarded or just copied to the output buffer.
In particular, if .debug_gnu_pub{names,types} are compressed and if no
-gdb-index option is given, we wasted CPU and memory because we
uncompress them into newly allocated bufers and then memcpy the buffers
to the output buffer. That temporary buffer was redundant.
This patch changes how to uncompress sections. Now, compressed sections
are uncompressed lazily. To do that, `Data` member of `InputSectionBase`
is now hidden from outside, and `data()` accessor automatically expands
an compressed buffer if necessary.
If no one calls `data()`, then `writeTo()` directly uncompresses
compressed data into the output buffer. That eliminates the redundant
memory allocation and redundant memcpy.
This patch significantly reduces memory consumption (20 GiB max RSS to
15 Gib) for an executable whose .debug_gnu_pub{names,types} are in total
5 GiB in an uncompressed form.
Differential Revision: https://reviews.llvm.org/D52917
llvm-svn: 343979
2018-10-09 00:58:59 +08:00
|
|
|
(dataSym == mapSyms.end()) ? isec->data().size() : (*dataSym)->value;
|
2017-12-15 18:32:34 +08:00
|
|
|
|
|
|
|
while (off < limit) {
|
2018-03-24 08:35:11 +08:00
|
|
|
uint64_t startAddr = isec->getVA(off);
|
2019-09-17 17:49:30 +08:00
|
|
|
if (uint64_t patcheeOffset =
|
|
|
|
scanCortexA53Errata843419(isec, off, limit))
|
2017-12-15 18:32:34 +08:00
|
|
|
implementPatch(startAddr, patcheeOffset, isec, patches);
|
|
|
|
}
|
|
|
|
if (dataSym == mapSyms.end())
|
|
|
|
break;
|
|
|
|
codeSym = std::next(dataSym);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return patches;
|
|
|
|
}
|
|
|
|
|
|
|
|
// For each InputSectionDescription make one pass over the executable sections
|
|
|
|
// looking for the erratum sequence; creating a synthetic Patch843419Section
|
|
|
|
// for each instance found. We insert these synthetic patch sections after the
|
|
|
|
// executable code in each InputSectionDescription.
|
|
|
|
//
|
|
|
|
// PreConditions:
|
|
|
|
// The Output and Input Sections have had their final addresses assigned.
|
|
|
|
//
|
|
|
|
// PostConditions:
|
|
|
|
// Returns true if at least one patch was added. The addresses of the
|
2019-10-29 09:41:38 +08:00
|
|
|
// Output and Input Sections may have been changed.
|
2017-12-15 18:32:34 +08:00
|
|
|
// Returns false if no patches were required and no changes were made.
|
|
|
|
bool AArch64Err843419Patcher::createFixes() {
|
2019-09-09 19:22:27 +08:00
|
|
|
if (!initialized)
|
2017-12-15 18:32:34 +08:00
|
|
|
init();
|
|
|
|
|
|
|
|
bool addressesChanged = false;
|
2017-12-06 00:04:45 +08:00
|
|
|
for (OutputSection *os : outputSections) {
|
|
|
|
if (!(os->flags & SHF_ALLOC) || !(os->flags & SHF_EXECINSTR))
|
|
|
|
continue;
|
2021-11-26 08:47:07 +08:00
|
|
|
for (BaseCommand *bc : os->commands)
|
2017-12-06 00:04:45 +08:00
|
|
|
if (auto *isd = dyn_cast<InputSectionDescription>(bc)) {
|
2017-12-15 18:32:34 +08:00
|
|
|
std::vector<Patch843419Section *> patches =
|
|
|
|
patchInputSectionDescription(*isd);
|
|
|
|
if (!patches.empty()) {
|
|
|
|
insertPatches(*isd, patches);
|
|
|
|
addressesChanged = true;
|
2017-12-06 00:04:45 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2017-12-15 18:32:34 +08:00
|
|
|
return addressesChanged;
|
2017-12-06 00:04:45 +08:00
|
|
|
}
|