2007-06-06 15:42:06 +08:00
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//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 15:42:06 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-lower"
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#include "MipsISelLowering.h"
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2007-08-28 13:08:16 +08:00
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#include "MipsMachineFunction.h"
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2007-06-06 15:42:06 +08:00
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#include "MipsTargetMachine.h"
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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#include "MipsSubtarget.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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2008-07-22 02:52:34 +08:00
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#include "llvm/GlobalVariable.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 12:13:23 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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const char *MipsTargetLowering::
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getTargetNodeName(unsigned Opcode) const
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{
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switch (Opcode)
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{
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2008-07-30 03:05:28 +08:00
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case MipsISD::JmpLink : return "MipsISD::JmpLink";
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case MipsISD::Hi : return "MipsISD::Hi";
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::GPRel : return "MipsISD::GPRel";
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case MipsISD::Ret : return "MipsISD::Ret";
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2008-08-13 15:13:40 +08:00
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case MipsISD::CMov : return "MipsISD::CMov";
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2008-07-30 03:05:28 +08:00
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case MipsISD::SelectCC : return "MipsISD::SelectCC";
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case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
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case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
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case MipsISD::FPCmp : return "MipsISD::FPCmp";
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default : return NULL;
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2007-06-06 15:42:06 +08:00
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}
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}
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MipsTargetLowering::
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MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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{
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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2007-06-06 15:42:06 +08:00
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// Mips does not have i1 type, so use i32 for
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// setcc operations results (slt, sgt, ...).
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2008-11-23 23:47:28 +08:00
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setBooleanContents(ZeroOrOneBooleanContent);
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2007-06-06 15:42:06 +08:00
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2007-11-13 03:49:57 +08:00
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// JumpTable targets must use GOT when using PIC_
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setUsesGlobalOffsetTable(true);
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2007-06-06 15:42:06 +08:00
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// Set up the register classes
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addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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// When dealing with single precision only, use libcalls
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if (!Subtarget->isSingleFloat()) {
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addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
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if (!Subtarget->isFP64bit())
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addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
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} else
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addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
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2008-07-31 03:00:31 +08:00
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// Legal fp constants
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addLegalFPImmediate(APFloat(+0.0f));
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2007-06-06 15:42:06 +08:00
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// Load extented operations for i1 types must be promoted
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2008-10-15 05:26:46 +08:00
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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2007-06-06 15:42:06 +08:00
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2008-08-01 02:31:28 +08:00
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// Used by legalize types to correctly generate the setcc result.
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2008-08-03 03:37:33 +08:00
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// Without this, every float setcc comes with a AND/OR with the result,
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2008-08-01 02:31:28 +08:00
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// we don't want this, since the fpcmp result goes to a flag register,
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// which is used implicitly by brcond and select operations.
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AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
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2008-07-09 12:15:08 +08:00
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// Mips Custom Operations
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2008-08-08 03:08:11 +08:00
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::SELECT, MVT::f32, Custom);
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setOperationAction(ISD::SELECT, MVT::i32, Custom);
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setOperationAction(ISD::SETCC, MVT::f32, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
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2008-07-09 12:15:08 +08:00
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2008-08-03 03:37:33 +08:00
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// We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
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// with operands comming from setcc fp comparions. This is necessary since
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// the result from these setcc are in a flag registers (FCR31).
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2008-08-01 02:31:28 +08:00
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setOperationAction(ISD::AND, MVT::i32, Custom);
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2008-08-03 03:37:33 +08:00
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setOperationAction(ISD::OR, MVT::i32, Custom);
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2008-08-01 02:31:28 +08:00
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2008-07-09 12:15:08 +08:00
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// Operations not directly supported by Mips.
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2008-07-08 03:11:24 +08:00
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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2008-07-09 12:15:08 +08:00
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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2008-08-01 02:50:54 +08:00
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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2008-07-09 12:15:08 +08:00
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// We don't have line number support yet.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
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// Use the default for now
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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2008-07-08 03:11:24 +08:00
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2008-08-04 14:44:31 +08:00
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if (Subtarget->isSingleFloat())
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2008-07-08 03:11:24 +08:00
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setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
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2007-06-06 15:42:06 +08:00
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2008-07-09 13:32:22 +08:00
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if (!Subtarget->hasSEInReg()) {
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2008-07-09 12:15:08 +08:00
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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}
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2008-08-08 14:16:31 +08:00
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if (!Subtarget->hasBitCount())
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setOperationAction(ISD::CTLZ, MVT::i32, Expand);
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2008-08-13 15:13:40 +08:00
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if (!Subtarget->hasSwap())
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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2007-06-06 15:42:06 +08:00
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setStackPointerRegisterToSaveRestore(Mips::SP);
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computeRegisterProperties();
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}
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2009-01-01 23:52:00 +08:00
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MVT MipsTargetLowering::getSetCCResultType(MVT VT) const {
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2008-03-10 23:42:14 +08:00
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return MVT::i32;
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}
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2008-07-28 05:46:04 +08:00
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SDValue MipsTargetLowering::
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LowerOperation(SDValue Op, SelectionDAG &DAG)
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2007-06-06 15:42:06 +08:00
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{
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switch (Op.getOpcode())
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{
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2008-08-08 03:08:11 +08:00
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case ISD::AND: return LowerANDOR(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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case ISD::CALL: return LowerCALL(Op, DAG);
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case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::OR: return LowerANDOR(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::SELECT: return LowerSELECT(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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2007-06-06 15:42:06 +08:00
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}
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2008-07-28 05:46:04 +08:00
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return SDValue();
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2007-06-06 15:42:06 +08:00
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}
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//===----------------------------------------------------------------------===//
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// Lower helper functions
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//===----------------------------------------------------------------------===//
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// AddLiveIn - This helper function adds the specified physical register to the
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// MachineFunction as a live in value. It also creates a corresponding
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// virtual register for it.
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static unsigned
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AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
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{
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assert(RC->contains(PReg) && "Not the correct regclass!");
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2007-12-31 12:13:23 +08:00
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unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
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MF.getRegInfo().addLiveIn(PReg, VReg);
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2007-06-06 15:42:06 +08:00
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return VReg;
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}
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2008-07-24 00:01:50 +08:00
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// A address must be loaded from a small section if its size is less than the
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// small section size threshold. Data in this section must be addressed using
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// gp_rel operator.
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bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
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return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
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}
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2008-07-22 02:52:34 +08:00
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// Discover if this global address can be placed into small data/bss section.
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bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
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{
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const TargetData *TD = getTargetData();
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2008-07-22 23:34:27 +08:00
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const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
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if (!GVA)
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return false;
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2008-07-22 02:52:34 +08:00
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const Type *Ty = GV->getType()->getElementType();
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2009-01-13 04:38:59 +08:00
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unsigned Size = TD->getTypePaddedSize(Ty);
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2008-07-22 02:52:34 +08:00
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// if this is a internal constant string, there is a special
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// section for it, but not in small data/bss.
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2009-01-16 04:18:42 +08:00
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if (GVA->hasInitializer() && GV->hasLocalLinkage()) {
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2008-07-22 02:52:34 +08:00
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|
Constant *C = GVA->getInitializer();
|
|
|
|
const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
|
|
|
|
if (CVA && CVA->isCString())
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2008-07-24 00:01:50 +08:00
|
|
|
return IsInSmallSection(Size);
|
2008-07-22 02:52:34 +08:00
|
|
|
}
|
|
|
|
|
2008-07-29 03:11:24 +08:00
|
|
|
// Get fp branch code (not opcode) from condition code.
|
|
|
|
static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
|
|
|
|
if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
|
|
|
|
return Mips::BRANCH_T;
|
|
|
|
|
|
|
|
if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
|
|
|
|
return Mips::BRANCH_F;
|
|
|
|
|
|
|
|
return Mips::BRANCH_INVALID;
|
|
|
|
}
|
|
|
|
|
2008-07-30 03:05:28 +08:00
|
|
|
static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
|
|
|
|
switch(BC) {
|
|
|
|
default:
|
|
|
|
assert(0 && "Unknown branch code");
|
|
|
|
case Mips::BRANCH_T : return Mips::BC1T;
|
|
|
|
case Mips::BRANCH_F : return Mips::BC1F;
|
|
|
|
case Mips::BRANCH_TL : return Mips::BC1TL;
|
|
|
|
case Mips::BRANCH_FL : return Mips::BC1FL;
|
|
|
|
}
|
|
|
|
}
|
2008-07-29 03:11:24 +08:00
|
|
|
|
|
|
|
static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
|
|
|
|
switch (CC) {
|
|
|
|
default: assert(0 && "Unknown fp condition code!");
|
|
|
|
case ISD::SETEQ:
|
|
|
|
case ISD::SETOEQ: return Mips::FCOND_EQ;
|
|
|
|
case ISD::SETUNE: return Mips::FCOND_OGL;
|
|
|
|
case ISD::SETLT:
|
|
|
|
case ISD::SETOLT: return Mips::FCOND_OLT;
|
|
|
|
case ISD::SETGT:
|
|
|
|
case ISD::SETOGT: return Mips::FCOND_OGT;
|
|
|
|
case ISD::SETLE:
|
|
|
|
case ISD::SETOLE: return Mips::FCOND_OLE;
|
|
|
|
case ISD::SETGE:
|
|
|
|
case ISD::SETOGE: return Mips::FCOND_OGE;
|
|
|
|
case ISD::SETULT: return Mips::FCOND_ULT;
|
|
|
|
case ISD::SETULE: return Mips::FCOND_ULE;
|
|
|
|
case ISD::SETUGT: return Mips::FCOND_UGT;
|
|
|
|
case ISD::SETUGE: return Mips::FCOND_UGE;
|
|
|
|
case ISD::SETUO: return Mips::FCOND_UN;
|
|
|
|
case ISD::SETO: return Mips::FCOND_OR;
|
|
|
|
case ISD::SETNE:
|
|
|
|
case ISD::SETONE: return Mips::FCOND_NEQ;
|
|
|
|
case ISD::SETUEQ: return Mips::FCOND_UEQ;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-30 03:05:28 +08:00
|
|
|
MachineBasicBlock *
|
|
|
|
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *BB)
|
|
|
|
{
|
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
|
|
bool isFPCmp = false;
|
|
|
|
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default: assert(false && "Unexpected instr type to insert");
|
|
|
|
case Mips::Select_FCC:
|
|
|
|
case Mips::Select_FCC_SO32:
|
|
|
|
case Mips::Select_FCC_AS32:
|
|
|
|
case Mips::Select_FCC_D32:
|
|
|
|
isFPCmp = true; // FALL THROUGH
|
|
|
|
case Mips::Select_CC:
|
|
|
|
case Mips::Select_CC_SO32:
|
|
|
|
case Mips::Select_CC_AS32:
|
|
|
|
case Mips::Select_CC_D32: {
|
|
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the
|
|
|
|
// diamond control-flow pattern. The incoming instruction knows the
|
|
|
|
// destination vreg to set, the condition code register to branch on, the
|
|
|
|
// true/false values to select between, and a branch opcode to use.
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// TrueVal = ...
|
|
|
|
// setcc r1, r2, r3
|
|
|
|
// bNE r1, r0, copy1MBB
|
|
|
|
// fallthrough --> copy0MBB
|
|
|
|
MachineBasicBlock *thisMBB = BB;
|
|
|
|
MachineFunction *F = BB->getParent();
|
|
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
|
|
|
|
// Emit the right instruction according to the type of the operands compared
|
|
|
|
if (isFPCmp) {
|
|
|
|
// Find the condiction code present in the setcc operation.
|
|
|
|
Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
|
|
|
|
// Get the branch opcode from the branch code.
|
|
|
|
unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
|
|
|
|
BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
|
|
|
|
} else
|
|
|
|
BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
|
|
|
|
.addReg(Mips::ZERO).addMBB(sinkMBB);
|
|
|
|
|
|
|
|
F->insert(It, copy0MBB);
|
|
|
|
F->insert(It, sinkMBB);
|
|
|
|
// Update machine-CFG edges by first adding all successors of the current
|
|
|
|
// block to the new block which will contain the Phi node for the select.
|
|
|
|
for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
|
|
|
|
e = BB->succ_end(); i != e; ++i)
|
|
|
|
sinkMBB->addSuccessor(*i);
|
|
|
|
// Next, remove all successors of the current block, and add the true
|
|
|
|
// and fallthrough blocks as its successors.
|
|
|
|
while(!BB->succ_empty())
|
|
|
|
BB->removeSuccessor(BB->succ_begin());
|
|
|
|
BB->addSuccessor(copy0MBB);
|
|
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
|
|
|
|
// copy0MBB:
|
|
|
|
// %FalseValue = ...
|
|
|
|
// # fallthrough to sinkMBB
|
|
|
|
BB = copy0MBB;
|
|
|
|
|
|
|
|
// Update machine-CFG edges
|
|
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
|
|
|
|
// sinkMBB:
|
|
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
|
|
// ...
|
|
|
|
BB = sinkMBB;
|
|
|
|
BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
|
|
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
|
|
|
.addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
|
|
|
|
|
|
|
|
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
|
|
|
return BB;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Misc Lower Operation implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
2008-07-30 03:29:50 +08:00
|
|
|
|
2008-08-08 03:08:11 +08:00
|
|
|
SDValue MipsTargetLowering::
|
|
|
|
LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
SDValue Size = Op.getOperand(1);
|
|
|
|
|
|
|
|
// Get a reference from Mips stack pointer
|
|
|
|
SDValue StackPointer = DAG.getCopyFromReg(Chain, Mips::SP, MVT::i32);
|
|
|
|
|
|
|
|
// Subtract the dynamic size from the actual stack size to
|
|
|
|
// obtain the new stack size.
|
|
|
|
SDValue Sub = DAG.getNode(ISD::SUB, MVT::i32, StackPointer, Size);
|
|
|
|
|
|
|
|
// The Sub result contains the new stack start address, so it
|
|
|
|
// must be placed in the stack pointer register.
|
|
|
|
Chain = DAG.getCopyToReg(StackPointer.getValue(1), Mips::SP, Sub);
|
|
|
|
|
|
|
|
// This node always has two return values: a new stack pointer
|
|
|
|
// value and a chain
|
|
|
|
SDValue Ops[2] = { Sub, Chain };
|
|
|
|
return DAG.getMergeValues(Ops, 2);
|
|
|
|
}
|
|
|
|
|
2008-08-01 02:31:28 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2008-08-03 03:37:33 +08:00
|
|
|
LowerANDOR(SDValue Op, SelectionDAG &DAG)
|
2008-08-01 02:31:28 +08:00
|
|
|
{
|
|
|
|
SDValue LHS = Op.getOperand(0);
|
|
|
|
SDValue RHS = Op.getOperand(1);
|
|
|
|
|
|
|
|
if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
SDValue True = DAG.getConstant(1, MVT::i32);
|
|
|
|
SDValue False = DAG.getConstant(0, MVT::i32);
|
|
|
|
|
|
|
|
SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
|
|
|
|
LHS, True, False, LHS.getOperand(2));
|
|
|
|
SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
|
|
|
|
RHS, True, False, RHS.getOperand(2));
|
|
|
|
|
2008-08-03 03:37:33 +08:00
|
|
|
return DAG.getNode(Op.getOpcode(), MVT::i32, LSEL, RSEL);
|
2008-08-01 02:31:28 +08:00
|
|
|
}
|
|
|
|
|
2008-07-29 03:11:24 +08:00
|
|
|
SDValue MipsTargetLowering::
|
|
|
|
LowerBRCOND(SDValue Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
// The first operand is the chain, the second is the condition, the third is
|
|
|
|
// the block to branch to if the condition is true.
|
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
SDValue Dest = Op.getOperand(2);
|
2008-08-01 02:31:28 +08:00
|
|
|
|
|
|
|
if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
|
2008-07-31 01:06:13 +08:00
|
|
|
return Op;
|
2008-07-29 03:11:24 +08:00
|
|
|
|
2008-08-01 02:31:28 +08:00
|
|
|
SDValue CondRes = Op.getOperand(1);
|
|
|
|
SDValue CCNode = CondRes.getOperand(2);
|
2008-09-13 00:56:44 +08:00
|
|
|
Mips::CondCode CC =
|
|
|
|
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
|
2008-07-29 03:11:24 +08:00
|
|
|
SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
|
|
|
|
|
|
|
|
return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
|
|
|
|
Dest, CondRes);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue MipsTargetLowering::
|
|
|
|
LowerSETCC(SDValue Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
// The operands to this are the left and right operands to compare (ops #0,
|
|
|
|
// and #1) and the condition code to compare them with (op #2) as a
|
|
|
|
// CondCodeSDNode.
|
|
|
|
SDValue LHS = Op.getOperand(0);
|
|
|
|
SDValue RHS = Op.getOperand(1);
|
|
|
|
|
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
|
|
|
|
|
|
|
|
return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
|
|
|
|
DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
|
|
|
|
}
|
|
|
|
|
2008-07-30 03:05:28 +08:00
|
|
|
SDValue MipsTargetLowering::
|
|
|
|
LowerSELECT(SDValue Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
SDValue Cond = Op.getOperand(0);
|
|
|
|
SDValue True = Op.getOperand(1);
|
|
|
|
SDValue False = Op.getOperand(2);
|
|
|
|
|
2008-08-13 15:13:40 +08:00
|
|
|
// if the incomming condition comes from a integer compare, the select
|
|
|
|
// operation must be SelectCC or a conditional move if the subtarget
|
|
|
|
// supports it.
|
|
|
|
if (Cond.getOpcode() != MipsISD::FPCmp) {
|
|
|
|
if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
|
|
|
|
return Op;
|
2008-08-01 02:31:28 +08:00
|
|
|
return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
|
|
|
|
Cond, True, False);
|
2008-08-13 15:13:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// if the incomming condition comes from fpcmp, the select
|
|
|
|
// operation must use FPSelectCC.
|
2008-08-01 02:31:28 +08:00
|
|
|
SDValue CCNode = Cond.getOperand(2);
|
2008-07-30 03:05:28 +08:00
|
|
|
return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
|
2008-08-01 02:31:28 +08:00
|
|
|
Cond, True, False, CCNode);
|
2008-07-30 03:05:28 +08:00
|
|
|
}
|
|
|
|
|
2008-07-30 03:29:50 +08:00
|
|
|
SDValue MipsTargetLowering::
|
|
|
|
LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
|
|
SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
|
|
|
|
|
|
|
|
if (!Subtarget->hasABICall()) {
|
|
|
|
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
|
|
|
|
SDValue Ops[] = { GA };
|
2008-07-31 01:06:13 +08:00
|
|
|
// %gp_rel relocation
|
|
|
|
if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
|
2008-07-30 03:29:50 +08:00
|
|
|
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
|
|
|
|
SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
|
|
|
|
return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
|
|
|
|
}
|
|
|
|
// %hi/%lo relocation
|
|
|
|
SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
|
|
|
|
return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
|
|
|
|
|
|
|
|
} else { // Abicall relocations, TODO: make this cleaner.
|
|
|
|
SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
|
|
|
|
// On functions and global targets not internal linked only
|
|
|
|
// a load from got/GP is necessary for PIC to work.
|
2009-01-16 04:18:42 +08:00
|
|
|
if (!GV->hasLocalLinkage() || isa<Function>(GV))
|
2008-07-30 03:29:50 +08:00
|
|
|
return ResNode;
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
|
|
|
|
return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(0 && "Dont know how to handle GlobalAddress");
|
|
|
|
return SDValue(0,0);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue MipsTargetLowering::
|
|
|
|
LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
|
|
|
|
{
|
|
|
|
assert(0 && "TLS not implemented for MIPS.");
|
|
|
|
return SDValue(); // Not reached
|
|
|
|
}
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue MipsTargetLowering::
|
|
|
|
LowerJumpTable(SDValue Op, SelectionDAG &DAG)
|
2007-11-13 03:49:57 +08:00
|
|
|
{
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue ResNode;
|
|
|
|
SDValue HiPart;
|
2007-11-13 03:49:57 +08:00
|
|
|
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT PtrVT = Op.getValueType();
|
2007-11-13 03:49:57 +08:00
|
|
|
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
|
2007-11-13 03:49:57 +08:00
|
|
|
|
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
|
2008-06-06 20:08:01 +08:00
|
|
|
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Ops[] = { JTI };
|
2007-11-13 03:49:57 +08:00
|
|
|
HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
|
|
|
|
} else // Emit Load from Global Pointer
|
|
|
|
HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
|
2007-11-13 03:49:57 +08:00
|
|
|
ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
|
|
|
|
|
|
|
|
return ResNode;
|
|
|
|
}
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue MipsTargetLowering::
|
|
|
|
LowerConstantPool(SDValue Op, SelectionDAG &DAG)
|
2008-07-09 12:15:08 +08:00
|
|
|
{
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue ResNode;
|
2008-07-24 00:01:50 +08:00
|
|
|
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
|
|
|
|
Constant *C = N->getConstVal();
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
|
2008-07-24 00:01:50 +08:00
|
|
|
|
|
|
|
// gp_rel relocation
|
2008-07-29 03:26:25 +08:00
|
|
|
// FIXME: we should reference the constant pool using small data sections,
|
|
|
|
// but the asm printer currently doens't support this feature without
|
|
|
|
// hacking it. This feature should come soon so we can uncomment the
|
|
|
|
// stuff below.
|
|
|
|
//if (!Subtarget->hasABICall() &&
|
2009-01-13 04:38:59 +08:00
|
|
|
// IsInSmallSection(getTargetData()->getTypePaddedSize(C->getType()))) {
|
2008-07-29 03:26:25 +08:00
|
|
|
// SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
|
|
|
|
// SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
|
|
|
|
// ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
|
|
|
|
//} else { // %hi/%lo relocation
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
|
2008-07-24 00:01:50 +08:00
|
|
|
ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
|
2008-07-29 03:26:25 +08:00
|
|
|
//}
|
2008-07-24 00:01:50 +08:00
|
|
|
|
|
|
|
return ResNode;
|
2008-07-09 12:15:08 +08:00
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Calling Convention Implementation
|
|
|
|
//
|
|
|
|
// The lower operations present on calling convention works on this order:
|
|
|
|
// LowerCALL (virt regs --> phys regs, virt regs --> stack)
|
|
|
|
// LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
|
|
|
|
// LowerRET (virt regs --> phys regs)
|
|
|
|
// LowerCALL (phys regs --> virt regs)
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#include "MipsGenCallingConv.inc"
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// CALL Calling Convention Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2009-01-26 11:15:54 +08:00
|
|
|
/// LowerCALL - functions arguments are copied from virtual regs to
|
|
|
|
/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
/// TODO: isVarArg, isTailCall.
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2008-08-04 15:12:52 +08:00
|
|
|
LowerCALL(SDValue Op, SelectionDAG &DAG)
|
2007-06-06 15:42:06 +08:00
|
|
|
{
|
2007-07-12 07:16:16 +08:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
|
2008-09-13 09:54:27 +08:00
|
|
|
CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
|
|
|
|
SDValue Chain = TheCall->getChain();
|
|
|
|
SDValue Callee = TheCall->getCallee();
|
|
|
|
bool isVarArg = TheCall->isVarArg();
|
|
|
|
unsigned CC = TheCall->getCallingConv();
|
2007-07-12 07:16:16 +08:00
|
|
|
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
2007-07-12 07:16:16 +08:00
|
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
|
|
|
|
|
2008-07-15 10:03:36 +08:00
|
|
|
// To meet O32 ABI, Mips must always allocate 16 bytes on
|
2007-07-12 07:16:16 +08:00
|
|
|
// the stack (even if less than 4 are used as arguments)
|
2008-07-15 10:03:36 +08:00
|
|
|
if (Subtarget->isABI_O32()) {
|
|
|
|
int VTsize = MVT(MVT::i32).getSizeInBits()/8;
|
|
|
|
MFI->CreateFixedObject(VTsize, (VTsize*3));
|
|
|
|
}
|
2007-07-12 07:16:16 +08:00
|
|
|
|
2008-09-13 09:54:27 +08:00
|
|
|
CCInfo.AnalyzeCallOperands(TheCall, CC_Mips);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
|
|
|
unsigned NumBytes = CCInfo.getNextStackOffset();
|
2008-10-12 06:08:30 +08:00
|
|
|
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
|
2007-06-06 15:42:06 +08:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// With EABI is it possible to have 16 args on registers.
|
2008-07-28 05:46:04 +08:00
|
|
|
SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
|
|
|
|
SmallVector<SDValue, 8> MemOpChains;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// First/LastArgStackLoc contains the first/last
|
|
|
|
// "at stack" argument location.
|
|
|
|
int LastArgStackLoc = 0;
|
|
|
|
unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Walk the register/memloc assignments, inserting copies/loads.
|
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
|
|
CCValAssign &VA = ArgLocs[i];
|
|
|
|
|
|
|
|
// Arguments start after the 5 first operands of ISD::CALL
|
2008-09-13 09:54:27 +08:00
|
|
|
SDValue Arg = TheCall->getArg(i);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Promote the value if needed.
|
|
|
|
switch (VA.getLocInfo()) {
|
2008-03-17 14:57:02 +08:00
|
|
|
default: assert(0 && "Unknown loc info!");
|
|
|
|
case CCValAssign::Full: break;
|
|
|
|
case CCValAssign::SExt:
|
|
|
|
Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
|
|
|
|
break;
|
|
|
|
case CCValAssign::ZExt:
|
|
|
|
Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
|
|
|
|
break;
|
|
|
|
case CCValAssign::AExt:
|
|
|
|
Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
|
|
|
|
break;
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
2007-11-05 11:02:32 +08:00
|
|
|
// Arguments that can be passed on register must be kept at
|
|
|
|
// RegsToPass vector
|
2007-06-06 15:42:06 +08:00
|
|
|
if (VA.isRegLoc()) {
|
|
|
|
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
2008-03-17 14:57:02 +08:00
|
|
|
continue;
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
2008-03-17 14:57:02 +08:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// Register cant get to this point...
|
2008-03-17 14:57:02 +08:00
|
|
|
assert(VA.isMemLoc());
|
|
|
|
|
|
|
|
// Create the frame index object for this incoming parameter
|
|
|
|
// This guarantees that when allocating Local Area the firsts
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// 16 bytes which are alwayes reserved won't be overwritten
|
|
|
|
// if O32 ABI is used. For EABI the first address is zero.
|
|
|
|
LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
|
2008-06-06 20:08:01 +08:00
|
|
|
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
LastArgStackLoc);
|
2008-03-17 14:57:02 +08:00
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
|
2008-03-17 14:57:02 +08:00
|
|
|
|
|
|
|
// emit ISD::STORE whichs stores the
|
|
|
|
// parameter value to a stack Location
|
|
|
|
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// Transform all store nodes into one single node because all store
|
|
|
|
// nodes are independent of each other.
|
2007-06-06 15:42:06 +08:00
|
|
|
if (!MemOpChains.empty())
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
|
|
|
&MemOpChains[0], MemOpChains.size());
|
|
|
|
|
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token
|
|
|
|
// chain and flag operands which copy the outgoing args into registers.
|
|
|
|
// The InFlag in necessary since all emited instructions must be
|
|
|
|
// stuck together.
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue InFlag;
|
2007-06-06 15:42:06 +08:00
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
|
|
|
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
|
|
|
|
RegsToPass[i].second, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2008-09-17 05:48:12 +08:00
|
|
|
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
|
|
|
|
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
|
|
|
|
// node so that legalize doesn't hack it.
|
2007-11-05 11:02:32 +08:00
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
2007-06-06 15:42:06 +08:00
|
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
|
2008-09-17 05:48:12 +08:00
|
|
|
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
|
|
|
|
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
|
|
|
|
|
2007-11-05 11:02:32 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// MipsJmpLink = #chain, #target_address, #opt_in_flags...
|
|
|
|
// = Chain, Callee, Reg#1, Reg#2, ...
|
|
|
|
//
|
|
|
|
// Returns a chain & a flag for retval copy to use.
|
|
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
2008-07-28 05:46:04 +08:00
|
|
|
SmallVector<SDValue, 8> Ops;
|
2007-06-06 15:42:06 +08:00
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(Callee);
|
|
|
|
|
|
|
|
// Add argument registers to the end of the list so that they are
|
|
|
|
// known live into the call.
|
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
|
|
|
|
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
|
|
|
|
RegsToPass[i].second.getValueType()));
|
|
|
|
|
2008-08-29 05:40:38 +08:00
|
|
|
if (InFlag.getNode())
|
2007-06-06 15:42:06 +08:00
|
|
|
Ops.push_back(InFlag);
|
|
|
|
|
|
|
|
Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2008-06-04 09:45:25 +08:00
|
|
|
// Create the CALLSEQ_END node.
|
2008-10-12 06:08:30 +08:00
|
|
|
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
|
|
|
|
DAG.getIntPtrConstant(0, true), InFlag);
|
2008-06-01 11:49:39 +08:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2007-11-05 11:02:32 +08:00
|
|
|
// Create a stack location to hold GP when PIC is used. This stack
|
|
|
|
// location is used on function prologue to save GP and also after all
|
|
|
|
// emited CALL's to restore GP.
|
|
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
|
|
|
|
// Function can have an arbitrary number of calls, so
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// hold the LastArgStackLoc with the biggest offset.
|
2007-11-05 11:02:32 +08:00
|
|
|
int FI;
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
|
|
|
|
LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
|
2007-11-05 11:02:32 +08:00
|
|
|
// Create the frame index only once. SPOffset here can be anything
|
|
|
|
// (this will be fixed on processFunctionBeforeFrameFinalized)
|
|
|
|
if (MipsFI->getGPStackOffset() == -1) {
|
|
|
|
FI = MFI->CreateFixedObject(4, 0);
|
|
|
|
MipsFI->setGPFI(FI);
|
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
MipsFI->setGPStackOffset(LastArgStackLoc);
|
2007-11-05 11:02:32 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Reload GP value.
|
|
|
|
FI = MipsFI->getGPFI();
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
|
|
|
|
SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
|
2007-11-05 11:02:32 +08:00
|
|
|
Chain = GPLoad.getValue(1);
|
|
|
|
Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
|
2008-07-28 05:46:04 +08:00
|
|
|
GPLoad, SDValue(0,0));
|
2008-06-01 11:49:39 +08:00
|
|
|
InFlag = Chain.getValue(1);
|
2007-11-05 11:02:32 +08:00
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// Handle result values, copying them out of physregs into vregs that we
|
|
|
|
// return.
|
2008-09-13 09:54:27 +08:00
|
|
|
return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), Op.getResNo());
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// LowerCallResult - Lower the result values of an ISD::CALL into the
|
|
|
|
/// appropriate copies out of appropriate physical registers. This assumes that
|
|
|
|
/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
|
|
|
|
/// being lowered. Returns a SDNode with the same number of values as the
|
|
|
|
/// ISD::CALL.
|
|
|
|
SDNode *MipsTargetLowering::
|
2008-09-13 09:54:27 +08:00
|
|
|
LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
|
2007-06-06 15:42:06 +08:00
|
|
|
unsigned CallingConv, SelectionDAG &DAG) {
|
|
|
|
|
2008-09-13 09:54:27 +08:00
|
|
|
bool isVarArg = TheCall->isVarArg();
|
2007-07-12 07:16:16 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// Assign locations to each value returned by this call.
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2007-07-12 07:16:16 +08:00
|
|
|
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
|
2008-07-28 05:46:04 +08:00
|
|
|
SmallVector<SDValue, 8> ResultVals;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
|
|
Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
|
|
|
|
RVLocs[i].getValVT(), InFlag).getValue(1);
|
|
|
|
InFlag = Chain.getValue(2);
|
|
|
|
ResultVals.push_back(Chain.getValue(0));
|
|
|
|
}
|
|
|
|
|
|
|
|
ResultVals.push_back(Chain);
|
2007-11-05 11:02:32 +08:00
|
|
|
|
|
|
|
// Merge everything together with a MERGE_VALUES node.
|
2008-12-01 19:41:29 +08:00
|
|
|
return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
|
|
|
|
&ResultVals[0], ResultVals.size()).getNode();
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FORMAL_ARGUMENTS Calling Convention Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2008-08-04 15:12:52 +08:00
|
|
|
/// LowerFORMAL_ARGUMENTS - transform physical registers into
|
2007-06-06 15:42:06 +08:00
|
|
|
/// virtual registers and generate load operations for
|
|
|
|
/// arguments places on the stack.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
/// TODO: isVarArg
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2008-08-04 15:12:52 +08:00
|
|
|
LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
|
2007-06-06 15:42:06 +08:00
|
|
|
{
|
2008-08-04 15:12:52 +08:00
|
|
|
SDValue Root = Op.getOperand(0);
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2007-06-06 15:42:06 +08:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2007-08-28 13:08:16 +08:00
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2007-07-12 07:16:16 +08:00
|
|
|
|
2008-09-13 00:56:44 +08:00
|
|
|
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
|
2008-08-04 15:12:52 +08:00
|
|
|
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
|
2007-07-12 07:16:16 +08:00
|
|
|
|
|
|
|
unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2008-07-22 02:52:34 +08:00
|
|
|
// GP must be live into PIC and non-PIC call target.
|
|
|
|
AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
|
2007-11-13 03:49:57 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// Assign locations to all of the incoming arguments.
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
2007-07-12 07:16:16 +08:00
|
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
|
|
|
|
|
2008-08-29 05:40:38 +08:00
|
|
|
CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Mips);
|
2008-07-28 05:46:04 +08:00
|
|
|
SmallVector<SDValue, 16> ArgValues;
|
|
|
|
SDValue StackPtr;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
|
|
|
|
|
|
CCValAssign &VA = ArgLocs[i];
|
|
|
|
|
|
|
|
// Arguments stored on registers
|
|
|
|
if (VA.isRegLoc()) {
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT RegVT = VA.getLocVT();
|
2008-07-09 13:55:53 +08:00
|
|
|
TargetRegisterClass *RC = 0;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
if (RegVT == MVT::i32)
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
RC = Mips::CPURegsRegisterClass;
|
|
|
|
else if (RegVT == MVT::f32) {
|
|
|
|
if (Subtarget->isSingleFloat())
|
|
|
|
RC = Mips::FGR32RegisterClass;
|
|
|
|
else
|
|
|
|
RC = Mips::AFGR32RegisterClass;
|
|
|
|
} else if (RegVT == MVT::f64) {
|
|
|
|
if (!Subtarget->isSingleFloat())
|
|
|
|
RC = Mips::AFGR64RegisterClass;
|
|
|
|
} else
|
|
|
|
assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Transform the arguments stored on
|
|
|
|
// physical registers into virtual ones
|
2007-07-12 07:16:16 +08:00
|
|
|
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// If this is an 8 or 16-bit value, it is really passed promoted
|
|
|
|
// to 32 bits. Insert an assert[sz]ext to capture this, then
|
|
|
|
// truncate to the right size.
|
|
|
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
|
|
|
ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
|
|
|
|
DAG.getValueType(VA.getValVT()));
|
|
|
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
|
|
|
ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
|
|
|
|
DAG.getValueType(VA.getValVT()));
|
|
|
|
|
|
|
|
if (VA.getLocInfo() != CCValAssign::Full)
|
|
|
|
ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
|
|
|
|
|
|
|
|
ArgValues.push_back(ArgValue);
|
|
|
|
|
2007-07-12 07:16:16 +08:00
|
|
|
// To meet ABI, when VARARGS are passed on registers, the registers
|
2007-08-28 13:08:16 +08:00
|
|
|
// must have their values written to the caller stack frame.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
if ((isVarArg) && (Subtarget->isABI_O32())) {
|
2008-08-29 05:40:38 +08:00
|
|
|
if (StackPtr.getNode() == 0)
|
2007-07-12 07:16:16 +08:00
|
|
|
StackPtr = DAG.getRegister(StackReg, getPointerTy());
|
|
|
|
|
2007-08-28 13:08:16 +08:00
|
|
|
// The stack pointer offset is relative to the caller stack frame.
|
|
|
|
// Since the real stack size is unknown here, a negative SPOffset
|
|
|
|
// is used so there's a way to adjust these offsets when the stack
|
|
|
|
// size get known (on EliminateFrameIndex). A dummy SPOffset is
|
|
|
|
// used instead of a direct negative address (which is recorded to
|
|
|
|
// be used on emitPrologue) to avoid mis-calc of the first stack
|
|
|
|
// offset on PEI::calculateFrameObjectOffsets.
|
|
|
|
// Arguments are always 32-bit.
|
|
|
|
int FI = MFI->CreateFixedObject(4, 0);
|
|
|
|
MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
|
2007-07-12 07:16:16 +08:00
|
|
|
|
|
|
|
// emit ISD::STORE whichs stores the
|
|
|
|
// parameter value to a stack Location
|
|
|
|
ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
} else { // VA.isRegLoc()
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// sanity check
|
|
|
|
assert(VA.isMemLoc());
|
|
|
|
|
2007-08-28 13:08:16 +08:00
|
|
|
// The stack pointer offset is relative to the caller stack frame.
|
|
|
|
// Since the real stack size is unknown here, a negative SPOffset
|
|
|
|
// is used so there's a way to adjust these offsets when the stack
|
|
|
|
// size get known (on EliminateFrameIndex). A dummy SPOffset is
|
|
|
|
// used instead of a direct negative address (which is recorded to
|
|
|
|
// be used on emitPrologue) to avoid mis-calc of the first stack
|
|
|
|
// offset on PEI::calculateFrameObjectOffsets.
|
|
|
|
// Arguments are always 32-bit.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
|
|
|
|
int FI = MFI->CreateFixedObject(ArgSize, 0);
|
|
|
|
MipsFI->recordLoadArgsFI(FI, -(ArgSize+
|
|
|
|
(FirstStackArgLoc + VA.getLocMemOffset())));
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Create load nodes to retrieve arguments from the stack
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
|
2007-06-06 15:42:06 +08:00
|
|
|
ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
|
|
|
|
}
|
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
|
|
|
// The mips ABIs for returning structs by value requires that we copy
|
|
|
|
// the sret argument into $v0 for the return. Save the argument into
|
|
|
|
// a virtual register so that we can access it from the return points.
|
|
|
|
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
|
|
unsigned Reg = MipsFI->getSRetReturnReg();
|
|
|
|
if (!Reg) {
|
|
|
|
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
|
|
|
|
MipsFI->setSRetReturnReg(Reg);
|
|
|
|
}
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
ArgValues.push_back(Root);
|
|
|
|
|
|
|
|
// Return the new list of results.
|
2008-12-01 19:41:29 +08:00
|
|
|
return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
|
|
|
|
&ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Return Value Calling Convention Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue MipsTargetLowering::
|
|
|
|
LowerRET(SDValue Op, SelectionDAG &DAG)
|
2007-06-06 15:42:06 +08:00
|
|
|
{
|
|
|
|
// CCValAssign - represent the assignment of
|
|
|
|
// the return value to a location
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2007-07-12 07:16:16 +08:00
|
|
|
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
|
|
|
|
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// CCState - Info about the registers and stack slot.
|
2007-07-12 07:16:16 +08:00
|
|
|
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Analize return values of ISD::RET
|
2008-08-29 05:40:38 +08:00
|
|
|
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// If this is the first return lowered for this function, add
|
|
|
|
// the regs to the liveout set for the function.
|
2007-12-31 12:13:23 +08:00
|
|
|
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
|
2007-06-06 15:42:06 +08:00
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i)
|
2007-07-12 07:16:16 +08:00
|
|
|
if (RVLocs[i].isRegLoc())
|
2007-12-31 12:13:23 +08:00
|
|
|
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// The chain is always operand #0
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
SDValue Flag;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Copy the result values into the output registers.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
|
|
CCValAssign &VA = RVLocs[i];
|
|
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
|
|
|
|
// ISD::RET => ret chain, (regnum1,val1), ...
|
|
|
|
// So i*2+1 index only the regnums
|
2007-10-09 11:15:11 +08:00
|
|
|
Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// guarantee that all emitted copies are
|
|
|
|
// stuck together, avoiding something bad
|
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// The mips ABIs for returning structs by value requires that we copy
|
|
|
|
// the sret argument into $v0 for the return. We saved the argument into
|
|
|
|
// a virtual register in the entry block, so now we copy the value out
|
|
|
|
// and into $v0.
|
|
|
|
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
unsigned Reg = MipsFI->getSRetReturnReg();
|
|
|
|
|
|
|
|
if (!Reg)
|
|
|
|
assert(0 && "sret virtual register not created in the entry block");
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
|
|
|
Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
|
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// Return on Mips is always a "jr $ra"
|
2008-08-29 05:40:38 +08:00
|
|
|
if (Flag.getNode())
|
2007-06-06 15:42:06 +08:00
|
|
|
return DAG.getNode(MipsISD::Ret, MVT::Other,
|
2007-10-09 11:15:11 +08:00
|
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
|
2007-06-06 15:42:06 +08:00
|
|
|
else // Return Void
|
|
|
|
return DAG.getNode(MipsISD::Ret, MVT::Other,
|
2007-10-09 11:15:11 +08:00
|
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32));
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
2007-08-22 00:09:25 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Mips Inline Assembly Support
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
|
|
/// constraint it is for this target.
|
|
|
|
MipsTargetLowering::ConstraintType MipsTargetLowering::
|
|
|
|
getConstraintType(const std::string &Constraint) const
|
|
|
|
{
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// Mips specific constrainy
|
|
|
|
// GCC config/mips/constraints.md
|
|
|
|
//
|
|
|
|
// 'd' : An address register. Equivalent to r
|
|
|
|
// unless generating MIPS16 code.
|
|
|
|
// 'y' : Equivalent to r; retained for
|
|
|
|
// backwards compatibility.
|
2008-07-09 12:45:36 +08:00
|
|
|
// 'f' : Floating Point registers.
|
2007-08-22 00:09:25 +08:00
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
default : break;
|
|
|
|
case 'd':
|
|
|
|
case 'y':
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
case 'f':
|
2007-08-22 00:09:25 +08:00
|
|
|
return C_RegisterClass;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
|
|
|
|
/// return a list of registers that can be used to satisfy the constraint.
|
|
|
|
/// This should only be used for C_RegisterClass constraints.
|
2007-08-22 00:09:25 +08:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
|
2008-06-06 20:08:01 +08:00
|
|
|
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
|
2007-08-22 00:09:25 +08:00
|
|
|
{
|
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
case 'r':
|
|
|
|
return std::make_pair(0U, Mips::CPURegsRegisterClass);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
case 'f':
|
2008-07-08 17:33:14 +08:00
|
|
|
if (VT == MVT::f32) {
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
if (Subtarget->isSingleFloat())
|
|
|
|
return std::make_pair(0U, Mips::FGR32RegisterClass);
|
|
|
|
else
|
|
|
|
return std::make_pair(0U, Mips::AFGR32RegisterClass);
|
2008-07-08 17:33:14 +08:00
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
if (VT == MVT::f64)
|
|
|
|
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
|
|
|
|
return std::make_pair(0U, Mips::AFGR64RegisterClass);
|
2007-08-22 00:09:25 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
/// Given a register class constraint, like 'r', if this corresponds directly
|
|
|
|
/// to an LLVM register class, return a register of 0 and the register class
|
|
|
|
/// pointer.
|
2007-08-22 00:09:25 +08:00
|
|
|
std::vector<unsigned> MipsTargetLowering::
|
|
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
2008-06-06 20:08:01 +08:00
|
|
|
MVT VT) const
|
2007-08-22 00:09:25 +08:00
|
|
|
{
|
|
|
|
if (Constraint.size() != 1)
|
|
|
|
return std::vector<unsigned>();
|
|
|
|
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
default : break;
|
|
|
|
case 'r':
|
|
|
|
// GCC Mips Constraint Letters
|
|
|
|
case 'd':
|
|
|
|
case 'y':
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
|
|
|
|
Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
|
|
|
|
Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
|
|
|
|
Mips::T8, 0);
|
|
|
|
|
|
|
|
case 'f':
|
2008-07-08 17:33:14 +08:00
|
|
|
if (VT == MVT::f32) {
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
if (Subtarget->isSingleFloat())
|
|
|
|
return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
|
|
|
|
Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
|
|
|
|
Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
|
|
|
|
Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
|
|
|
|
Mips::F30, Mips::F31, 0);
|
|
|
|
else
|
|
|
|
return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
|
|
|
|
Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
|
|
|
|
Mips::F28, Mips::F30, 0);
|
2008-07-08 17:33:14 +08:00
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
|
|
|
if (VT == MVT::f64)
|
|
|
|
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
|
|
|
|
return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
|
|
|
|
Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
|
|
|
|
Mips::D14, Mips::D15, 0);
|
2007-08-22 00:09:25 +08:00
|
|
|
}
|
|
|
|
return std::vector<unsigned>();
|
|
|
|
}
|
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
llvm-svn: 57748
2008-10-18 10:06:02 +08:00
|
|
|
|
|
|
|
bool
|
|
|
|
MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
|
|
|
|
// The Mips target isn't yet aware of offsets.
|
|
|
|
return false;
|
|
|
|
}
|