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llvm-project/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out...

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AMDGPU: Handle frame index expansion with no free SGPRs pre gfx9 Since an add instruction must produce an unused carry out, this requires additional SGPRs. This can be avoided by keeping the entire offset computation in SGPRs. If one SGPR is still available, this only costs one extra mov. If none are available, the entire computation can be done in place and reversed. This does assume the use is a VGPR operand. This was already assumed, and we currently only select frame indexes to VALU instructions. This should probably be fixed at some point to handle more possible MIR. llvm-svn: 370929
2019-09-05 01:12:57 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
# Test what happens when an SGPR is unavailable for the unused add
# carry out when materializing the frame index.
# There are truly no free SGPRs, so the entire frame index expansion
# needs to be inverted to restore the original frame register.
---
name: scavenge_sgpr_pei_no_sgprs
tracksRegLiveness: true
stack:
- { id: 0, type: default, offset: 0, size: 4, alignment: 8192 }
- { id: 1, type: default, offset: 0, size: 4, alignment: 8192 }
machineFunctionInfo:
isEntryFunction: false
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
[AMDGPU] Move frame pointer from s34 to s33 Remove the gap left between the stack pointer (s32) and frame pointer (s34) now that the scratch wave offset is no longer a part of the calling convention ABI. Update llvm/docs/AMDGPUUsage.rst to reflect the change. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75657
2020-03-04 09:39:47 +08:00
frameOffsetReg: $sgpr33
AMDGPU: Handle frame index expansion with no free SGPRs pre gfx9 Since an add instruction must produce an unused carry out, this requires additional SGPRs. This can be avoided by keeping the entire offset computation in SGPRs. If one SGPR is still available, this only costs one extra mov. If none are available, the entire computation can be done in place and reversed. This does assume the use is a VGPR operand. This was already assumed, and we currently only select frame indexes to VALU instructions. This should probably be fixed at some point to handle more possible MIR. llvm-svn: 370929
2019-09-05 01:12:57 +08:00
stackPtrOffsetReg: $sgpr32
body: |
bb.0:
liveins: $vgpr1
; CHECK-LABEL: name: scavenge_sgpr_pei_no_sgprs
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: liveins: $vgpr1, $vgpr2
; CHECK: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def $scc, implicit $exec
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr6 = S_ADD_I32 $sgpr32, 524544, implicit-def $scc
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 10:25:51 +08:00
; CHECK: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $exec = S_MOV_B64 killed $sgpr4_sgpr5
; CHECK: $vgpr2 = V_WRITELANE_B32 $sgpr33, 0, undef $vgpr2
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc
[AMDGPU] Remove unused tmp register The temporary register is only used to compute the frame pointer. The frame pointer is overwritten and not used in between, so we can reuse the frame pointer for the computation, saving one register. Differential Revision: https://reviews.llvm.org/D95865
2021-02-03 00:08:57 +08:00
; CHECK: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def $scc
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 1572864, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc
[AMDGPU] Remove scratch rsrc from spill pseudos Differential Revision: https://reviews.llvm.org/D91110
2020-11-10 08:40:35 +08:00
; CHECK: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
[AMDGPU] Move frame pointer from s34 to s33 Remove the gap left between the stack pointer (s32) and frame pointer (s34) now that the scratch wave offset is no longer a part of the calling convention ABI. Update llvm/docs/AMDGPUUsage.rst to reflect the change. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75657
2020-03-04 09:39:47 +08:00
; CHECK: $sgpr33 = S_LSHR_B32 $sgpr33, 6, implicit-def $scc
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr33 = S_ADD_I32 killed $sgpr33, 8192, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $vgpr3 = COPY killed $sgpr33
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr33 = S_ADD_I32 killed $sgpr33, -8192, implicit-def $scc
[AMDGPU] Move frame pointer from s34 to s33 Remove the gap left between the stack pointer (s32) and frame pointer (s34) now that the scratch wave offset is no longer a part of the calling convention ABI. Update llvm/docs/AMDGPUUsage.rst to reflect the change. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75657
2020-03-04 09:39:47 +08:00
; CHECK: $sgpr33 = S_LSHL_B32 $sgpr33, 6, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $vgpr0 = V_OR_B32_e32 killed $vgpr3, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr32 = frame-destroy S_ADD_I32 $sgpr32, -1572864, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $sgpr33 = V_READLANE_B32 $vgpr2, 0
; CHECK: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def $scc, implicit $exec
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr6 = S_ADD_I32 $sgpr32, 524544, implicit-def $scc
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 10:25:51 +08:00
; CHECK: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $exec = S_MOV_B64 killed $sgpr4_sgpr5
AMDGPU: Handle frame index expansion with no free SGPRs pre gfx9 Since an add instruction must produce an unused carry out, this requires additional SGPRs. This can be avoided by keeping the entire offset computation in SGPRs. If one SGPR is still available, this only costs one extra mov. If none are available, the entire computation can be done in place and reversed. This does assume the use is a VGPR operand. This was already assumed, and we currently only select frame indexes to VALU instructions. This should probably be fixed at some point to handle more possible MIR. llvm-svn: 370929
2019-09-05 01:12:57 +08:00
; CHECK: S_ENDPGM 0, implicit $vcc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr29, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc
[AMDGPU] Remove scratch rsrc from spill pseudos Differential Revision: https://reviews.llvm.org/D91110
2020-11-10 08:40:35 +08:00
$vgpr0 = V_MOV_B32_e32 %stack.0, implicit $exec
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
$vgpr0 = V_OR_B32_e32 %stack.1, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31
AMDGPU: Handle frame index expansion with no free SGPRs pre gfx9 Since an add instruction must produce an unused carry out, this requires additional SGPRs. This can be avoided by keeping the entire offset computation in SGPRs. If one SGPR is still available, this only costs one extra mov. If none are available, the entire computation can be done in place and reversed. This does assume the use is a VGPR operand. This was already assumed, and we currently only select frame indexes to VALU instructions. This should probably be fixed at some point to handle more possible MIR. llvm-svn: 370929
2019-09-05 01:12:57 +08:00
S_ENDPGM 0, implicit $vcc
...
# One 32-bit SGPR is available for the intermediate scale computation,
# so only an extra copy to VALU is necessary.
---
name: scavenge_sgpr_pei_one_sgpr
tracksRegLiveness: true
stack:
- { id: 0, type: default, offset: 0, size: 4, alignment: 8192 }
- { id: 1, type: default, offset: 0, size: 4, alignment: 8192 }
machineFunctionInfo:
isEntryFunction: false
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
[AMDGPU] Move frame pointer from s34 to s33 Remove the gap left between the stack pointer (s32) and frame pointer (s34) now that the scratch wave offset is no longer a part of the calling convention ABI. Update llvm/docs/AMDGPUUsage.rst to reflect the change. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75657
2020-03-04 09:39:47 +08:00
frameOffsetReg: $sgpr33
AMDGPU: Handle frame index expansion with no free SGPRs pre gfx9 Since an add instruction must produce an unused carry out, this requires additional SGPRs. This can be avoided by keeping the entire offset computation in SGPRs. If one SGPR is still available, this only costs one extra mov. If none are available, the entire computation can be done in place and reversed. This does assume the use is a VGPR operand. This was already assumed, and we currently only select frame indexes to VALU instructions. This should probably be fixed at some point to handle more possible MIR. llvm-svn: 370929
2019-09-05 01:12:57 +08:00
stackPtrOffsetReg: $sgpr32
body: |
bb.0:
liveins: $vgpr1
; CHECK-LABEL: name: scavenge_sgpr_pei_one_sgpr
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: liveins: $sgpr29, $vgpr1
; CHECK: $sgpr29 = frame-setup COPY $sgpr33
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc
[AMDGPU] Remove unused tmp register The temporary register is only used to compute the frame pointer. The frame pointer is overwritten and not used in between, so we can reuse the frame pointer for the computation, saving one register. Differential Revision: https://reviews.llvm.org/D95865
2021-02-03 00:08:57 +08:00
; CHECK: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def $scc
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 1572864, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc
[AMDGPU] Remove scratch rsrc from spill pseudos Differential Revision: https://reviews.llvm.org/D91110
2020-11-10 08:40:35 +08:00
; CHECK: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $sgpr33 = S_LSHR_B32 $sgpr33, 6, implicit-def $scc
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr33 = S_ADD_I32 killed $sgpr33, 8192, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $vgpr2 = COPY killed $sgpr33
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr33 = S_ADD_I32 killed $sgpr33, -8192, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $sgpr33 = S_LSHL_B32 $sgpr33, 6, implicit-def $scc
; CHECK: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr31
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr32 = frame-destroy S_ADD_I32 $sgpr32, -1572864, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $sgpr33 = frame-destroy COPY $sgpr29
AMDGPU: Handle frame index expansion with no free SGPRs pre gfx9 Since an add instruction must produce an unused carry out, this requires additional SGPRs. This can be avoided by keeping the entire offset computation in SGPRs. If one SGPR is still available, this only costs one extra mov. If none are available, the entire computation can be done in place and reversed. This does assume the use is a VGPR operand. This was already assumed, and we currently only select frame indexes to VALU instructions. This should probably be fixed at some point to handle more possible MIR. llvm-svn: 370929
2019-09-05 01:12:57 +08:00
; CHECK: S_ENDPGM 0, implicit $vcc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr28, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc
[AMDGPU] Remove scratch rsrc from spill pseudos Differential Revision: https://reviews.llvm.org/D91110
2020-11-10 08:40:35 +08:00
$vgpr0 = V_MOV_B32_e32 %stack.0, implicit $exec
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
$vgpr0 = V_OR_B32_e32 %stack.1, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr31
AMDGPU: Handle frame index expansion with no free SGPRs pre gfx9 Since an add instruction must produce an unused carry out, this requires additional SGPRs. This can be avoided by keeping the entire offset computation in SGPRs. If one SGPR is still available, this only costs one extra mov. If none are available, the entire computation can be done in place and reversed. This does assume the use is a VGPR operand. This was already assumed, and we currently only select frame indexes to VALU instructions. This should probably be fixed at some point to handle more possible MIR. llvm-svn: 370929
2019-09-05 01:12:57 +08:00
S_ENDPGM 0, implicit $vcc
...
AMDGPU: Reuse carry out register during FI elimination Summary: Pre gfx9 we need to scavenge a 64-bit SGPR to use as the carry out for an Add. If only one SGPR was available this crashed when trying to scavenge another 32bit SGPR to materialize the offset. Instead, reuse a 32-bit SGPR from the carry out as the offset register. Also prefer to use vcc for the unused carry out when it is available. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70614
2019-11-23 04:25:13 +08:00
# When only one 64-bit SGPR is available for the unused carry out pre gfx9,
# we must reuse one of the 32-bit SGPR sub-regs to materialize the offset.
---
name: scavenge_sgpr_pei_one_sgpr_64
tracksRegLiveness: true
stack:
- { id: 0, type: default, offset: 0, size: 4, alignment: 8192 }
- { id: 1, type: default, offset: 0, size: 4, alignment: 8192 }
machineFunctionInfo:
isEntryFunction: false
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
[AMDGPU] Move frame pointer from s34 to s33 Remove the gap left between the stack pointer (s32) and frame pointer (s34) now that the scratch wave offset is no longer a part of the calling convention ABI. Update llvm/docs/AMDGPUUsage.rst to reflect the change. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75657
2020-03-04 09:39:47 +08:00
frameOffsetReg: $sgpr33
AMDGPU: Reuse carry out register during FI elimination Summary: Pre gfx9 we need to scavenge a 64-bit SGPR to use as the carry out for an Add. If only one SGPR was available this crashed when trying to scavenge another 32bit SGPR to materialize the offset. Instead, reuse a 32-bit SGPR from the carry out as the offset register. Also prefer to use vcc for the unused carry out when it is available. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70614
2019-11-23 04:25:13 +08:00
stackPtrOffsetReg: $sgpr32
body: |
bb.0:
liveins: $vgpr1
; CHECK-LABEL: name: scavenge_sgpr_pei_one_sgpr_64
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: liveins: $sgpr28, $vgpr1
; CHECK: $sgpr28 = frame-setup COPY $sgpr33
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc
[AMDGPU] Remove unused tmp register The temporary register is only used to compute the frame pointer. The frame pointer is overwritten and not used in between, so we can reuse the frame pointer for the computation, saving one register. Differential Revision: https://reviews.llvm.org/D95865
2021-02-03 00:08:57 +08:00
; CHECK: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def $scc
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 1572864, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc
[AMDGPU] Remove scratch rsrc from spill pseudos Differential Revision: https://reviews.llvm.org/D91110
2020-11-10 08:40:35 +08:00
; CHECK: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $sgpr29 = S_LSHR_B32 $sgpr33, 6, implicit-def $scc
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr29 = S_ADD_I32 killed $sgpr29, 8192, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $vgpr2 = COPY killed $sgpr29
; CHECK: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr31
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr32 = frame-destroy S_ADD_I32 $sgpr32, -1572864, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $sgpr33 = frame-destroy COPY $sgpr28
AMDGPU: Reuse carry out register during FI elimination Summary: Pre gfx9 we need to scavenge a 64-bit SGPR to use as the carry out for an Add. If only one SGPR was available this crashed when trying to scavenge another 32bit SGPR to materialize the offset. Instead, reuse a 32-bit SGPR from the carry out as the offset register. Also prefer to use vcc for the unused carry out when it is available. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70614
2019-11-23 04:25:13 +08:00
; CHECK: S_ENDPGM 0, implicit $vcc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr30, implicit-def $sgpr31, implicit-def $vcc
[AMDGPU] Remove scratch rsrc from spill pseudos Differential Revision: https://reviews.llvm.org/D91110
2020-11-10 08:40:35 +08:00
$vgpr0 = V_MOV_B32_e32 %stack.0, implicit $exec
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
$vgpr0 = V_OR_B32_e32 %stack.1, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr31
AMDGPU: Reuse carry out register during FI elimination Summary: Pre gfx9 we need to scavenge a 64-bit SGPR to use as the carry out for an Add. If only one SGPR was available this crashed when trying to scavenge another 32bit SGPR to materialize the offset. Instead, reuse a 32-bit SGPR from the carry out as the offset register. Also prefer to use vcc for the unused carry out when it is available. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70614
2019-11-23 04:25:13 +08:00
S_ENDPGM 0, implicit $vcc
...
# Prefer to use vcc as unused carry out.
---
name: scavenge_sgpr_pei_prefer_vcc
tracksRegLiveness: true
stack:
- { id: 0, type: default, offset: 0, size: 4, alignment: 8192 }
- { id: 1, type: default, offset: 0, size: 4, alignment: 8192 }
machineFunctionInfo:
isEntryFunction: false
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
[AMDGPU] Move frame pointer from s34 to s33 Remove the gap left between the stack pointer (s32) and frame pointer (s34) now that the scratch wave offset is no longer a part of the calling convention ABI. Update llvm/docs/AMDGPUUsage.rst to reflect the change. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75657
2020-03-04 09:39:47 +08:00
frameOffsetReg: $sgpr33
AMDGPU: Reuse carry out register during FI elimination Summary: Pre gfx9 we need to scavenge a 64-bit SGPR to use as the carry out for an Add. If only one SGPR was available this crashed when trying to scavenge another 32bit SGPR to materialize the offset. Instead, reuse a 32-bit SGPR from the carry out as the offset register. Also prefer to use vcc for the unused carry out when it is available. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70614
2019-11-23 04:25:13 +08:00
stackPtrOffsetReg: $sgpr32
body: |
bb.0:
liveins: $vgpr1
; CHECK-LABEL: name: scavenge_sgpr_pei_prefer_vcc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: liveins: $sgpr28, $vgpr1
; CHECK: $sgpr28 = frame-setup COPY $sgpr33
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc
[AMDGPU] Remove unused tmp register The temporary register is only used to compute the frame pointer. The frame pointer is overwritten and not used in between, so we can reuse the frame pointer for the computation, saving one register. Differential Revision: https://reviews.llvm.org/D95865
2021-02-03 00:08:57 +08:00
; CHECK: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def $scc
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 1572864, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr30, implicit-def $sgpr31
[AMDGPU] Remove scratch rsrc from spill pseudos Differential Revision: https://reviews.llvm.org/D91110
2020-11-10 08:40:35 +08:00
; CHECK: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
[AMDGPU] Reuse register during frame index elimination If there were no free VGPRs we would need two emergency spill slots for register scavenging during PEI/frame index elimination. Reuse 'ResultReg' for scale calculation so that only one spill is needed. Differential Revision: https://reviews.llvm.org/D76387
2020-03-19 04:47:39 +08:00
; CHECK: $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
AMDGPU: Reuse carry out register during FI elimination Summary: Pre gfx9 we need to scavenge a 64-bit SGPR to use as the carry out for an Add. If only one SGPR was available this crashed when trying to scavenge another 32bit SGPR to materialize the offset. Instead, reuse a 32-bit SGPR from the carry out as the offset register. Also prefer to use vcc for the unused carry out when it is available. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70614
2019-11-23 04:25:13 +08:00
; CHECK: $vcc_lo = S_MOV_B32 8192
AMDGPU: Rename add/sub with carry out instructions The hardware has created a real mess in the naming for add/sub, which have been renamed basically every generation. Switch the carry out pseudos to have the gfx9/gfx10 names. We were using the original SI/CI v_add_i32/v_sub_i32 names. Later targets reintroduced these names as carryless instructions with a saturating clamp bit, which we do not define. Do this rename so we can unambiguously add these missing instructions. The carry-in versions should also be renamed, but at least those had a consistent _u32 name to begin with. The 16-bit instructions were also renamed, but aren't ambiguous. This does regress assembler error message quality in some cases. In mismatched wave32/wave64 situations, this will switch from "unsupported instruction" to "invalid operand", with the error pointing at the wrong position. I couldn't quite follow how the assembler selects these, but the previous behavior seemed accidental to me. It looked like there was a partial attempt to handle this which was never completed (i.e. there is an AMDGPUOperand::isBoolReg but it isn't used for anything).
2020-07-14 21:18:36 +08:00
; CHECK: $vgpr2, dead $vcc = V_ADD_CO_U32_e64 killed $vcc_lo, killed $vgpr2, 0, implicit $exec
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr31
[AMDGPU] Use s_add_i32 for address additions This allows to convert the add instruction to s_addk_i32 and v_add_nc_u32 instead of needing v_add_co_u32 when converting to a VALU instruction. Differential Revision: https://reviews.llvm.org/D103322
2021-06-07 22:09:48 +08:00
; CHECK: $sgpr32 = frame-destroy S_ADD_I32 $sgpr32, -1572864, implicit-def $scc
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
; CHECK: $sgpr33 = frame-destroy COPY $sgpr28
AMDGPU: Reuse carry out register during FI elimination Summary: Pre gfx9 we need to scavenge a 64-bit SGPR to use as the carry out for an Add. If only one SGPR was available this crashed when trying to scavenge another 32bit SGPR to materialize the offset. Instead, reuse a 32-bit SGPR from the carry out as the offset register. Also prefer to use vcc for the unused carry out when it is available. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70614
2019-11-23 04:25:13 +08:00
; CHECK: S_ENDPGM 0
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $sgpr8, implicit-def $sgpr9, implicit-def $sgpr10, implicit-def $sgpr11, implicit-def $sgpr12, implicit-def $sgpr13, implicit-def $sgpr14, implicit-def $sgpr15, implicit-def $sgpr16, implicit-def $sgpr17, implicit-def $sgpr18, implicit-def $sgpr19, implicit-def $sgpr20, implicit-def $sgpr21, implicit-def $sgpr22, implicit-def $sgpr23, implicit-def $sgpr24, implicit-def $sgpr25, implicit-def $sgpr26, implicit-def $sgpr27, implicit-def $sgpr30, implicit-def $sgpr31
[AMDGPU] Remove scratch rsrc from spill pseudos Differential Revision: https://reviews.llvm.org/D91110
2020-11-10 08:40:35 +08:00
$vgpr0 = V_MOV_B32_e32 %stack.0, implicit $exec
[AMDGPU] Fix typo in implicit operand lists Several tests had a typo where they mentioned sgpr17 twice instead of sgpr17 and sgpr27. This had a significant effect on the "scavenge_sgpr_pei_no_sgprs" tests because there was actually an sgpr available, namely sgpr27. Differential Revision: https://reviews.llvm.org/D100960
2021-04-21 22:32:00 +08:00
$vgpr0 = V_OR_B32_e32 %stack.1, $vgpr1, implicit $exec, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr31
AMDGPU: Reuse carry out register during FI elimination Summary: Pre gfx9 we need to scavenge a 64-bit SGPR to use as the carry out for an Add. If only one SGPR was available this crashed when trying to scavenge another 32bit SGPR to materialize the offset. Instead, reuse a 32-bit SGPR from the carry out as the offset register. Also prefer to use vcc for the unused carry out when it is available. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70614
2019-11-23 04:25:13 +08:00
S_ENDPGM 0
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