llvm-project/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

# RUN: llc -mtriple arm-- -global-isel -run-pass=regbankselect %s -o - | FileCheck %s
--- |
  define void @test_add_s32() { ret void }
  define void @test_add_s16() { ret void }
  define void @test_add_s8() { ret void }
  define void @test_add_s1() { ret void }

  define void @test_loads() { ret void }

  define void @test_fadd_s32() { ret void }
...
---
name:            test_add_s32
# CHECK-LABEL: name: test_add_s32
legalized:       true
regBankSelected: false
selected:        false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }

registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %r0
    %1(s32) = COPY %r1
    %2(s32) = G_ADD %0, %1
    %r0 = COPY %2(s32)
    BX_RET 14, _, implicit %r0

...
---
name:            test_add_s16
# CHECK-LABEL: name: test_add_s16
legalized:       true
regBankSelected: false
selected:        false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }

registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s16) = COPY %r0
    %1(s16) = COPY %r1
    %2(s16) = G_ADD %0, %1
    %r0 = COPY %2(s16)
    BX_RET 14, _, implicit %r0

...
---
name:            test_add_s8
# CHECK-LABEL: name: test_add_s8
legalized:       true
regBankSelected: false
selected:        false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }

registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s8) = COPY %r0
    %1(s8) = COPY %r1
    %2(s8) = G_ADD %0, %1
    %r0 = COPY %2(s8)
    BX_RET 14, _, implicit %r0

...
---
name:            test_add_s1
# CHECK-LABEL: name: test_add_s1
legalized:       true
regBankSelected: false
selected:        false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }

registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s1) = COPY %r0
    %1(s1) = COPY %r1
    %2(s1) = G_ADD %0, %1
    %r0 = COPY %2(s1)
    BX_RET 14, _, implicit %r0

...
---
name:            test_loads
# CHECK-LABEL: name: test_loads
legalized:       true
regBankSelected: false
selected:        false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 5, class: gprb }

registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
body:             |
  bb.0:
    liveins: %r0
    %0(p0) = COPY %r0
    %1(s32) = G_LOAD %0
    %2(s16) = G_LOAD %0
    %3(s8)  = G_LOAD %0
    %4(s1)  = G_LOAD %0
    %5(p0)  = G_LOAD %0
    BX_RET 14, _, implicit %r0

...
---
name:            test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32
legalized:       true
regBankSelected: false
selected:        false
# CHECK: registers:
# CHECK: - { id: 0, class: fprb }
# CHECK: - { id: 1, class: fprb }
# CHECK: - { id: 2, class: fprb }

registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.0:
    liveins: %r0, %r1

    %0(s32) = COPY %s0
    %1(s32) = COPY %s1
    %2(s32) = G_FADD %0, %1
    %s0 = COPY %2(s32)
    BX_RET 14, _, implicit %r0

...