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llvm-project/llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll

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[AArch64] Handle vec4, vec8, vec16 *itofp for half Summary: Set operation action for SINT_TO_FP and UINT_TO_FP nodes with v4i32, v8i8, v8i16 inputs to allow promotion of v4f16 results. Add tests for sitofp and uitofp for vec4, vec8, vec16, and i8, i16, i32, and i64 vectors. Only missing tests are for v16i8 and v16i16 as the shift operations are too complicated to write a proper check sequence. The conversions from v4i64 to v4f16 do not depend on this patch - v4i64 is split and the conversion gets handled while lowering v2i64. I am adding a test here for completeness. Reviewers: aemerson, rengolin, ab, jmolloy, srhines Subscribers: rengolin, aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D9166 llvm-svn: 235609
2015-04-24 01:16:27 +08:00
; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
Teach the AArch64 backend about v4f16 and v8f16 This teaches the AArch64 backend to deal with the operations required to deal with the operations on v4f16 and v8f16 which are exposed by NEON intrinsics, plus the add, sub, mul and div operations. llvm-svn: 216555
2014-08-28 00:16:04 +08:00
define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
entry:
; CHECK-LABEL: add_h:
; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
; CHECK: fcvtn v0.4h, [[RES]]
%0 = fadd <4 x half> %a, %b
ret <4 x half> %0
}
Fix bug while building FP16 constant vectors for AArch64 Summary: Building FP16 constant vectors caused the FP16 data to be bitcast to i64. This patch creates a BITCAST node with the correct value, and adds a test to verify correct handling. Reviewers: mcrosier Reviewed By: mcrosier Subscribers: mcrosier, jmolloy, ab, srhines, llvm-commits, rengolin, aemerson Differential Revision: http://reviews.llvm.org/D8369 llvm-svn: 232562
2015-03-18 07:10:29 +08:00
define <4 x half> @build_h4(<4 x half> %a) {
entry:
; CHECK-LABEL: build_h4:
add support for -print-imm-hex for AArch64 Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a:b:c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
2016-05-14 02:00:09 +08:00
; CHECK: movz [[GPR:w[0-9]+]], #15565
Fix bug while building FP16 constant vectors for AArch64 Summary: Building FP16 constant vectors caused the FP16 data to be bitcast to i64. This patch creates a BITCAST node with the correct value, and adds a test to verify correct handling. Reviewers: mcrosier Reviewed By: mcrosier Subscribers: mcrosier, jmolloy, ab, srhines, llvm-commits, rengolin, aemerson Differential Revision: http://reviews.llvm.org/D8369 llvm-svn: 232562
2015-03-18 07:10:29 +08:00
; CHECK: dup v0.4h, [[GPR]]
ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>
}
Teach the AArch64 backend about v4f16 and v8f16 This teaches the AArch64 backend to deal with the operations required to deal with the operations on v4f16 and v8f16 which are exposed by NEON intrinsics, plus the add, sub, mul and div operations. llvm-svn: 216555
2014-08-28 00:16:04 +08:00
define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
entry:
; CHECK-LABEL: sub_h:
; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
; CHECK: fcvtn v0.4h, [[RES]]
%0 = fsub <4 x half> %a, %b
ret <4 x half> %0
}
define <4 x half> @mul_h(<4 x half> %a, <4 x half> %b) {
entry:
; CHECK-LABEL: mul_h:
; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
; CHECK: fcvtn v0.4h, [[RES]]
%0 = fmul <4 x half> %a, %b
ret <4 x half> %0
}
define <4 x half> @div_h(<4 x half> %a, <4 x half> %b) {
entry:
; CHECK-LABEL: div_h:
; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
; CHECK: fcvtn v0.4h, [[RES]]
%0 = fdiv <4 x half> %a, %b
ret <4 x half> %0
}
define <4 x half> @load_h(<4 x half>* %a) {
entry:
; CHECK-LABEL: load_h:
; CHECK: ldr d0, [x0]
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load <4 x half>, <4 x half>* %a, align 4
Teach the AArch64 backend about v4f16 and v8f16 This teaches the AArch64 backend to deal with the operations required to deal with the operations on v4f16 and v8f16 which are exposed by NEON intrinsics, plus the add, sub, mul and div operations. llvm-svn: 216555
2014-08-28 00:16:04 +08:00
ret <4 x half> %0
}
define void @store_h(<4 x half>* %a, <4 x half> %b) {
entry:
; CHECK-LABEL: store_h:
; CHECK: str d0, [x0]
store <4 x half> %b, <4 x half>* %a, align 4
ret void
}
define <4 x half> @s_to_h(<4 x float> %a) {
; CHECK-LABEL: s_to_h:
; CHECK: fcvtn v0.4h, v0.4s
%1 = fptrunc <4 x float> %a to <4 x half>
ret <4 x half> %1
}
define <4 x half> @d_to_h(<4 x double> %a) {
; CHECK-LABEL: d_to_h:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: ins
; CHECK-DAG: ins
; CHECK-DAG: ins
; CHECK-DAG: ins
%1 = fptrunc <4 x double> %a to <4 x half>
ret <4 x half> %1
}
define <4 x float> @h_to_s(<4 x half> %a) {
; CHECK-LABEL: h_to_s:
; CHECK: fcvtl v0.4s, v0.4h
%1 = fpext <4 x half> %a to <4 x float>
ret <4 x float> %1
}
define <4 x double> @h_to_d(<4 x half> %a) {
; CHECK-LABEL: h_to_d:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: ins
; CHECK-DAG: ins
; CHECK-DAG: ins
; CHECK-DAG: ins
%1 = fpext <4 x half> %a to <4 x double>
ret <4 x double> %1
}
define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) {
; CHECK-LABEL: bitcast_i_to_h:
; CHECK: mov v0.16b, v1.16b
%2 = bitcast <4 x i16> %a to <4 x half>
ret <4 x half> %2
}
define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {
; CHECK-LABEL: bitcast_h_to_i:
; CHECK: mov v0.16b, v1.16b
%2 = bitcast <4 x half> %a to <4 x i16>
ret <4 x i16> %2
}
[AArch64] Handle vec4, vec8, vec16 *itofp for half Summary: Set operation action for SINT_TO_FP and UINT_TO_FP nodes with v4i32, v8i8, v8i16 inputs to allow promotion of v4f16 results. Add tests for sitofp and uitofp for vec4, vec8, vec16, and i8, i16, i32, and i64 vectors. Only missing tests are for v16i8 and v16i16 as the shift operations are too complicated to write a proper check sequence. The conversions from v4i64 to v4f16 do not depend on this patch - v4i64 is split and the conversion gets handled while lowering v2i64. I am adding a test here for completeness. Reviewers: aemerson, rengolin, ab, jmolloy, srhines Subscribers: rengolin, aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D9166 llvm-svn: 235609
2015-04-24 01:16:27 +08:00
define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {
; CHECK-LABEL: sitofp_i8:
; CHECK-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
; CHECK-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
; CHECK-NEXT: fcvtn v0.4h, [[OP4]]
; CHECK-NEXT: ret
%1 = sitofp <4 x i8> %a to <4 x half>
ret <4 x half> %1
}
define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {
; CHECK-LABEL: sitofp_i16:
; CHECK-NEXT: sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
; CHECK-NEXT: scvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
; CHECK-NEXT: ret
%1 = sitofp <4 x i16> %a to <4 x half>
ret <4 x half> %1
}
define <4 x half> @sitofp_i32(<4 x i32> %a) #0 {
; CHECK-LABEL: sitofp_i32:
; CHECK-NEXT: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
%1 = sitofp <4 x i32> %a to <4 x half>
ret <4 x half> %1
}
define <4 x half> @sitofp_i64(<4 x i64> %a) #0 {
; CHECK-LABEL: sitofp_i64:
; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
%1 = sitofp <4 x i64> %a to <4 x half>
ret <4 x half> %1
}
define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {
; CHECK-LABEL: uitofp_i8:
add support for -print-imm-hex for AArch64 Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a:b:c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
2016-05-14 02:00:09 +08:00
; CHECK-NEXT: bic v0.4h, #255, lsl #8
[AArch64] Handle vec4, vec8, vec16 *itofp for half Summary: Set operation action for SINT_TO_FP and UINT_TO_FP nodes with v4i32, v8i8, v8i16 inputs to allow promotion of v4f16 results. Add tests for sitofp and uitofp for vec4, vec8, vec16, and i8, i16, i32, and i64 vectors. Only missing tests are for v16i8 and v16i16 as the shift operations are too complicated to write a proper check sequence. The conversions from v4i64 to v4f16 do not depend on this patch - v4i64 is split and the conversion gets handled while lowering v2i64. I am adding a test here for completeness. Reviewers: aemerson, rengolin, ab, jmolloy, srhines Subscribers: rengolin, aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D9166 llvm-svn: 235609
2015-04-24 01:16:27 +08:00
; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
; CHECK-NEXT: ret
%1 = uitofp <4 x i8> %a to <4 x half>
ret <4 x half> %1
}
define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {
; CHECK-LABEL: uitofp_i16:
; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
; CHECK-NEXT: ret
%1 = uitofp <4 x i16> %a to <4 x half>
ret <4 x half> %1
}
define <4 x half> @uitofp_i32(<4 x i32> %a) #0 {
; CHECK-LABEL: uitofp_i32:
; CHECK-NEXT: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
%1 = uitofp <4 x i32> %a to <4 x half>
ret <4 x half> %1
}
define <4 x half> @uitofp_i64(<4 x i64> %a) #0 {
; CHECK-LABEL: uitofp_i64:
; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
%1 = uitofp <4 x i64> %a to <4 x half>
ret <4 x half> %1
}
Define selection for v4f16, v8f16 scalar_to_vector Summary: This fixes failure when trying to select insertelement <4 x half> undef, half %a, i64 0 which gets transformed to a scalar_to_vector node. The accompanying v4 and v8 tests fail instruction selection without this patch. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15322 llvm-svn: 255072
2015-12-09 07:07:06 +08:00
define void @test_insert_at_zero(half %a, <4 x half>* %b) #0 {
; CHECK-LABEL: test_insert_at_zero:
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
%1 = insertelement <4 x half> undef, half %a, i64 0
store <4 x half> %1, <4 x half>* %b, align 4
ret void
}
Fix fptosi, fptoui from f16 vectors to i8, i16 vectors Summary: Convert f16 vectors to corresponding f32 vectors before doing the conversion to int. Add tests for v4f16, v8f16. Reviewers: ab, jmolloy Subscribers: llvm-commits, srhines Differential Revision: http://reviews.llvm.org/D14936 llvm-svn: 255263
2015-12-11 01:16:49 +08:00
define <4 x i8> @fptosi_i8(<4 x half> %a) #0 {
; CHECK-LABEL: fptosi_i8:
; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
; CHECK-NEXT: xtn v0.4h, [[REG2]]
; CHECK-NEXT: ret
%1 = fptosi<4 x half> %a to <4 x i8>
ret <4 x i8> %1
}
define <4 x i16> @fptosi_i16(<4 x half> %a) #0 {
; CHECK-LABEL: fptosi_i16:
; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
; CHECK-NEXT: xtn v0.4h, [[REG2]]
; CHECK-NEXT: ret
%1 = fptosi<4 x half> %a to <4 x i16>
ret <4 x i16> %1
}
define <4 x i8> @fptoui_i8(<4 x half> %a) #0 {
; CHECK-LABEL: fptoui_i8:
; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
; NOTE: fcvtzs selected here because the xtn shaves the sign bit
; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
; CHECK-NEXT: xtn v0.4h, [[REG2]]
; CHECK-NEXT: ret
%1 = fptoui<4 x half> %a to <4 x i8>
ret <4 x i8> %1
}
define <4 x i16> @fptoui_i16(<4 x half> %a) #0 {
; CHECK-LABEL: fptoui_i16:
; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
; CHECK-NEXT: fcvtzu [[REG2:v[0-9]+\.4s]], [[REG1]]
; CHECK-NEXT: xtn v0.4h, [[REG2]]
; CHECK-NEXT: ret
%1 = fptoui<4 x half> %a to <4 x i16>
ret <4 x i16> %1
}
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_une:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, ne
; CHECK-DAG: csetm {{.*}}, ne
; CHECK-DAG: csetm {{.*}}, ne
; CHECK-DAG: csetm {{.*}}, ne
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp une <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_ueq:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm [[REG1:w[0-9]+]], eq
; CHECK-DAG: csetm [[REG2:w[0-9]+]], eq
; CHECK-DAG: csetm [[REG3:w[0-9]+]], eq
; CHECK-DAG: csetm [[REG4:w[0-9]+]], eq
; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, vc
; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, vc
; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, vc
; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, vc
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp ueq <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_ugt:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, hi
; CHECK-DAG: csetm {{.*}}, hi
; CHECK-DAG: csetm {{.*}}, hi
; CHECK-DAG: csetm {{.*}}, hi
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp ugt <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_uge:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, pl
; CHECK-DAG: csetm {{.*}}, pl
; CHECK-DAG: csetm {{.*}}, pl
; CHECK-DAG: csetm {{.*}}, pl
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp uge <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_ult:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, lt
; CHECK-DAG: csetm {{.*}}, lt
; CHECK-DAG: csetm {{.*}}, lt
; CHECK-DAG: csetm {{.*}}, lt
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp ult <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_ule:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, le
; CHECK-DAG: csetm {{.*}}, le
; CHECK-DAG: csetm {{.*}}, le
; CHECK-DAG: csetm {{.*}}, le
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp ule <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_uno:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, vs
; CHECK-DAG: csetm {{.*}}, vs
; CHECK-DAG: csetm {{.*}}, vs
; CHECK-DAG: csetm {{.*}}, vs
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp uno <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_one:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm [[REG1:w[0-9]+]], mi
; CHECK-DAG: csetm [[REG2:w[0-9]+]], mi
; CHECK-DAG: csetm [[REG3:w[0-9]+]], mi
; CHECK-DAG: csetm [[REG4:w[0-9]+]], mi
; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, le
; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, le
; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, le
; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, le
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp one <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_oeq:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, eq
; CHECK-DAG: csetm {{.*}}, eq
; CHECK-DAG: csetm {{.*}}, eq
; CHECK-DAG: csetm {{.*}}, eq
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp oeq <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_ogt:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, gt
; CHECK-DAG: csetm {{.*}}, gt
; CHECK-DAG: csetm {{.*}}, gt
; CHECK-DAG: csetm {{.*}}, gt
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp ogt <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_oge:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, ge
; CHECK-DAG: csetm {{.*}}, ge
; CHECK-DAG: csetm {{.*}}, ge
; CHECK-DAG: csetm {{.*}}, ge
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp oge <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_olt:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, mi
; CHECK-DAG: csetm {{.*}}, mi
; CHECK-DAG: csetm {{.*}}, mi
; CHECK-DAG: csetm {{.*}}, mi
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp olt <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_ole:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, ls
; CHECK-DAG: csetm {{.*}}, ls
; CHECK-DAG: csetm {{.*}}, ls
; CHECK-DAG: csetm {{.*}}, ls
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp ole <4 x half> %a, %b
ret <4 x i1> %1
}
; Function Attrs: nounwind readnone
; CHECK-LABEL: test_fcmp_ord:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
[AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675
2016-02-24 03:34:13 +08:00
; CHECK-DAG: csetm {{.*}}, vc
; CHECK-DAG: csetm {{.*}}, vc
; CHECK-DAG: csetm {{.*}}, vc
; CHECK-DAG: csetm {{.*}}, vc
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 llvm-svn: 258471
2016-01-22 09:16:57 +08:00
define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 {
%1 = fcmp ord <4 x half> %a, %b
ret <4 x i1> %1
}
[AArch64] Handle vec4, vec8, vec16 *itofp for half Summary: Set operation action for SINT_TO_FP and UINT_TO_FP nodes with v4i32, v8i8, v8i16 inputs to allow promotion of v4f16 results. Add tests for sitofp and uitofp for vec4, vec8, vec16, and i8, i16, i32, and i64 vectors. Only missing tests are for v16i8 and v16i16 as the shift operations are too complicated to write a proper check sequence. The conversions from v4i64 to v4f16 do not depend on this patch - v4i64 is split and the conversion gets handled while lowering v2i64. I am adding a test here for completeness. Reviewers: aemerson, rengolin, ab, jmolloy, srhines Subscribers: rengolin, aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D9166 llvm-svn: 235609
2015-04-24 01:16:27 +08:00
attributes #0 = { nounwind }