2017-05-29 13:38:20 +08:00
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// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
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2013-12-25 09:23:43 +08:00
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// Test new aarch64 intrinsics and types
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#include <arm_neon.h>
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <2 x float> @test_vmla_n_f32(<2 x float> %a, <2 x float> %b, float %c) #0 {
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2016-03-10 02:54:42 +08:00
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// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %c, i32 0
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// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %c, i32 1
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// CHECK: [[MUL_I:%.*]] = fmul <2 x float> %b, [[VECINIT1_I]]
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// CHECK: [[ADD_I:%.*]] = fadd <2 x float> %a, [[MUL_I]]
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// CHECK: ret <2 x float> [[ADD_I]]
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2013-12-25 09:23:43 +08:00
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float32x2_t test_vmla_n_f32(float32x2_t a, float32x2_t b, float32_t c) {
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return vmla_n_f32(a, b, c);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <4 x float> @test_vmlaq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 {
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2016-03-10 02:54:42 +08:00
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// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0
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// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %c, i32 1
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// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %c, i32 2
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// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %c, i32 3
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// CHECK: [[MUL_I:%.*]] = fmul <4 x float> %b, [[VECINIT3_I]]
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// CHECK: [[ADD_I:%.*]] = fadd <4 x float> %a, [[MUL_I]]
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// CHECK: ret <4 x float> [[ADD_I]]
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2013-12-25 09:23:43 +08:00
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float32x4_t test_vmlaq_n_f32(float32x4_t a, float32x4_t b, float32_t c) {
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return vmlaq_n_f32(a, b, c);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <2 x double> @test_vmlaq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 {
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2016-03-10 02:54:42 +08:00
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// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0
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// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1
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// CHECK: [[MUL_I:%.*]] = fmul <2 x double> %b, [[VECINIT1_I]]
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// CHECK: [[ADD_I:%.*]] = fadd <2 x double> %a, [[MUL_I]]
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// CHECK: ret <2 x double> [[ADD_I]]
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2014-02-25 19:13:49 +08:00
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float64x2_t test_vmlaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
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return vmlaq_n_f64(a, b, c);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <4 x float> @test_vmlsq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 {
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2016-03-10 02:54:42 +08:00
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// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0
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// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %c, i32 1
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// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %c, i32 2
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// CHECK: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %c, i32 3
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// CHECK: [[MUL_I:%.*]] = fmul <4 x float> %b, [[VECINIT3_I]]
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// CHECK: [[SUB_I:%.*]] = fsub <4 x float> %a, [[MUL_I]]
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// CHECK: ret <4 x float> [[SUB_I]]
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2013-12-25 09:23:43 +08:00
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float32x4_t test_vmlsq_n_f32(float32x4_t a, float32x4_t b, float32_t c) {
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return vmlsq_n_f32(a, b, c);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <2 x float> @test_vmls_n_f32(<2 x float> %a, <2 x float> %b, float %c) #0 {
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2016-03-10 02:54:42 +08:00
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// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %c, i32 0
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// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %c, i32 1
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// CHECK: [[MUL_I:%.*]] = fmul <2 x float> %b, [[VECINIT1_I]]
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// CHECK: [[SUB_I:%.*]] = fsub <2 x float> %a, [[MUL_I]]
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// CHECK: ret <2 x float> [[SUB_I]]
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2013-12-25 09:23:43 +08:00
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float32x2_t test_vmls_n_f32(float32x2_t a, float32x2_t b, float32_t c) {
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return vmls_n_f32(a, b, c);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <2 x double> @test_vmlsq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 {
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2016-03-10 02:54:42 +08:00
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// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0
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// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1
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// CHECK: [[MUL_I:%.*]] = fmul <2 x double> %b, [[VECINIT1_I]]
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// CHECK: [[SUB_I:%.*]] = fsub <2 x double> %a, [[MUL_I]]
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// CHECK: ret <2 x double> [[SUB_I]]
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2014-02-25 19:13:49 +08:00
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float64x2_t test_vmlsq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
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return vmlsq_n_f64(a, b, c);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <2 x float> @test_vmla_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
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[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
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// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
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// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> zeroinitializer
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// CHECK: [[MUL:%.*]] = fmul <2 x float> [[B:%.*]], [[LANE]]
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// CHECK: [[ADD:%.*]] = fadd <2 x float> [[A:%.*]], [[MUL]]
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// CHECK: ret <2 x float> [[ADD]]
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2013-12-25 09:23:43 +08:00
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float32x2_t test_vmla_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) {
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return vmla_lane_f32(a, b, v, 0);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <4 x float> @test_vmlaq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
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// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
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// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> zeroinitializer
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// CHECK: [[MUL:%.*]] = fmul <4 x float> [[B:%.*]], [[LANE]]
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// CHECK: [[ADD:%.*]] = fadd <4 x float> [[A:%.*]], [[MUL]]
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// CHECK: ret <4 x float> [[ADD]]
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2013-12-25 09:23:43 +08:00
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float32x4_t test_vmlaq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) {
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return vmlaq_lane_f32(a, b, v, 0);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <2 x float> @test_vmla_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
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// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
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// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> zeroinitializer
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// CHECK: [[MUL:%.*]] = fmul <2 x float> [[B:%.*]], [[LANE]]
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// CHECK: [[ADD:%.*]] = fadd <2 x float> [[A:%.*]], [[MUL]]
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// CHECK: ret <2 x float> [[ADD]]
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2013-12-25 09:23:43 +08:00
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float32x2_t test_vmla_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) {
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return vmla_laneq_f32(a, b, v, 0);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <4 x float> @test_vmlaq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
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// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
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// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> zeroinitializer
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// CHECK: [[MUL:%.*]] = fmul <4 x float> [[B:%.*]], [[LANE]]
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// CHECK: [[ADD:%.*]] = fadd <4 x float> [[A:%.*]], [[MUL]]
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// CHECK: ret <4 x float> [[ADD]]
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2013-12-25 09:23:43 +08:00
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float32x4_t test_vmlaq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v) {
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return vmlaq_laneq_f32(a, b, v, 0);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <2 x float> @test_vmls_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
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// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
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// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> zeroinitializer
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// CHECK: [[MUL:%.*]] = fmul <2 x float> [[B:%.*]], [[LANE]]
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// CHECK: [[SUB:%.*]] = fsub <2 x float> [[A:%.*]], [[MUL]]
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// CHECK: ret <2 x float> [[SUB]]
|
2013-12-25 09:23:43 +08:00
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float32x2_t test_vmls_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) {
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return vmls_lane_f32(a, b, v, 0);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <4 x float> @test_vmlsq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
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// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
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// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> zeroinitializer
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// CHECK: [[MUL:%.*]] = fmul <4 x float> [[B:%.*]], [[LANE]]
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// CHECK: [[SUB:%.*]] = fsub <4 x float> [[A:%.*]], [[MUL]]
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// CHECK: ret <4 x float> [[SUB]]
|
2013-12-25 09:23:43 +08:00
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float32x4_t test_vmlsq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) {
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return vmlsq_lane_f32(a, b, v, 0);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <2 x float> @test_vmls_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
|
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// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
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// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> zeroinitializer
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// CHECK: [[MUL:%.*]] = fmul <2 x float> [[B:%.*]], [[LANE]]
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// CHECK: [[SUB:%.*]] = fsub <2 x float> [[A:%.*]], [[MUL]]
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// CHECK: ret <2 x float> [[SUB]]
|
2013-12-25 09:23:43 +08:00
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float32x2_t test_vmls_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) {
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return vmls_laneq_f32(a, b, v, 0);
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}
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2020-02-04 02:09:39 +08:00
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// CHECK-LABEL: define <4 x float> @test_vmlsq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
|
|
|
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
|
|
|
|
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
|
|
|
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> zeroinitializer
|
|
|
|
// CHECK: [[MUL:%.*]] = fmul <4 x float> [[B:%.*]], [[LANE]]
|
|
|
|
// CHECK: [[SUB:%.*]] = fsub <4 x float> [[A:%.*]], [[MUL]]
|
|
|
|
// CHECK: ret <4 x float> [[SUB]]
|
2013-12-25 09:23:43 +08:00
|
|
|
float32x4_t test_vmlsq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v) {
|
|
|
|
return vmlsq_laneq_f32(a, b, v, 0);
|
|
|
|
}
|
|
|
|
|
2020-02-04 02:09:39 +08:00
|
|
|
// CHECK-LABEL: define <2 x float> @test_vmla_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
|
|
|
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
|
|
|
|
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
|
|
|
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> <i32 1, i32 1>
|
|
|
|
// CHECK: [[MUL:%.*]] = fmul <2 x float> [[B:%.*]], [[LANE]]
|
|
|
|
// CHECK: [[ADD:%.*]] = fadd <2 x float> [[A:%.*]], [[MUL]]
|
|
|
|
// CHECK: ret <2 x float> [[ADD]]
|
2013-12-25 09:23:43 +08:00
|
|
|
float32x2_t test_vmla_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) {
|
|
|
|
return vmla_lane_f32(a, b, v, 1);
|
|
|
|
}
|
|
|
|
|
2020-02-04 02:09:39 +08:00
|
|
|
// CHECK-LABEL: define <4 x float> @test_vmlaq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
|
|
|
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
|
|
|
|
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
|
|
|
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
|
|
// CHECK: [[MUL:%.*]] = fmul <4 x float> [[B:%.*]], [[LANE]]
|
|
|
|
// CHECK: [[ADD:%.*]] = fadd <4 x float> [[A:%.*]], [[MUL]]
|
|
|
|
// CHECK: ret <4 x float> [[ADD]]
|
2013-12-25 09:23:43 +08:00
|
|
|
float32x4_t test_vmlaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) {
|
|
|
|
return vmlaq_lane_f32(a, b, v, 1);
|
|
|
|
}
|
|
|
|
|
2020-02-04 02:09:39 +08:00
|
|
|
// CHECK-LABEL: define <2 x float> @test_vmla_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
|
|
|
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
|
|
|
|
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
|
|
|
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> <i32 3, i32 3>
|
|
|
|
// CHECK: [[MUL:%.*]] = fmul <2 x float> [[B:%.*]], [[LANE]]
|
|
|
|
// CHECK: [[ADD:%.*]] = fadd <2 x float> [[A:%.*]], [[MUL]]
|
|
|
|
// CHECK: ret <2 x float> [[ADD]]
|
2013-12-25 09:23:43 +08:00
|
|
|
float32x2_t test_vmla_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) {
|
|
|
|
return vmla_laneq_f32(a, b, v, 3);
|
|
|
|
}
|
|
|
|
|
2020-02-04 02:09:39 +08:00
|
|
|
// CHECK-LABEL: define <4 x float> @test_vmlaq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
|
|
|
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
|
|
|
|
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
|
|
|
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
|
|
|
|
// CHECK: [[MUL:%.*]] = fmul <4 x float> [[B:%.*]], [[LANE]]
|
|
|
|
// CHECK: [[ADD:%.*]] = fadd <4 x float> [[A:%.*]], [[MUL]]
|
|
|
|
// CHECK: ret <4 x float> [[ADD]]
|
2013-12-25 09:23:43 +08:00
|
|
|
float32x4_t test_vmlaq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) {
|
|
|
|
return vmlaq_laneq_f32(a, b, v, 3);
|
|
|
|
}
|
|
|
|
|
2020-02-04 02:09:39 +08:00
|
|
|
// CHECK-LABEL: define <2 x float> @test_vmls_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
|
|
|
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
|
|
|
|
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
|
|
|
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> <i32 1, i32 1>
|
|
|
|
// CHECK: [[MUL:%.*]] = fmul <2 x float> [[B:%.*]], [[LANE]]
|
|
|
|
// CHECK: [[SUB:%.*]] = fsub <2 x float> [[A:%.*]], [[MUL]]
|
|
|
|
// CHECK: ret <2 x float> [[SUB]]
|
2013-12-25 09:23:43 +08:00
|
|
|
float32x2_t test_vmls_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) {
|
|
|
|
return vmls_lane_f32(a, b, v, 1);
|
|
|
|
}
|
|
|
|
|
2020-02-04 02:09:39 +08:00
|
|
|
// CHECK-LABEL: define <4 x float> @test_vmlsq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
|
|
|
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
|
|
|
|
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
|
|
|
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
|
|
// CHECK: [[MUL:%.*]] = fmul <4 x float> [[B:%.*]], [[LANE]]
|
|
|
|
// CHECK: [[SUB:%.*]] = fsub <4 x float> [[A:%.*]], [[MUL]]
|
|
|
|
// CHECK: ret <4 x float> [[SUB]]
|
|
|
|
//
|
2013-12-25 09:23:43 +08:00
|
|
|
float32x4_t test_vmlsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) {
|
|
|
|
return vmlsq_lane_f32(a, b, v, 1);
|
|
|
|
}
|
2020-02-04 02:09:39 +08:00
|
|
|
// CHECK-LABEL: define <2 x float> @test_vmls_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
|
|
|
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
|
|
|
|
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
|
|
|
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> <i32 3, i32 3>
|
|
|
|
// CHECK: [[MUL:%.*]] = fmul <2 x float> [[B:%.*]], [[LANE]]
|
|
|
|
// CHECK: [[SUB:%.*]] = fsub <2 x float> [[A:%.*]], [[MUL]]
|
|
|
|
// CHECK: ret <2 x float> [[SUB]]
|
2013-12-25 09:23:43 +08:00
|
|
|
float32x2_t test_vmls_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) {
|
|
|
|
return vmls_laneq_f32(a, b, v, 3);
|
|
|
|
}
|
|
|
|
|
2020-02-04 02:09:39 +08:00
|
|
|
// CHECK-LABEL: define <4 x float> @test_vmlsq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
|
[ARM] Enabling range checks on Neon intrinsics' lane arguments
Summary:
Range checks were not properly performed in the lane arguments of Neon
intrinsics implemented based on splat operations. Calls to those
intrinsics where translated to `__builtin__shufflevector` calls directly
by the pre-processor through the arm_neon.h macros, missing the chance
for the proper range checks.
This patch enables the range check by introducing an auxiliary splat
instruction in arm_neon.td, delaying the translation to shufflevector
calls to CGBuiltin.cpp in clang after the checks were performed.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, ostannard
Reviewed By: ostannard
Subscribers: ostannard, dnsampaio, danielkiss, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74619
2020-03-06 00:45:03 +08:00
|
|
|
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
|
|
|
|
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
|
|
|
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
|
|
|
|
// CHECK: [[MUL:%.*]] = fmul <4 x float> [[B:%.*]], [[LANE]]
|
|
|
|
// CHECK: [[SUB:%.*]] = fsub <4 x float> [[A:%.*]], [[MUL]]
|
|
|
|
// CHECK: ret <4 x float> [[SUB]]
|
2013-12-25 09:23:43 +08:00
|
|
|
float32x4_t test_vmlsq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) {
|
|
|
|
return vmlsq_laneq_f32(a, b, v, 3);
|
|
|
|
}
|
|
|
|
|
2020-02-04 02:09:39 +08:00
|
|
|
// CHECK-LABEL: define <2 x double> @test_vfmaq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 {
|
2016-03-10 02:54:42 +08:00
|
|
|
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0
|
|
|
|
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1
|
2016-07-26 13:52:37 +08:00
|
|
|
// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> [[VECINIT1_I]], <2 x double> %a)
|
2016-03-10 02:54:42 +08:00
|
|
|
// CHECK: ret <2 x double> [[TMP6]]
|
2014-02-25 19:13:49 +08:00
|
|
|
float64x2_t test_vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
|
|
|
|
return vfmaq_n_f64(a, b, c);
|
|
|
|
}
|
|
|
|
|
2020-02-04 02:09:39 +08:00
|
|
|
// CHECK-LABEL: define <2 x double> @test_vfmsq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 {
|
2019-10-14 23:35:01 +08:00
|
|
|
// CHECK: [[SUB_I:%.*]] = fneg <2 x double> %b
|
2016-03-10 02:54:42 +08:00
|
|
|
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0
|
|
|
|
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1
|
2018-10-25 01:42:17 +08:00
|
|
|
// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[SUB_I]], <2 x double> [[VECINIT1_I]], <2 x double> %a) #3
|
[ARM NEON] Define vfms_f32 on ARM, and all vfms using vfma.
r259537 added vfma/vfms to armv7, but the builtin was only lowered
on the AArch64 side. Instead of supporting it on ARM, get rid of it.
The vfms builtin lowered to:
%nb = fsub float -0.0, %b
%r = @llvm.fma.f32(%a, %nb, %c)
Instead, define the operation in terms of vfma, and swap the
multiplicands. It now lowers to:
%na = fsub float -0.0, %a
%r = @llvm.fma.f32(%na, %b, %c)
This matches the instruction more closely, and lets current LLVM
generate the "natural" operand ordering:
fmls.2s v0, v1, v2
instead of the crooked (but equivalent):
fmls.2s v0, v2, v1
Except for theses changes, assembly is identical.
LLVM accepts both commutations, and the LLVM tests in:
test/CodeGen/AArch64/arm64-fmadd.ll
test/CodeGen/AArch64/fp-dp3.ll
test/CodeGen/AArch64/neon-fma.ll
test/CodeGen/ARM/fusedMAC.ll
already check either the new one only, or both.
Also verified against the test-suite unittests.
llvm-svn: 266807
2016-04-20 03:44:45 +08:00
|
|
|
// CHECK: ret <2 x double> [[TMP6]]
|
2014-02-25 19:13:49 +08:00
|
|
|
float64x2_t test_vfmsq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
|
|
|
|
return vfmsq_n_f64(a, b, c);
|
|
|
|
}
|
2018-10-25 01:42:17 +08:00
|
|
|
|
|
|
|
// CHECK: attributes #0 ={{.*}}"min-legal-vector-width"="64"
|
|
|
|
// CHECK: attributes #1 ={{.*}}"min-legal-vector-width"="128"
|