forked from OSchip/llvm-project
441 lines
17 KiB
LLVM
441 lines
17 KiB
LLVM
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; RUN: opt -S -o - -mtriple=armv7-apple-ios7.0 -atomic-expand -codegen-opt-level=1 %s | FileCheck %s
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define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) {
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; CHECK-LABEL: @test_atomic_xchg_i8
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; CHECK-NOT: dmb
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK-NOT: dmb
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic
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ret i8 %res
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}
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define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) {
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; CHECK-LABEL: @test_atomic_add_i16
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
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; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend
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; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i16 [[OLDVAL]]
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%res = atomicrmw add i16* %ptr, i16 %addend seq_cst
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ret i16 %res
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}
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define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) {
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; CHECK-LABEL: @test_atomic_sub_i32
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; CHECK-NOT: dmb
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr)
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; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i32 [[OLDVAL]]
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%res = atomicrmw sub i32* %ptr, i32 %subend acquire
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ret i32 %res
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}
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define i8 @test_atomic_and_i8(i8* %ptr, i8 %andend) {
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; CHECK-LABEL: @test_atomic_and_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[NEWVAL:%.*]] = and i8 [[OLDVAL]], %andend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK-NOT: dmb
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw and i8* %ptr, i8 %andend release
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ret i8 %res
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}
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define i16 @test_atomic_nand_i16(i16* %ptr, i16 %nandend) {
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; CHECK-LABEL: @test_atomic_nand_i16
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
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; CHECK: [[NEWVAL_TMP:%.*]] = and i16 [[OLDVAL]], %nandend
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; CHECK: [[NEWVAL:%.*]] = xor i16 [[NEWVAL_TMP]], -1
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; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i16 [[OLDVAL]]
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%res = atomicrmw nand i16* %ptr, i16 %nandend seq_cst
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ret i16 %res
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}
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define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) {
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; CHECK-LABEL: @test_atomic_or_i64
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
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; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
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; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
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; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
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; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64
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; CHECK: [[HI64_TMP:%.*]] = zext i32 [[HI]] to i64
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; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32
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; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]]
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; CHECK: [[NEWVAL:%.*]] = or i64 [[OLDVAL]], %orend
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; CHECK: [[NEWLO:%.*]] = trunc i64 [[NEWVAL]] to i32
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; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 [[NEWVAL]], 32
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; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
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; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i64 [[OLDVAL]]
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%res = atomicrmw or i64* %ptr, i64 %orend seq_cst
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ret i64 %res
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}
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define i8 @test_atomic_xor_i8(i8* %ptr, i8 %xorend) {
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; CHECK-LABEL: @test_atomic_xor_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[NEWVAL:%.*]] = xor i8 [[OLDVAL]], %xorend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw xor i8* %ptr, i8 %xorend seq_cst
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ret i8 %res
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}
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define i8 @test_atomic_max_i8(i8* %ptr, i8 %maxend) {
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; CHECK-LABEL: @test_atomic_max_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[WANT_OLD:%.*]] = icmp sgt i8 [[OLDVAL]], %maxend
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; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %maxend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw max i8* %ptr, i8 %maxend seq_cst
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ret i8 %res
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}
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define i8 @test_atomic_min_i8(i8* %ptr, i8 %minend) {
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; CHECK-LABEL: @test_atomic_min_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[WANT_OLD:%.*]] = icmp sle i8 [[OLDVAL]], %minend
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; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %minend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw min i8* %ptr, i8 %minend seq_cst
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ret i8 %res
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}
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define i8 @test_atomic_umax_i8(i8* %ptr, i8 %umaxend) {
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; CHECK-LABEL: @test_atomic_umax_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[WANT_OLD:%.*]] = icmp ugt i8 [[OLDVAL]], %umaxend
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; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %umaxend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw umax i8* %ptr, i8 %umaxend seq_cst
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ret i8 %res
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}
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define i8 @test_atomic_umin_i8(i8* %ptr, i8 %uminend) {
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; CHECK-LABEL: @test_atomic_umin_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[WANT_OLD:%.*]] = icmp ule i8 [[OLDVAL]], %uminend
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; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %uminend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw umin i8* %ptr, i8 %uminend seq_cst
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ret i8 %res
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}
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define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
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; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst
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; CHECK: br label %[[START:.*]]
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; CHECK: [[START]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired
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; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
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; CHECK: [[FENCED_STORE]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[LOADED_LOOP:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ]
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; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD]]
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; CHECK: [[RELEASED_LOAD]]:
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; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i8
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; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i8 [[OLDVAL_LOOP]], %desired
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; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]]
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; CHECK: [[SUCCESS_BB]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[DONE:.*]]
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; CHECK: [[NO_STORE_BB]]:
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; CHECK-NEXT: [[LOADED_NO_STORE:%.*]] = phi i8 [ [[OLDVAL]], %[[START]] ], [ [[OLDVAL_LOOP]], %[[RELEASED_LOAD]] ]
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; CHECK-NEXT: call void @llvm.arm.clrex()
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; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
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; CHECK: [[FAILURE_BB]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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||
|
|
; CHECK: br label %[[DONE]]
|
||
|
|
|
||
|
|
; CHECK: [[DONE]]:
|
||
|
|
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
|
||
|
|
; CHECK: [[LOADED:%.*]] = phi i8 [ [[LOADED_LOOP]], %[[SUCCESS_BB]] ], [ [[LOADED_NO_STORE]], %[[FAILURE_BB]] ]
|
||
|
|
; CHECK: ret i8 [[LOADED]]
|
||
|
|
|
||
|
|
%pairold = cmpxchg i8* %ptr, i8 %desired, i8 %newval seq_cst seq_cst
|
||
|
|
%old = extractvalue { i8, i1 } %pairold, 0
|
||
|
|
ret i8 %old
|
||
|
|
}
|
||
|
|
|
||
|
|
define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) {
|
||
|
|
; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic
|
||
|
|
; CHECK: br label %[[LOOP:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[LOOP]]:
|
||
|
|
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr)
|
||
|
|
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16
|
||
|
|
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired
|
||
|
|
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[FENCED_STORE]]:
|
||
|
|
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||
|
|
; CHECK: br label %[[LOOP:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[LOOP]]:
|
||
|
|
; CHECK: [[LOADED_LOOP:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ]
|
||
|
|
; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32
|
||
|
|
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr)
|
||
|
|
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
|
||
|
|
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[RELEASED_LOAD]]:
|
||
|
|
; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr)
|
||
|
|
; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i16
|
||
|
|
; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i16 [[OLDVAL_LOOP]], %desired
|
||
|
|
; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]]
|
||
|
|
|
||
|
|
; CHECK: [[SUCCESS_BB]]:
|
||
|
|
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||
|
|
; CHECK: br label %[[DONE:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[NO_STORE_BB]]:
|
||
|
|
; CHECK-NEXT: [[LOADED_NO_STORE:%.*]] = phi i16 [ [[OLDVAL]], %[[START]] ], [ [[OLDVAL_LOOP]], %[[RELEASED_LOAD]] ]
|
||
|
|
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||
|
|
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[FAILURE_BB]]:
|
||
|
|
; CHECK-NOT: dmb
|
||
|
|
; CHECK: br label %[[DONE]]
|
||
|
|
|
||
|
|
; CHECK: [[DONE]]:
|
||
|
|
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
|
||
|
|
; CHECK: [[LOADED:%.*]] = phi i16 [ [[LOADED_LOOP]], %[[SUCCESS_BB]] ], [ [[LOADED_NO_STORE]], %[[FAILURE_BB]] ]
|
||
|
|
; CHECK: ret i16 [[LOADED]]
|
||
|
|
|
||
|
|
%pairold = cmpxchg i16* %ptr, i16 %desired, i16 %newval seq_cst monotonic
|
||
|
|
%old = extractvalue { i16, i1 } %pairold, 0
|
||
|
|
ret i16 %old
|
||
|
|
}
|
||
|
|
|
||
|
|
define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) {
|
||
|
|
; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire
|
||
|
|
; CHECK-NOT: dmb
|
||
|
|
; CHECK: br label %[[LOOP:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[LOOP]]:
|
||
|
|
; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr)
|
||
|
|
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired
|
||
|
|
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[TRY_STORE]]:
|
||
|
|
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr)
|
||
|
|
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
|
||
|
|
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
|
||
|
|
|
||
|
|
; CHECK: [[SUCCESS_BB]]:
|
||
|
|
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||
|
|
; CHECK: br label %[[DONE:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[NO_STORE_BB]]:
|
||
|
|
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||
|
|
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[FAILURE_BB]]:
|
||
|
|
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||
|
|
; CHECK: br label %[[DONE]]
|
||
|
|
|
||
|
|
; CHECK: [[DONE]]:
|
||
|
|
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
|
||
|
|
; CHECK: ret i32 [[OLDVAL]]
|
||
|
|
|
||
|
|
%pairold = cmpxchg i32* %ptr, i32 %desired, i32 %newval acquire acquire
|
||
|
|
%old = extractvalue { i32, i1 } %pairold, 0
|
||
|
|
ret i32 %old
|
||
|
|
}
|
||
|
|
|
||
|
|
define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %newval) {
|
||
|
|
; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic
|
||
|
|
; CHECK-NOT: dmb
|
||
|
|
; CHECK: br label %[[LOOP:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[LOOP]]:
|
||
|
|
; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
|
||
|
|
; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
|
||
|
|
; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
|
||
|
|
; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
|
||
|
|
; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64
|
||
|
|
; CHECK: [[HI64_TMP:%.*]] = zext i32 [[HI]] to i64
|
||
|
|
; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32
|
||
|
|
; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]]
|
||
|
|
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i64 [[OLDVAL]], %desired
|
||
|
|
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[TRY_STORE]]:
|
||
|
|
; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32
|
||
|
|
; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 %newval, 32
|
||
|
|
; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
|
||
|
|
; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
|
||
|
|
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
|
||
|
|
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
|
||
|
|
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
|
||
|
|
|
||
|
|
; CHECK: [[SUCCESS_BB]]:
|
||
|
|
; CHECK-NOT: dmb
|
||
|
|
; CHECK: br label %[[DONE:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[NO_STORE_BB]]:
|
||
|
|
; CHECK-NEXT: call void @llvm.arm.clrex()
|
||
|
|
; CHECK-NEXT: br label %[[FAILURE_BB:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[FAILURE_BB]]:
|
||
|
|
; CHECK-NOT: dmb
|
||
|
|
; CHECK: br label %[[DONE]]
|
||
|
|
|
||
|
|
; CHECK: [[DONE]]:
|
||
|
|
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
|
||
|
|
; CHECK: ret i64 [[OLDVAL]]
|
||
|
|
|
||
|
|
%pairold = cmpxchg i64* %ptr, i64 %desired, i64 %newval monotonic monotonic
|
||
|
|
%old = extractvalue { i64, i1 } %pairold, 0
|
||
|
|
ret i64 %old
|
||
|
|
}
|
||
|
|
|
||
|
|
define i32 @test_cmpxchg_minsize(i32* %addr, i32 %desired, i32 %new) minsize {
|
||
|
|
; CHECK-LABEL: @test_cmpxchg_minsize
|
||
|
|
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||
|
|
; CHECK: br label %[[START:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[START]]:
|
||
|
|
; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
|
||
|
|
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
|
||
|
|
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[TRY_STORE]]:
|
||
|
|
; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr)
|
||
|
|
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
|
||
|
|
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[START]]
|
||
|
|
|
||
|
|
; CHECK: [[SUCCESS_BB]]:
|
||
|
|
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||
|
|
; CHECK: br label %[[END:.*]]
|
||
|
|
|
||
|
|
; CHECK: [[NO_STORE_BB]]:
|
||
|
|
; CHECK: call void @llvm.arm.clrex()
|
||
|
|
; CHECK: br label %[[FAILURE_BB]]
|
||
|
|
|
||
|
|
; CHECK: [[FAILURE_BB]]:
|
||
|
|
; CHECK: call void @llvm.arm.dmb(i32 11)
|
||
|
|
; CHECK: br label %[[END]]
|
||
|
|
|
||
|
|
; CHECK: [[END]]:
|
||
|
|
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
|
||
|
|
; CHECK: ret i32 [[LOADED]]
|
||
|
|
|
||
|
|
%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
|
||
|
|
%oldval = extractvalue { i32, i1 } %pair, 0
|
||
|
|
ret i32 %oldval
|
||
|
|
}
|