maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp

3533 lines
140 KiB
C++
Raw Normal View History

Added -*- C++ -*- mode to the comments. llvm-svn: 4826
2002-11-23 06:42:50 +08:00
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
* Remove trailing whitespace * Convert tabs to spaces llvm-svn: 21426
2005-04-22 07:38:14 +08:00
//
Added LLVM project notice to the top of every C++ source file. Header files will be on the way. llvm-svn: 9298
2003-10-21 03:43:21 +08:00
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
* Remove trailing whitespace * Convert tabs to spaces llvm-svn: 21426
2005-04-22 07:38:14 +08:00
//
Added LLVM project notice to the top of every C++ source file. Header files will be on the way. llvm-svn: 9298
2003-10-21 03:43:21 +08:00
//===----------------------------------------------------------------------===//
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284
2002-10-26 06:55:53 +08:00
//
Rename MachineInstrInfo -> TargetInstrInfo llvm-svn: 5272
2003-01-15 06:00:31 +08:00
// This file contains the X86 implementation of the TargetInstrInfo class.
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284
2002-10-26 06:55:53 +08:00
//
//===----------------------------------------------------------------------===//
Rename X86InstructionInfo to X86InstrInfo llvm-svn: 4413
2002-10-30 05:05:24 +08:00
#include "X86InstrInfo.h"
* Move information about Implicit Defs/Uses into X86InstrInfo.def. * Expose information about implicit defs/uses of register through the MachineInstrInfo.h file. llvm-svn: 4877
2002-12-03 13:42:53 +08:00
#include "X86.h"
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
#include "X86InstrBuilder.h"
Move some more functionality from MRegisterInfo to TargetInstrInfo. llvm-svn: 45603
2008-01-05 07:57:37 +08:00
#include "X86MachineFunctionInfo.h"
Fix a build breaker. llvm-svn: 28574
2006-05-31 05:45:53 +08:00
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
Tidy up #includes, deleting a bunch of unnecessary #includes. llvm-svn: 61715
2009-01-06 01:59:02 +08:00
#include "llvm/DerivedTypes.h"
Begin the painful process of tearing apart the rat'ss nest that is Constants.cpp and ConstantFold.cpp. This involves temporarily hard wiring some parts to use the global context. This isn't ideal, but it's the only way I could figure out to make this process vaguely incremental. llvm-svn: 75445
2009-07-13 12:09:18 +08:00
#include "llvm/LLVMContext.h"
Add lengthof and endof templates that hide a lot of sizeof computations. Patch by Sterling Stein! llvm-svn: 41758
2007-09-07 12:06:50 +08:00
#include "llvm/ADT/STLExtras.h"
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
#include "llvm/CodeGen/MachineConstantPool.h"
Move some more functionality from MRegisterInfo to TargetInstrInfo. llvm-svn: 45603
2008-01-05 07:57:37 +08:00
#include "llvm/CodeGen/MachineFrameInfo.h"
Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface. llvm-svn: 6320
2003-05-24 08:09:50 +08:00
#include "llvm/CodeGen/MachineInstrBuilder.h"
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
2007-12-31 12:13:23 +08:00
#include "llvm/CodeGen/MachineRegisterInfo.h"
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
#include "llvm/CodeGen/LiveVariables.h"
Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a machine instruction loads or stores from/to a stack slot. Unlike isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be something other than a pure load/store (e.g. it may be an arithmetic operation with a memory operand). This helps AsmPrinter determine when to print a spill/reload comment. This is only a hint since we may not be able to figure this out in all cases. As such, it should not be relied upon for correctness. Implement for X86. Return false by default for other architectures. llvm-svn: 87026
2009-11-13 04:55:29 +08:00
#include "llvm/CodeGen/PseudoSourceValue.h"
on darwin empty functions need to codegen into something of non-zero length, otherwise labels get incorrectly merged. We handled this by emitting a ".byte 0", but this isn't correct on thumb/arm targets where the text segment needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This is more gross than it should be because arm/ppc are not fully mc'ized yet. This fixes rdar://7908505 llvm-svn: 102400
2010-04-27 07:37:21 +08:00
#include "llvm/MC/MCInst.h"
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
#include "llvm/Support/CommandLine.h"
Change errs() to dbgs(). llvm-svn: 92653
2010-01-05 09:29:29 +08:00
#include "llvm/Support/Debug.h"
Start converting to new error handling API. cerr+abort -> llvm_report_error assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included) llvm-svn: 75018
2009-07-09 02:01:40 +08:00
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
2007-09-25 09:57:46 +08:00
#include "llvm/Target/TargetOptions.h"
Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. llvm-svn: 79763
2009-08-23 04:48:53 +08:00
#include "llvm/MC/MCAsmInfo.h"
Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a machine instruction loads or stores from/to a stack slot. Unlike isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be something other than a pure load/store (e.g. it may be an arithmetic operation with a memory operand). This helps AsmPrinter determine when to print a spill/reload comment. This is only a hint since we may not be able to figure this out in all cases. As such, it should not be relied upon for correctness. Implement for X86. Return false by default for other architectures. llvm-svn: 87026
2009-11-13 04:55:29 +08:00
#include <limits>
Hide the call to InitMCInstrInfo into tblgen generated ctor. llvm-svn: 134244
2011-07-02 01:57:27 +08:00
#define GET_INSTRINFO_CTOR
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc llvm-svn: 134024
2011-06-29 04:07:07 +08:00
#include "X86GenInstrInfo.inc"
Put all LLVM code into the llvm namespace, as per bug 109. llvm-svn: 9903
2003-11-12 06:41:34 +08:00
using namespace llvm;
remove various std::ostream version of printing methods from MachineInstr and MachineOperand. This required eliminating a bunch of stuff that was using DOUT, I hope that bill doesn't mind me stealing his fun. ;-) llvm-svn: 79813
2009-08-23 11:41:05 +08:00
static cl::opt<bool>
NoFusing("disable-spill-fusing",
cl::desc("Disable fusing of spill code into instructions"));
static cl::opt<bool>
PrintFailedFusing("print-failed-fuse-candidates",
cl::desc("Print instructions that the allocator wants to"
" fuse, but the X86 backend currently can't"),
cl::Hidden);
static cl::opt<bool>
ReMatPICStubLoad("remat-pic-stub-load",
cl::desc("Re-materialize load from stub in PIC mode"),
cl::init(false), cl::Hidden);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
enum {
// Select which memory operand is being unfolded.
// (stored in bits 0 - 7)
TB_INDEX_0 = 0,
TB_INDEX_1 = 1,
TB_INDEX_2 = 2,
TB_INDEX_MASK = 0xff,
// Minimum alignment required for load/store.
// Used for RegOp->MemOp conversion.
// (stored in bits 8 - 15)
TB_ALIGN_SHIFT = 8,
TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT,
// Do not insert the reverse map (MemOp -> RegOp) into the table.
// This may be needed because there is a many -> one mapping.
TB_NO_REVERSE = 1 << 16,
// Do not insert the forward map (RegOp -> MemOp) into the table.
// This is needed for Native Client, which prohibits branch
// instructions from using a memory operand.
TB_NO_FORWARD = 1 << 17,
TB_FOLDED_LOAD = 1 << 18,
TB_FOLDED_STORE = 1 << 19
};
Fix a build breaker. llvm-svn: 28574
2006-05-31 05:45:53 +08:00
X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
Hide the call to InitMCInstrInfo into tblgen generated ctor. llvm-svn: 134244
2011-07-02 01:57:27 +08:00
: X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
? X86::ADJCALLSTACKDOWN64
: X86::ADJCALLSTACKDOWN32),
(tm.getSubtarget<X86Subtarget>().is64Bit()
? X86::ADJCALLSTACKUP64
: X86::ADJCALLSTACKUP32)),
Committing X86-64 support. llvm-svn: 30177
2006-09-08 14:48:29 +08:00
TM(tm), RI(tm, *this) {
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
static const unsigned OpTbl2Addr[][3] = {
{ X86::ADC32ri, X86::ADC32mi, 0 },
{ X86::ADC32ri8, X86::ADC32mi8, 0 },
{ X86::ADC32rr, X86::ADC32mr, 0 },
{ X86::ADC64ri32, X86::ADC64mi32, 0 },
{ X86::ADC64ri8, X86::ADC64mi8, 0 },
{ X86::ADC64rr, X86::ADC64mr, 0 },
{ X86::ADD16ri, X86::ADD16mi, 0 },
{ X86::ADD16ri8, X86::ADD16mi8, 0 },
{ X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
{ X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
{ X86::ADD16rr, X86::ADD16mr, 0 },
{ X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
{ X86::ADD32ri, X86::ADD32mi, 0 },
{ X86::ADD32ri8, X86::ADD32mi8, 0 },
{ X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
{ X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
{ X86::ADD32rr, X86::ADD32mr, 0 },
{ X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
{ X86::ADD64ri32, X86::ADD64mi32, 0 },
{ X86::ADD64ri8, X86::ADD64mi8, 0 },
{ X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
{ X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
{ X86::ADD64rr, X86::ADD64mr, 0 },
{ X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
{ X86::ADD8ri, X86::ADD8mi, 0 },
{ X86::ADD8rr, X86::ADD8mr, 0 },
{ X86::AND16ri, X86::AND16mi, 0 },
{ X86::AND16ri8, X86::AND16mi8, 0 },
{ X86::AND16rr, X86::AND16mr, 0 },
{ X86::AND32ri, X86::AND32mi, 0 },
{ X86::AND32ri8, X86::AND32mi8, 0 },
{ X86::AND32rr, X86::AND32mr, 0 },
{ X86::AND64ri32, X86::AND64mi32, 0 },
{ X86::AND64ri8, X86::AND64mi8, 0 },
{ X86::AND64rr, X86::AND64mr, 0 },
{ X86::AND8ri, X86::AND8mi, 0 },
{ X86::AND8rr, X86::AND8mr, 0 },
{ X86::DEC16r, X86::DEC16m, 0 },
{ X86::DEC32r, X86::DEC32m, 0 },
{ X86::DEC64_16r, X86::DEC64_16m, 0 },
{ X86::DEC64_32r, X86::DEC64_32m, 0 },
{ X86::DEC64r, X86::DEC64m, 0 },
{ X86::DEC8r, X86::DEC8m, 0 },
{ X86::INC16r, X86::INC16m, 0 },
{ X86::INC32r, X86::INC32m, 0 },
{ X86::INC64_16r, X86::INC64_16m, 0 },
{ X86::INC64_32r, X86::INC64_32m, 0 },
{ X86::INC64r, X86::INC64m, 0 },
{ X86::INC8r, X86::INC8m, 0 },
{ X86::NEG16r, X86::NEG16m, 0 },
{ X86::NEG32r, X86::NEG32m, 0 },
{ X86::NEG64r, X86::NEG64m, 0 },
{ X86::NEG8r, X86::NEG8m, 0 },
{ X86::NOT16r, X86::NOT16m, 0 },
{ X86::NOT32r, X86::NOT32m, 0 },
{ X86::NOT64r, X86::NOT64m, 0 },
{ X86::NOT8r, X86::NOT8m, 0 },
{ X86::OR16ri, X86::OR16mi, 0 },
{ X86::OR16ri8, X86::OR16mi8, 0 },
{ X86::OR16rr, X86::OR16mr, 0 },
{ X86::OR32ri, X86::OR32mi, 0 },
{ X86::OR32ri8, X86::OR32mi8, 0 },
{ X86::OR32rr, X86::OR32mr, 0 },
{ X86::OR64ri32, X86::OR64mi32, 0 },
{ X86::OR64ri8, X86::OR64mi8, 0 },
{ X86::OR64rr, X86::OR64mr, 0 },
{ X86::OR8ri, X86::OR8mi, 0 },
{ X86::OR8rr, X86::OR8mr, 0 },
{ X86::ROL16r1, X86::ROL16m1, 0 },
{ X86::ROL16rCL, X86::ROL16mCL, 0 },
{ X86::ROL16ri, X86::ROL16mi, 0 },
{ X86::ROL32r1, X86::ROL32m1, 0 },
{ X86::ROL32rCL, X86::ROL32mCL, 0 },
{ X86::ROL32ri, X86::ROL32mi, 0 },
{ X86::ROL64r1, X86::ROL64m1, 0 },
{ X86::ROL64rCL, X86::ROL64mCL, 0 },
{ X86::ROL64ri, X86::ROL64mi, 0 },
{ X86::ROL8r1, X86::ROL8m1, 0 },
{ X86::ROL8rCL, X86::ROL8mCL, 0 },
{ X86::ROL8ri, X86::ROL8mi, 0 },
{ X86::ROR16r1, X86::ROR16m1, 0 },
{ X86::ROR16rCL, X86::ROR16mCL, 0 },
{ X86::ROR16ri, X86::ROR16mi, 0 },
{ X86::ROR32r1, X86::ROR32m1, 0 },
{ X86::ROR32rCL, X86::ROR32mCL, 0 },
{ X86::ROR32ri, X86::ROR32mi, 0 },
{ X86::ROR64r1, X86::ROR64m1, 0 },
{ X86::ROR64rCL, X86::ROR64mCL, 0 },
{ X86::ROR64ri, X86::ROR64mi, 0 },
{ X86::ROR8r1, X86::ROR8m1, 0 },
{ X86::ROR8rCL, X86::ROR8mCL, 0 },
{ X86::ROR8ri, X86::ROR8mi, 0 },
{ X86::SAR16r1, X86::SAR16m1, 0 },
{ X86::SAR16rCL, X86::SAR16mCL, 0 },
{ X86::SAR16ri, X86::SAR16mi, 0 },
{ X86::SAR32r1, X86::SAR32m1, 0 },
{ X86::SAR32rCL, X86::SAR32mCL, 0 },
{ X86::SAR32ri, X86::SAR32mi, 0 },
{ X86::SAR64r1, X86::SAR64m1, 0 },
{ X86::SAR64rCL, X86::SAR64mCL, 0 },
{ X86::SAR64ri, X86::SAR64mi, 0 },
{ X86::SAR8r1, X86::SAR8m1, 0 },
{ X86::SAR8rCL, X86::SAR8mCL, 0 },
{ X86::SAR8ri, X86::SAR8mi, 0 },
{ X86::SBB32ri, X86::SBB32mi, 0 },
{ X86::SBB32ri8, X86::SBB32mi8, 0 },
{ X86::SBB32rr, X86::SBB32mr, 0 },
{ X86::SBB64ri32, X86::SBB64mi32, 0 },
{ X86::SBB64ri8, X86::SBB64mi8, 0 },
{ X86::SBB64rr, X86::SBB64mr, 0 },
{ X86::SHL16rCL, X86::SHL16mCL, 0 },
{ X86::SHL16ri, X86::SHL16mi, 0 },
{ X86::SHL32rCL, X86::SHL32mCL, 0 },
{ X86::SHL32ri, X86::SHL32mi, 0 },
{ X86::SHL64rCL, X86::SHL64mCL, 0 },
{ X86::SHL64ri, X86::SHL64mi, 0 },
{ X86::SHL8rCL, X86::SHL8mCL, 0 },
{ X86::SHL8ri, X86::SHL8mi, 0 },
{ X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
{ X86::SHLD16rri8, X86::SHLD16mri8, 0 },
{ X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
{ X86::SHLD32rri8, X86::SHLD32mri8, 0 },
{ X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
{ X86::SHLD64rri8, X86::SHLD64mri8, 0 },
{ X86::SHR16r1, X86::SHR16m1, 0 },
{ X86::SHR16rCL, X86::SHR16mCL, 0 },
{ X86::SHR16ri, X86::SHR16mi, 0 },
{ X86::SHR32r1, X86::SHR32m1, 0 },
{ X86::SHR32rCL, X86::SHR32mCL, 0 },
{ X86::SHR32ri, X86::SHR32mi, 0 },
{ X86::SHR64r1, X86::SHR64m1, 0 },
{ X86::SHR64rCL, X86::SHR64mCL, 0 },
{ X86::SHR64ri, X86::SHR64mi, 0 },
{ X86::SHR8r1, X86::SHR8m1, 0 },
{ X86::SHR8rCL, X86::SHR8mCL, 0 },
{ X86::SHR8ri, X86::SHR8mi, 0 },
{ X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
{ X86::SHRD16rri8, X86::SHRD16mri8, 0 },
{ X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
{ X86::SHRD32rri8, X86::SHRD32mri8, 0 },
{ X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
{ X86::SHRD64rri8, X86::SHRD64mri8, 0 },
{ X86::SUB16ri, X86::SUB16mi, 0 },
{ X86::SUB16ri8, X86::SUB16mi8, 0 },
{ X86::SUB16rr, X86::SUB16mr, 0 },
{ X86::SUB32ri, X86::SUB32mi, 0 },
{ X86::SUB32ri8, X86::SUB32mi8, 0 },
{ X86::SUB32rr, X86::SUB32mr, 0 },
{ X86::SUB64ri32, X86::SUB64mi32, 0 },
{ X86::SUB64ri8, X86::SUB64mi8, 0 },
{ X86::SUB64rr, X86::SUB64mr, 0 },
{ X86::SUB8ri, X86::SUB8mi, 0 },
{ X86::SUB8rr, X86::SUB8mr, 0 },
{ X86::XOR16ri, X86::XOR16mi, 0 },
{ X86::XOR16ri8, X86::XOR16mi8, 0 },
{ X86::XOR16rr, X86::XOR16mr, 0 },
{ X86::XOR32ri, X86::XOR32mi, 0 },
{ X86::XOR32ri8, X86::XOR32mi8, 0 },
{ X86::XOR32rr, X86::XOR32mr, 0 },
{ X86::XOR64ri32, X86::XOR64mi32, 0 },
{ X86::XOR64ri8, X86::XOR64mi8, 0 },
{ X86::XOR64rr, X86::XOR64mr, 0 },
{ X86::XOR8ri, X86::XOR8mi, 0 },
{ X86::XOR8rr, X86::XOR8mr, 0 }
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
};
for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
unsigned RegOp = OpTbl2Addr[i][0];
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
unsigned MemOp = OpTbl2Addr[i][1];
unsigned Flags = OpTbl2Addr[i][2];
AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
RegOp, MemOp,
// Index 0, folded load and store, no alignment requirement.
Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
}
static const unsigned OpTbl0[][3] = {
{ X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
{ X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
{ X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
{ X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
{ X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
{ X86::WINCALL64r, X86::WINCALL64m, TB_FOLDED_LOAD },
{ X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
{ X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
{ X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
{ X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
{ X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
{ X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
{ X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
{ X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
{ X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
{ X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
{ X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
{ X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
{ X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
{ X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
{ X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
{ X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
{ X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
{ X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
{ X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
{ X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
{ X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
{ X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
{ X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
{ X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
{ X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
{ X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
{ X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
{ X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
{ X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
{ X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
{ X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
{ X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
{ X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
{ X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
{ X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
{ X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
{ X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
{ X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
{ X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
{ X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
{ X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
{ X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
{ X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
{ X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
{ X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
{ X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
{ X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
{ X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
{ X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
{ X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
{ X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
{ X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
{ X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
{ X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
{ X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
{ X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
{ X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
{ X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
{ X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
{ X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
{ X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
{ X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
{ X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
{ X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
{ X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
{ X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
{ X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
{ X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
{ X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
{ X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
{ X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
{ X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
// AVX 128-bit versions of foldable instructions
{ X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
{ X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
{ X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
{ X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
{ X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
{ X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
{ X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
{ X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
{ X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
{ X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
{ X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
{ X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
// AVX 256-bit foldable instructions
{ X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
{ X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
{ X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
{ X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
{ X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
};
for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
reapply: Use the new TB_NOT_REVERSABLE flag instead of special reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
2010-10-08 11:57:25 +08:00
unsigned RegOp = OpTbl0[i][0];
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
unsigned MemOp = OpTbl0[i][1];
unsigned Flags = OpTbl0[i][2];
AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
RegOp, MemOp, TB_INDEX_0 | Flags);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
Move load / store folding alignment require into the table(s). llvm-svn: 75749
2009-07-15 14:10:07 +08:00
static const unsigned OpTbl1[][3] = {
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
{ X86::CMP16rr, X86::CMP16rm, 0 },
{ X86::CMP32rr, X86::CMP32rm, 0 },
{ X86::CMP64rr, X86::CMP64rm, 0 },
{ X86::CMP8rr, X86::CMP8rm, 0 },
{ X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
{ X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
{ X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
{ X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
{ X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
{ X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
{ X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
{ X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
{ X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
{ X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
{ X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
{ X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
{ X86::IMUL16rri, X86::IMUL16rmi, 0 },
{ X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
{ X86::IMUL32rri, X86::IMUL32rmi, 0 },
{ X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
{ X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
{ X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
{ X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
{ X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
{ X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, TB_ALIGN_16 },
{ X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, TB_ALIGN_16 },
{ X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, TB_ALIGN_16 },
{ X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, TB_ALIGN_16 },
{ X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, TB_ALIGN_16 },
{ X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
{ X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
{ X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
{ X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
{ X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
{ X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
{ X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
{ X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
{ X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
{ X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
{ X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
{ X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
{ X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
{ X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
{ X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
{ X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
{ X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
{ X86::MOV16rr, X86::MOV16rm, 0 },
{ X86::MOV32rr, X86::MOV32rm, 0 },
{ X86::MOV64rr, X86::MOV64rm, 0 },
{ X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
{ X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
{ X86::MOV8rr, X86::MOV8rm, 0 },
{ X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
{ X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
{ X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
{ X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
{ X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
{ X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
{ X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
{ X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
{ X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
{ X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
{ X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
{ X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
{ X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
{ X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
{ X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
{ X86::MOVUPSrr, X86::MOVUPSrm, 0 },
{ X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
{ X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
{ X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
{ X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
{ X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
{ X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
{ X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
{ X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
{ X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
{ X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
{ X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
{ X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
{ X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
{ X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
{ X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
{ X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
{ X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
{ X86::RSQRTSSr, X86::RSQRTSSm, 0 },
{ X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
{ X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
{ X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 },
{ X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
{ X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 },
{ X86::SQRTSDr, X86::SQRTSDm, 0 },
{ X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
{ X86::SQRTSSr, X86::SQRTSSm, 0 },
{ X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
{ X86::TEST16rr, X86::TEST16rm, 0 },
{ X86::TEST32rr, X86::TEST32rm, 0 },
{ X86::TEST64rr, X86::TEST64rm, 0 },
{ X86::TEST8rr, X86::TEST8rm, 0 },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
{ X86::UCOMISDrr, X86::UCOMISDrm, 0 },
{ X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
// AVX 128-bit versions of foldable instructions
{ X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
{ X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
{ X86::Int_VCVTDQ2PDrr, X86::Int_VCVTDQ2PDrm, TB_ALIGN_16 },
{ X86::Int_VCVTDQ2PSrr, X86::Int_VCVTDQ2PSrm, TB_ALIGN_16 },
{ X86::Int_VCVTPD2DQrr, X86::Int_VCVTPD2DQrm, TB_ALIGN_16 },
{ X86::Int_VCVTPD2PSrr, X86::Int_VCVTPD2PSrm, TB_ALIGN_16 },
{ X86::Int_VCVTPS2DQrr, X86::Int_VCVTPS2DQrm, TB_ALIGN_16 },
{ X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm, 0 },
{ X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
{ X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
{ X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
{ X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
{ X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
{ X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
{ X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
{ X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
{ X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
{ X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
{ X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
{ X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
{ X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
{ X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
{ X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 },
{ X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
{ X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 },
{ X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
{ X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
{ X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 },
{ X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 },
{ X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 },
{ X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 },
{ X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 },
{ X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 },
{ X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 },
{ X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 },
{ X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 },
{ X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 },
{ X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 },
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
{ X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
{ X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
// AVX 256-bit foldable instructions
{ X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
{ X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
{ X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_16 },
{ X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
{ X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
};
for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
unsigned RegOp = OpTbl1[i][0];
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
unsigned MemOp = OpTbl1[i][1];
unsigned Flags = OpTbl1[i][2];
AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
RegOp, MemOp,
// Index 1, folded load
Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
Move load / store folding alignment require into the table(s). llvm-svn: 75749
2009-07-15 14:10:07 +08:00
static const unsigned OpTbl2[][3] = {
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
{ X86::ADC32rr, X86::ADC32rm, 0 },
{ X86::ADC64rr, X86::ADC64rm, 0 },
{ X86::ADD16rr, X86::ADD16rm, 0 },
{ X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
{ X86::ADD32rr, X86::ADD32rm, 0 },
{ X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
{ X86::ADD64rr, X86::ADD64rm, 0 },
{ X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
{ X86::ADD8rr, X86::ADD8rm, 0 },
{ X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
{ X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
{ X86::ADDSDrr, X86::ADDSDrm, 0 },
{ X86::ADDSSrr, X86::ADDSSrm, 0 },
{ X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
{ X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
{ X86::AND16rr, X86::AND16rm, 0 },
{ X86::AND32rr, X86::AND32rm, 0 },
{ X86::AND64rr, X86::AND64rm, 0 },
{ X86::AND8rr, X86::AND8rm, 0 },
{ X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
{ X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
{ X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
{ X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
{ X86::CMOVA16rr, X86::CMOVA16rm, 0 },
{ X86::CMOVA32rr, X86::CMOVA32rm, 0 },
{ X86::CMOVA64rr, X86::CMOVA64rm, 0 },
{ X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
{ X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
{ X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
{ X86::CMOVB16rr, X86::CMOVB16rm, 0 },
{ X86::CMOVB32rr, X86::CMOVB32rm, 0 },
{ X86::CMOVB64rr, X86::CMOVB64rm, 0 },
{ X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
{ X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
{ X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
{ X86::CMOVE16rr, X86::CMOVE16rm, 0 },
{ X86::CMOVE32rr, X86::CMOVE32rm, 0 },
{ X86::CMOVE64rr, X86::CMOVE64rm, 0 },
{ X86::CMOVG16rr, X86::CMOVG16rm, 0 },
{ X86::CMOVG32rr, X86::CMOVG32rm, 0 },
{ X86::CMOVG64rr, X86::CMOVG64rm, 0 },
{ X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
{ X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
{ X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
{ X86::CMOVL16rr, X86::CMOVL16rm, 0 },
{ X86::CMOVL32rr, X86::CMOVL32rm, 0 },
{ X86::CMOVL64rr, X86::CMOVL64rm, 0 },
{ X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
{ X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
{ X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
{ X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
{ X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
{ X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
{ X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
{ X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
{ X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
{ X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
{ X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
{ X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
{ X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
{ X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
{ X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
{ X86::CMOVO16rr, X86::CMOVO16rm, 0 },
{ X86::CMOVO32rr, X86::CMOVO32rm, 0 },
{ X86::CMOVO64rr, X86::CMOVO64rm, 0 },
{ X86::CMOVP16rr, X86::CMOVP16rm, 0 },
{ X86::CMOVP32rr, X86::CMOVP32rm, 0 },
{ X86::CMOVP64rr, X86::CMOVP64rm, 0 },
{ X86::CMOVS16rr, X86::CMOVS16rm, 0 },
{ X86::CMOVS32rr, X86::CMOVS32rm, 0 },
{ X86::CMOVS64rr, X86::CMOVS64rm, 0 },
{ X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
{ X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
{ X86::CMPSDrr, X86::CMPSDrm, 0 },
{ X86::CMPSSrr, X86::CMPSSrm, 0 },
{ X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
{ X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
{ X86::DIVSDrr, X86::DIVSDrm, 0 },
{ X86::DIVSSrr, X86::DIVSSrm, 0 },
{ X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
{ X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
{ X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
{ X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
{ X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
{ X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
{ X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
{ X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
{ X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
{ X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
{ X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
{ X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
{ X86::IMUL16rr, X86::IMUL16rm, 0 },
{ X86::IMUL32rr, X86::IMUL32rm, 0 },
{ X86::IMUL64rr, X86::IMUL64rm, 0 },
{ X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
{ X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
{ X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
{ X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 },
{ X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
{ X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 },
{ X86::MAXSDrr, X86::MAXSDrm, 0 },
{ X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
{ X86::MAXSSrr, X86::MAXSSrm, 0 },
{ X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
{ X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
{ X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 },
{ X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
{ X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 },
{ X86::MINSDrr, X86::MINSDrm, 0 },
{ X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
{ X86::MINSSrr, X86::MINSSrm, 0 },
{ X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
{ X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
{ X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
{ X86::MULSDrr, X86::MULSDrm, 0 },
{ X86::MULSSrr, X86::MULSSrm, 0 },
{ X86::OR16rr, X86::OR16rm, 0 },
{ X86::OR32rr, X86::OR32rm, 0 },
{ X86::OR64rr, X86::OR64rm, 0 },
{ X86::OR8rr, X86::OR8rm, 0 },
{ X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
{ X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
{ X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
{ X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
{ X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
{ X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
{ X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
{ X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
{ X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
{ X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
{ X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
{ X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
{ X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
{ X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
{ X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
{ X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
{ X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
{ X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
{ X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
{ X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
{ X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
{ X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
{ X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
{ X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
{ X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
{ X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
{ X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
{ X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
{ X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
{ X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
{ X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
{ X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
{ X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
{ X86::PORrr, X86::PORrm, TB_ALIGN_16 },
{ X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
{ X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
{ X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
{ X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
{ X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
{ X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
{ X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
{ X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
{ X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
{ X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
{ X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
{ X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
{ X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
{ X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
{ X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
{ X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
{ X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
{ X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
{ X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
{ X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
{ X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
{ X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
{ X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
{ X86::SBB32rr, X86::SBB32rm, 0 },
{ X86::SBB64rr, X86::SBB64rm, 0 },
{ X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
{ X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
{ X86::SUB16rr, X86::SUB16rm, 0 },
{ X86::SUB32rr, X86::SUB32rm, 0 },
{ X86::SUB64rr, X86::SUB64rm, 0 },
{ X86::SUB8rr, X86::SUB8rm, 0 },
{ X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
{ X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
{ X86::SUBSDrr, X86::SUBSDrm, 0 },
{ X86::SUBSSrr, X86::SUBSSrm, 0 },
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// FIXME: TEST*rr -> swapped operand of TEST*mr.
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
{ X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
{ X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
{ X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
{ X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
{ X86::XOR16rr, X86::XOR16rm, 0 },
{ X86::XOR32rr, X86::XOR32rm, 0 },
{ X86::XOR64rr, X86::XOR64rm, 0 },
{ X86::XOR8rr, X86::XOR8rm, 0 },
{ X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
{ X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
// AVX 128-bit versions of foldable instructions
{ X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
{ X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
{ X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
{ X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
{ X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
{ X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
{ X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
{ X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
{ X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
{ X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
{ X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
{ X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
{ X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
{ X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm, 0 },
{ X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
{ X86::Int_VCVTTSD2SIrr, X86::Int_VCVTTSD2SIrm, 0 },
{ X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
{ X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm, 0 },
{ X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
{ X86::Int_VCVTTSS2SIrr, X86::Int_VCVTTSS2SIrm, 0 },
{ X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
{ X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
{ X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, TB_ALIGN_16 },
{ X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 },
{ X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
{ X86::VSQRTSDr, X86::VSQRTSDm, 0 },
{ X86::VSQRTSSr, X86::VSQRTSSm, 0 },
{ X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 },
{ X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 },
{ X86::VADDSDrr, X86::VADDSDrm, 0 },
{ X86::VADDSSrr, X86::VADDSSrm, 0 },
{ X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 },
{ X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 },
{ X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 },
{ X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 },
{ X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 },
{ X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 },
{ X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 },
{ X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 },
{ X86::VCMPSDrr, X86::VCMPSDrm, 0 },
{ X86::VCMPSSrr, X86::VCMPSSrm, 0 },
{ X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 },
{ X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 },
{ X86::VDIVSDrr, X86::VDIVSDrm, 0 },
{ X86::VDIVSSrr, X86::VDIVSSrm, 0 },
{ X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
{ X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
{ X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
{ X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
{ X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
{ X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
{ X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
{ X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
{ X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 },
{ X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 },
{ X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 },
{ X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 },
{ X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
{ X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
{ X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 },
{ X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 },
{ X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 },
{ X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 },
{ X86::VMAXSDrr, X86::VMAXSDrm, 0 },
{ X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
{ X86::VMAXSSrr, X86::VMAXSSrm, 0 },
{ X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
{ X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 },
{ X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 },
{ X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 },
{ X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 },
{ X86::VMINSDrr, X86::VMINSDrm, 0 },
{ X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
{ X86::VMINSSrr, X86::VMINSSrm, 0 },
{ X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
{ X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 },
{ X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 },
{ X86::VMULSDrr, X86::VMULSDrm, 0 },
{ X86::VMULSSrr, X86::VMULSSrm, 0 },
{ X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 },
{ X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 },
{ X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 },
{ X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 },
{ X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 },
{ X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 },
{ X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 },
{ X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 },
{ X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 },
{ X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 },
{ X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 },
{ X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 },
{ X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 },
{ X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 },
{ X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 },
{ X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 },
{ X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 },
{ X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 },
{ X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 },
{ X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 },
{ X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 },
{ X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 },
{ X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 },
{ X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 },
{ X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 },
{ X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 },
{ X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 },
{ X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 },
{ X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 },
{ X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 },
{ X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 },
{ X86::VPORrr, X86::VPORrm, TB_ALIGN_16 },
{ X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 },
{ X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 },
{ X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 },
{ X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 },
{ X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 },
{ X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 },
{ X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 },
{ X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 },
{ X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 },
{ X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 },
{ X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 },
{ X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 },
{ X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 },
{ X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 },
{ X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 },
{ X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 },
{ X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 },
{ X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 },
{ X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 },
{ X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 },
{ X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 },
{ X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 },
{ X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 },
{ X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 },
{ X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 },
{ X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 },
{ X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 },
{ X86::VSUBSDrr, X86::VSUBSDrm, 0 },
{ X86::VSUBSSrr, X86::VSUBSSrm, 0 },
{ X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 },
{ X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 },
{ X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 },
{ X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 },
{ X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 },
{ X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 }
// FIXME: add AVX 256-bit foldable instructions
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
};
for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
unsigned RegOp = OpTbl2[i][0];
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
unsigned MemOp = OpTbl2[i][1];
unsigned Flags = OpTbl2[i][2];
AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
RegOp, MemOp,
// Index 2, folded load
Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
}
}
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
void
X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
MemOp2RegOpTableType &M2RTable,
unsigned RegOp, unsigned MemOp, unsigned Flags) {
if ((Flags & TB_NO_FORWARD) == 0) {
assert(!R2MTable.count(RegOp) && "Duplicate entry!");
R2MTable[RegOp] = std::make_pair(MemOp, Flags);
}
if ((Flags & TB_NO_REVERSE) == 0) {
assert(!M2RTable.count(MemOp) &&
reapply the patch reverted in r116033: "Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'" With a critical fix: the add pseudos clobber EFLAGS. llvm-svn: 116039
2010-10-08 11:54:52 +08:00
"Duplicated entries in unfolding maps?");
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
M2RTable[MemOp] = std::make_pair(RegOp, Flags);
}
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284
2002-10-26 06:55:53 +08:00
}
Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified instruction is copy like where the source and destination registers can overlap. This is to be used by the coalescable to coalesce the source and destination registers of instructions like X86::MOVSX64rr32. Apparently some crazy people believe the coalescer is too simple. llvm-svn: 93210
2010-01-12 08:09:37 +08:00
bool
Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg. For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used. llvm-svn: 93278
2010-01-13 08:30:23 +08:00
X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SubIdx) const {
Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified instruction is copy like where the source and destination registers can overlap. This is to be used by the coalescable to coalesce the source and destination registers of instructions like X86::MOVSX64rr32. Apparently some crazy people believe the coalescer is too simple. llvm-svn: 93210
2010-01-12 08:09:37 +08:00
switch (MI.getOpcode()) {
default: break;
case X86::MOVSX16rr8:
case X86::MOVZX16rr8:
case X86::MOVSX32rr8:
case X86::MOVZX32rr8:
case X86::MOVSX64rr8:
case X86::MOVZX64rr8:
For now, avoid issuing extract_subreg to reuse lower 8-bit, it's not safe in 32-bit. llvm-svn: 93307
2010-01-13 16:01:32 +08:00
if (!TM.getSubtarget<X86Subtarget>().is64Bit())
// It's not always legal to reference the low 8-bit of the larger
// register in 32-bit mode.
return false;
Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified instruction is copy like where the source and destination registers can overlap. This is to be used by the coalescable to coalesce the source and destination registers of instructions like X86::MOVSX64rr32. Apparently some crazy people believe the coalescer is too simple. llvm-svn: 93210
2010-01-12 08:09:37 +08:00
case X86::MOVSX32rr16:
case X86::MOVZX32rr16:
case X86::MOVSX64rr16:
case X86::MOVZX64rr16:
case X86::MOVSX64rr32:
case X86::MOVZX64rr32: {
if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
// Be conservative.
return false;
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
switch (MI.getOpcode()) {
default:
llvm_unreachable(0);
break;
case X86::MOVSX16rr8:
case X86::MOVZX16rr8:
case X86::MOVSX32rr8:
case X86::MOVZX32rr8:
case X86::MOVSX64rr8:
case X86::MOVZX64rr8:
Use enums instead of literals for X86 subregisters. The cases in getMatchingSuperRegClass cannot be broken up until the enums have unique values. llvm-svn: 104611
2010-05-26 01:04:16 +08:00
SubIdx = X86::sub_8bit;
Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified instruction is copy like where the source and destination registers can overlap. This is to be used by the coalescable to coalesce the source and destination registers of instructions like X86::MOVSX64rr32. Apparently some crazy people believe the coalescer is too simple. llvm-svn: 93210
2010-01-12 08:09:37 +08:00
break;
case X86::MOVSX32rr16:
case X86::MOVZX32rr16:
case X86::MOVSX64rr16:
case X86::MOVZX64rr16:
Use enums instead of literals for X86 subregisters. The cases in getMatchingSuperRegClass cannot be broken up until the enums have unique values. llvm-svn: 104611
2010-05-26 01:04:16 +08:00
SubIdx = X86::sub_16bit;
Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified instruction is copy like where the source and destination registers can overlap. This is to be used by the coalescable to coalesce the source and destination registers of instructions like X86::MOVSX64rr32. Apparently some crazy people believe the coalescer is too simple. llvm-svn: 93210
2010-01-12 08:09:37 +08:00
break;
case X86::MOVSX64rr32:
case X86::MOVZX64rr32:
Use enums instead of literals for X86 subregisters. The cases in getMatchingSuperRegClass cannot be broken up until the enums have unique values. llvm-svn: 104611
2010-05-26 01:04:16 +08:00
SubIdx = X86::sub_32bit;
Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified instruction is copy like where the source and destination registers can overlap. This is to be used by the coalescable to coalesce the source and destination registers of instructions like X86::MOVSX64rr32. Apparently some crazy people believe the coalescer is too simple. llvm-svn: 93210
2010-01-12 08:09:37 +08:00
break;
}
Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg. For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used. llvm-svn: 93278
2010-01-13 08:30:23 +08:00
return true;
Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified instruction is copy like where the source and destination registers can overlap. This is to be used by the coalescable to coalesce the source and destination registers of instructions like X86::MOVSX64rr32. Apparently some crazy people believe the coalescer is too simple. llvm-svn: 93210
2010-01-12 08:09:37 +08:00
}
}
Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg. For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used. llvm-svn: 93278
2010-01-13 08:30:23 +08:00
return false;
Add TargetInstrInfo::isCoalescableInstr. It returns true if the specified instruction is copy like where the source and destination registers can overlap. This is to be used by the coalescable to coalesce the source and destination registers of instructions like X86::MOVSX64rr32. Apparently some crazy people believe the coalescer is too simple. llvm-svn: 93210
2010-01-12 08:09:37 +08:00
}
Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a machine instruction loads or stores from/to a stack slot. Unlike isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be something other than a pure load/store (e.g. it may be an arithmetic operation with a memory operand). This helps AsmPrinter determine when to print a spill/reload comment. This is only a hint since we may not be able to figure this out in all cases. As such, it should not be relied upon for correctness. Implement for X86. Return false by default for other architectures. llvm-svn: 87026
2009-11-13 04:55:29 +08:00
/// isFrameOperand - Return true and the FrameIndex if the specified
/// operand and follow operands form a reference to the stack frame.
bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
int &FrameIndex) const {
if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
MI->getOperand(Op+1).getImm() == 1 &&
MI->getOperand(Op+2).getReg() == 0 &&
MI->getOperand(Op+3).getImm() == 0) {
FrameIndex = MI->getOperand(Op).getIndex();
return true;
}
return false;
}
Fix a bootstrap failure. Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE interfaces to explicitly request checking for post-frame ptr elimination operands. This uses a heuristic so it isn't reliable for correctness. llvm-svn: 87047
2009-11-13 08:29:53 +08:00
static bool isFrameLoadOpcode(int Opcode) {
switch (Opcode) {
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
default: break;
case X86::MOV8rm:
case X86::MOV16rm:
case X86::MOV32rm:
Committing X86-64 support. llvm-svn: 30177
2006-09-08 14:48:29 +08:00
case X86::MOV64rm:
Refactor X87 instructions. As a side effect, all their names are changed. llvm-svn: 37876
2007-07-05 05:07:47 +08:00
case X86::LD_Fp64m:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
case X86::MOVSSrm:
case X86::MOVSDrm:
Teach the codegen about instructions used for SSE spill code, allowing it to optimize cases where it has to spill a lot llvm-svn: 27801
2006-04-19 00:44:51 +08:00
case X86::MOVAPSrm:
case X86::MOVAPDrm:
Add load-folding table entries for MOVDQA. llvm-svn: 61972
2009-01-09 10:40:34 +08:00
case X86::MOVDQArm:
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
case X86::VMOVSSrm:
case X86::VMOVSDrm:
case X86::VMOVAPSrm:
case X86::VMOVAPDrm:
case X86::VMOVDQArm:
Add 256-bit load/store recognition and matching in several places. llvm-svn: 135171
2011-07-15 02:50:58 +08:00
case X86::VMOVAPSYrm:
case X86::VMOVAPDYrm:
case X86::VMOVDQAYrm:
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. llvm-svn: 35616
2007-04-03 14:00:37 +08:00
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
Fix a bootstrap failure. Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE interfaces to explicitly request checking for post-frame ptr elimination operands. This uses a heuristic so it isn't reliable for correctness. llvm-svn: 87047
2009-11-13 08:29:53 +08:00
return true;
break;
}
return false;
}
static bool isFrameStoreOpcode(int Opcode) {
switch (Opcode) {
default: break;
case X86::MOV8mr:
case X86::MOV16mr:
case X86::MOV32mr:
case X86::MOV64mr:
case X86::ST_FpP64m:
case X86::MOVSSmr:
case X86::MOVSDmr:
case X86::MOVAPSmr:
case X86::MOVAPDmr:
case X86::MOVDQAmr:
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
case X86::VMOVSSmr:
case X86::VMOVSDmr:
case X86::VMOVAPSmr:
case X86::VMOVAPDmr:
case X86::VMOVDQAmr:
Add 256-bit load/store recognition and matching in several places. llvm-svn: 135171
2011-07-15 02:50:58 +08:00
case X86::VMOVAPSYmr:
case X86::VMOVAPDYmr:
case X86::VMOVDQAYmr:
Fix a bootstrap failure. Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE interfaces to explicitly request checking for post-frame ptr elimination operands. This uses a heuristic so it isn't reliable for correctness. llvm-svn: 87047
2009-11-13 08:29:53 +08:00
case X86::MMX_MOVD64mr:
case X86::MMX_MOVQ64mr:
case X86::MMX_MOVNTQmr:
return true;
}
return false;
}
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
Fix a bootstrap failure. Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE interfaces to explicitly request checking for post-frame ptr elimination operands. This uses a heuristic so it isn't reliable for correctness. llvm-svn: 87047
2009-11-13 08:29:53 +08:00
int &FrameIndex) const {
if (isFrameLoadOpcode(MI->getOpcode()))
The isLoadFromStackSlot and isStoreToStackSlot have no way of reporting subregister operands like this: %reg1040:sub_32bit<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0, %reg1040<imp-def>; mem:LD4[FixedStack-2](align=8) Make them return false when subreg operands are present. VirtRegRewriter is making bad assumptions otherwise. This fixes PR7713. llvm-svn: 109489
2010-07-27 12:17:01 +08:00
if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
return MI->getOperand(0).getReg();
Fix a bootstrap failure. Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE interfaces to explicitly request checking for post-frame ptr elimination operands. This uses a heuristic so it isn't reliable for correctness. llvm-svn: 87047
2009-11-13 08:29:53 +08:00
return 0;
}
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
Fix a bootstrap failure. Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE interfaces to explicitly request checking for post-frame ptr elimination operands. This uses a heuristic so it isn't reliable for correctness. llvm-svn: 87047
2009-11-13 08:29:53 +08:00
int &FrameIndex) const {
if (isFrameLoadOpcode(MI->getOpcode())) {
unsigned Reg;
if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
return Reg;
Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a machine instruction loads or stores from/to a stack slot. Unlike isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be something other than a pure load/store (e.g. it may be an arithmetic operation with a memory operand). This helps AsmPrinter determine when to print a spill/reload comment. This is only a hint since we may not be able to figure this out in all cases. As such, it should not be relied upon for correctness. Implement for X86. Return false by default for other architectures. llvm-svn: 87026
2009-11-13 04:55:29 +08:00
// Check for post-frame index elimination operations
Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand. llvm-svn: 90608
2009-12-05 06:38:46 +08:00
const MachineMemOperand *Dummy;
return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
}
return 0;
}
Add more const qualifiers. This fixes build breakage from r59540. llvm-svn: 59542
2008-11-19 03:49:32 +08:00
unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
int &FrameIndex) const {
Fix a bootstrap failure. Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE interfaces to explicitly request checking for post-frame ptr elimination operands. This uses a heuristic so it isn't reliable for correctness. llvm-svn: 87047
2009-11-13 08:29:53 +08:00
if (isFrameStoreOpcode(MI->getOpcode()))
The isLoadFromStackSlot and isStoreToStackSlot have no way of reporting subregister operands like this: %reg1040:sub_32bit<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0, %reg1040<imp-def>; mem:LD4[FixedStack-2](align=8) Make them return false when subreg operands are present. VirtRegRewriter is making bad assumptions otherwise. This fixes PR7713. llvm-svn: 109489
2010-07-27 12:17:01 +08:00
if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
isFrameOperand(MI, 0, FrameIndex))
add some long-overdue enums to refer to the parts of the 5-operand X86 memory operand. llvm-svn: 107925
2010-07-09 06:41:28 +08:00
return MI->getOperand(X86::AddrNumOperands).getReg();
Fix a bootstrap failure. Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE interfaces to explicitly request checking for post-frame ptr elimination operands. This uses a heuristic so it isn't reliable for correctness. llvm-svn: 87047
2009-11-13 08:29:53 +08:00
return 0;
}
unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
int &FrameIndex) const {
if (isFrameStoreOpcode(MI->getOpcode())) {
unsigned Reg;
if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
return Reg;
Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a machine instruction loads or stores from/to a stack slot. Unlike isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be something other than a pure load/store (e.g. it may be an arithmetic operation with a memory operand). This helps AsmPrinter determine when to print a spill/reload comment. This is only a hint since we may not be able to figure this out in all cases. As such, it should not be relied upon for correctness. Implement for X86. Return false by default for other architectures. llvm-svn: 87026
2009-11-13 04:55:29 +08:00
// Check for post-frame index elimination operations
Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand. llvm-svn: 90608
2009-12-05 06:38:46 +08:00
const MachineMemOperand *Dummy;
return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
2006-02-03 04:12:32 +08:00
}
return 0;
}
Code clean up. llvm-svn: 48856
2008-03-27 09:45:11 +08:00
/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
/// X86::MOVPC32r.
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Code clean up. llvm-svn: 48856
2008-03-27 09:45:11 +08:00
bool isPICBase = false;
for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
E = MRI.def_end(); I != E; ++I) {
MachineInstr *DefMI = I.getOperand().getParent();
if (DefMI->getOpcode() != X86::MOVPC32r)
return false;
assert(!isPICBase && "More than one PIC base?");
isPICBase = true;
}
return isPICBase;
}
Re-apply 48911. llvm-svn: 48977
2008-03-31 15:54:19 +08:00
Constify the machine instruction passed into the "is{Trivially,Really}ReMaterializable" methods. llvm-svn: 51001
2008-05-13 04:54:26 +08:00
bool
Replace X86's CanRematLoadWithDispOperand by calling the target-independent MachineInstr::isInvariantLoad instead, which has the benefit of being more complete. llvm-svn: 83696
2009-10-10 08:34:18 +08:00
X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
AliasAnalysis *AA) const {
Add a target hook to allow loads from constant pools to be rematerialized, and an implementation for x86. llvm-svn: 37576
2007-06-15 04:50:44 +08:00
switch (MI->getOpcode()) {
default: break;
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
case X86::MOV8rm:
case X86::MOV16rm:
case X86::MOV32rm:
case X86::MOV64rm:
case X86::LD_Fp64m:
case X86::MOVSSrm:
case X86::MOVSDrm:
case X86::MOVAPSrm:
- Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. - Mark MOVUPSrm re-materializable. llvm-svn: 88974
2009-11-17 05:56:03 +08:00
case X86::MOVUPSrm:
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
case X86::MOVAPDrm:
Add load-folding table entries for MOVDQA. llvm-svn: 61972
2009-01-09 10:40:34 +08:00
case X86::MOVDQArm:
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
case X86::VMOVSSrm:
case X86::VMOVSDrm:
case X86::VMOVAPSrm:
case X86::VMOVUPSrm:
case X86::VMOVAPDrm:
case X86::VMOVDQArm:
Add 256-bit load/store recognition and matching in several places. llvm-svn: 135171
2011-07-15 02:50:58 +08:00
case X86::VMOVAPSYrm:
case X86::VMOVUPSYrm:
case X86::VMOVAPDYrm:
case X86::VMOVDQAYrm:
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
case X86::MMX_MOVD64rm:
Re-apply 89011. It's not to be blamed. llvm-svn: 89081
2009-11-17 17:51:18 +08:00
case X86::MMX_MOVQ64rm:
Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use it! llvm-svn: 139063
2011-09-03 08:46:45 +08:00
case X86::FsVMOVAPSrm:
case X86::FsVMOVAPDrm:
Re-apply 89011. It's not to be blamed. llvm-svn: 89081
2009-11-17 17:51:18 +08:00
case X86::FsMOVAPSrm:
case X86::FsMOVAPDrm: {
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
// Loads from constant pools are trivially rematerializable.
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MI->getOperand(1).isReg() &&
MI->getOperand(2).isImm() &&
MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
Replace X86's CanRematLoadWithDispOperand by calling the target-independent MachineInstr::isInvariantLoad instead, which has the benefit of being more complete. llvm-svn: 83696
2009-10-10 08:34:18 +08:00
MI->isInvariantLoad(AA)) {
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
unsigned BaseReg = MI->getOperand(1).getReg();
Reimplement rip-relative addressing in the X86-64 backend. The new implementation primarily differs from the former in that the asmprinter doesn't make a zillion decisions about whether or not something will be RIP relative or not. Instead, those decisions are made by isel lowering and propagated through to the asm printer. To achieve this, we: 1. Represent RIP relative addresses by setting the base of the X86 addr mode to X86::RIP. 2. When ISel Lowering decides that it is safe to use RIP, it lowers to X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to X86ISD::Wrapper as before. 3. This removes isRIPRel from X86ISelAddressMode, representing it with a basereg of RIP instead. 4. The addressing mode matching logic in isel is greatly simplified. 5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate passed through various printoperand routines is gone now. 6. The various symbol printing routines in asmprinter now no longer infer when to emit (%rip), they just print the symbol. I think this is a big improvement over the previous situation. It does have two small caveats though: 1. I implemented a horrible "no-rip" modifier for the inline asm "P" constraint modifier. This is a short term hack, there is a much better, but more involved, solution. 2. I had to xfail an -aggressive-remat testcase because it isn't handling the use of RIP in the constant-pool reading instruction. This specific test is easy to fix without -aggressive-remat, which I intend to do next. llvm-svn: 74372
2009-06-27 12:16:01 +08:00
if (BaseReg == 0 || BaseReg == X86::RIP)
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
return true;
// Allow re-materialization of PIC load.
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now. llvm-svn: 49059
2008-04-02 07:26:12 +08:00
return false;
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
const MachineFunction &MF = *MI->getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
bool isPICBase = false;
for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
E = MRI.def_end(); I != E; ++I) {
MachineInstr *DefMI = I.getOperand().getParent();
if (DefMI->getOpcode() != X86::MOVPC32r)
return false;
assert(!isPICBase && "More than one PIC base?");
isPICBase = true;
}
return isPICBase;
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
}
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
return false;
Allow re-materialization of pic load (controlled by -remat-pic-load for now). llvm-svn: 47476
2008-02-22 17:25:47 +08:00
}
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
case X86::LEA32r:
case X86::LEA64r: {
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MI->getOperand(2).isImm() &&
MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
!MI->getOperand(4).isReg()) {
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
// lea fi#, lea GV, etc. are all rematerializable.
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (!MI->getOperand(1).isReg())
Mark lea fi# as being really rematerializable. llvm-svn: 56698
2008-09-27 05:30:20 +08:00
return true;
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
unsigned BaseReg = MI->getOperand(1).getReg();
if (BaseReg == 0)
return true;
// Allow re-materialization of lea PICBase + x.
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
const MachineFunction &MF = *MI->getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
Code clean up. llvm-svn: 48856
2008-03-27 09:45:11 +08:00
return regIsPICBase(BaseReg, MRI);
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
}
return false;
}
Add a target hook to allow loads from constant pools to be rematerialized, and an implementation for x86. llvm-svn: 37576
2007-06-15 04:50:44 +08:00
}
Allow certain lea instructions to be rematerialized. llvm-svn: 48855
2008-03-27 09:41:09 +08:00
Revert the earlier change that removed the M_REMATERIALIZABLE machine instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
2007-06-26 08:48:07 +08:00
// All other instructions marked M_REMATERIALIZABLE are always trivially
// rematerializable.
return true;
Add a target hook to allow loads from constant pools to be rematerialized, and an implementation for x86. llvm-svn: 37576
2007-06-15 04:50:44 +08:00
}
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
/// would clobber the EFLAGS condition register. Note the result may be
/// conservative. If it cannot definitely determine the safety after visiting
Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards (for uses marked kill and defs marked dead) a few instructions in addition to forwards. Also, increase the maximum number of instructions to scan, as it appears to help in a fair number of cases. llvm-svn: 84061
2009-10-14 08:08:59 +08:00
/// a few instructions in each direction it assumes it's not safe.
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) {
Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically? llvm-svn: 99320
2010-03-24 04:35:45 +08:00
MachineBasicBlock::iterator E = MBB.end();
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
// For compile time consideration, if we are not able to determine the
Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards (for uses marked kill and defs marked dead) a few instructions in addition to forwards. Also, increase the maximum number of instructions to scan, as it appears to help in a fair number of cases. llvm-svn: 84061
2009-10-14 08:08:59 +08:00
// safety after visiting 4 instructions in each direction, we will assume
// it's not safe.
MachineBasicBlock::iterator Iter = I;
Check for EFLAGS live-out before clobbering it. It is only allowed to clobber EFLAGS at the end of a block if it isn't live-in to any successor. llvm-svn: 139056
2011-09-03 07:52:52 +08:00
for (unsigned i = 0; Iter != E && i < 4; ++i) {
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
bool SeenDef = false;
Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards (for uses marked kill and defs marked dead) a few instructions in addition to forwards. Also, increase the maximum number of instructions to scan, as it appears to help in a fair number of cases. llvm-svn: 84061
2009-10-14 08:08:59 +08:00
for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
MachineOperand &MO = Iter->getOperand(j);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (!MO.isReg())
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
continue;
if (MO.getReg() == X86::EFLAGS) {
if (MO.isUse())
return false;
SeenDef = true;
}
}
if (SeenDef)
// This instruction defines EFLAGS, no need to look any further.
return true;
Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards (for uses marked kill and defs marked dead) a few instructions in addition to forwards. Also, increase the maximum number of instructions to scan, as it appears to help in a fair number of cases. llvm-svn: 84061
2009-10-14 08:08:59 +08:00
++Iter;
Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically? llvm-svn: 99320
2010-03-24 04:35:45 +08:00
// Skip over DBG_VALUE.
while (Iter != E && Iter->isDebugValue())
++Iter;
Check for EFLAGS live-out before clobbering it. It is only allowed to clobber EFLAGS at the end of a block if it isn't live-in to any successor. llvm-svn: 139056
2011-09-03 07:52:52 +08:00
}
When the coalescer is doing rematerializing, have it remove the copy instruction from the instruction list before asking the target to create the new instruction. This gets the old instruction out of the way so that it doesn't interfere with the target's rematerialization code. In the case of x86, this helps it find more cases where EFLAGS is not live. Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check to see if it reached the end of the block after scanning each instruction, instead of just before. This lets it notice when the end of the block is only two instructions away, without doing any additional scanning. These changes allow rematerialization to clobber EFLAGS in more cases, for example using xor instead of mov to set the return value to zero in the included testcase. llvm-svn: 57872
2008-10-21 11:24:31 +08:00
Check for EFLAGS live-out before clobbering it. It is only allowed to clobber EFLAGS at the end of a block if it isn't live-in to any successor. llvm-svn: 139056
2011-09-03 07:52:52 +08:00
// It is safe to clobber EFLAGS at the end of a block of no successor has it
// live in.
if (Iter == E) {
for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
SE = MBB.succ_end(); SI != SE; ++SI)
if ((*SI)->isLiveIn(X86::EFLAGS))
return false;
return true;
Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards (for uses marked kill and defs marked dead) a few instructions in addition to forwards. Also, increase the maximum number of instructions to scan, as it appears to help in a fair number of cases. llvm-svn: 84061
2009-10-14 08:08:59 +08:00
}
Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically? llvm-svn: 99320
2010-03-24 04:35:45 +08:00
MachineBasicBlock::iterator B = MBB.begin();
Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards (for uses marked kill and defs marked dead) a few instructions in addition to forwards. Also, increase the maximum number of instructions to scan, as it appears to help in a fair number of cases. llvm-svn: 84061
2009-10-14 08:08:59 +08:00
Iter = I;
for (unsigned i = 0; i < 4; ++i) {
// If we make it to the beginning of the block, it's safe to clobber
// EFLAGS iff EFLAGS is not live-in.
Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically? llvm-svn: 99320
2010-03-24 04:35:45 +08:00
if (Iter == B)
Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards (for uses marked kill and defs marked dead) a few instructions in addition to forwards. Also, increase the maximum number of instructions to scan, as it appears to help in a fair number of cases. llvm-svn: 84061
2009-10-14 08:08:59 +08:00
return !MBB.isLiveIn(X86::EFLAGS);
--Iter;
Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically? llvm-svn: 99320
2010-03-24 04:35:45 +08:00
// Skip over DBG_VALUE.
while (Iter != B && Iter->isDebugValue())
--Iter;
Make isSafeToClobberEFLAGS more aggressive. Teach it to scan backwards (for uses marked kill and defs marked dead) a few instructions in addition to forwards. Also, increase the maximum number of instructions to scan, as it appears to help in a fair number of cases. llvm-svn: 84061
2009-10-14 08:08:59 +08:00
bool SawKill = false;
for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
MachineOperand &MO = Iter->getOperand(j);
if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
if (MO.isDef()) return MO.isDead();
if (MO.isKill()) SawKill = true;
}
}
if (SawKill)
// This instruction kills EFLAGS and doesn't redefine it, so
// there's no need to look further.
When the coalescer is doing rematerializing, have it remove the copy instruction from the instruction list before asking the target to create the new instruction. This gets the old instruction out of the way so that it doesn't interfere with the target's rematerialization code. In the case of x86, this helps it find more cases where EFLAGS is not live. Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check to see if it reached the end of the block after scanning each instruction, instead of just before. This lets it notice when the end of the block is only two instructions away, without doing any additional scanning. These changes allow rematerialization to clobber EFLAGS in more cases, for example using xor instead of mov to set the return value to zero in the included testcase. llvm-svn: 57872
2008-10-21 11:24:31 +08:00
return true;
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
}
// Conservative answer.
return false;
}
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Let callers decide the sub-register index on the def operand of rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
2009-07-16 17:20:10 +08:00
unsigned DestReg, unsigned SubIdx,
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. - If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. llvm-svn: 88745
2009-11-14 10:55:43 +08:00
const MachineInstr *Orig,
Slightly change the meaning of the reMaterialize target hook when the original instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
2010-06-03 06:47:25 +08:00
const TargetRegisterInfo &TRI) const {
When rematerializing, use the debug location of the original instruction, rather than a location near where the new instruction is being inserted. llvm-svn: 103232
2010-05-07 09:28:10 +08:00
DebugLoc DL = Orig->getDebugLoc();
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
// MOV32r0 etc. are implemented with xor which clobbers condition code.
// Re-materialize them as movri instructions to avoid side effects.
Let callers decide the sub-register index on the def operand of rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
2009-07-16 17:20:10 +08:00
bool Clone = true;
unsigned Opc = Orig->getOpcode();
switch (Opc) {
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
default: break;
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
case X86::MOV8r0:
Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. llvm-svn: 93229
2010-01-12 12:42:54 +08:00
case X86::MOV16r0:
case X86::MOV32r0:
case X86::MOV64r0: {
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
if (!isSafeToClobberEFLAGS(MBB, I)) {
Let callers decide the sub-register index on the def operand of rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
2009-07-16 17:20:10 +08:00
switch (Opc) {
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
default: break;
case X86::MOV8r0: Opc = X86::MOV8ri; break;
Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. llvm-svn: 93229
2010-01-12 12:42:54 +08:00
case X86::MOV16r0: Opc = X86::MOV16ri; break;
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
case X86::MOV32r0: Opc = X86::MOV32ri; break;
movl is a cheaper way to materialize 0 without clobbering EFLAGS than movabsq. llvm-svn: 97227
2010-02-27 00:49:27 +08:00
case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
}
Let callers decide the sub-register index on the def operand of rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
2009-07-16 17:20:10 +08:00
Clone = false;
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
}
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
break;
If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. llvm-svn: 52670
2008-06-24 15:10:51 +08:00
}
}
Let callers decide the sub-register index on the def operand of rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
2009-07-16 17:20:10 +08:00
if (Clone) {
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
MBB.insert(I, MI);
Let callers decide the sub-register index on the def operand of rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
2009-07-16 17:20:10 +08:00
} else {
Slightly change the meaning of the reMaterialize target hook when the original instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
2010-06-03 06:47:25 +08:00
BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
}
Don't forget about sub-register indices when rematting instructions. llvm-svn: 49830
2008-04-17 07:44:44 +08:00
Let callers decide the sub-register index on the def operand of rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
2009-07-16 17:20:10 +08:00
MachineInstr *NewMI = prior(I);
Slightly change the meaning of the reMaterialize target hook when the original instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
2010-06-03 06:47:25 +08:00
NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. llvm-svn: 48995
2008-04-01 04:40:39 +08:00
}
Testing convertToThreeeAddress as X86 llcbeta. llvm-svn: 42630
2007-10-05 16:04:01 +08:00
/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
/// is not marked dead.
static bool hasLiveCondCodeDef(MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isReg() && MO.isDef() &&
Testing convertToThreeeAddress as X86 llcbeta. llvm-svn: 42630
2007-10-05 16:04:01 +08:00
MO.getReg() == X86::EFLAGS && !MO.isDead()) {
return true;
}
}
return false;
}
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
/// to a 32-bit superregister and then truncating back down to a 16-bit
/// subregister.
MachineInstr *
X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
MachineFunction::iterator &MFI,
MachineBasicBlock::iterator &MBBI,
LiveVariables *LV) const {
MachineInstr *MI = MBBI;
unsigned Dest = MI->getOperand(0).getReg();
unsigned Src = MI->getOperand(1).getReg();
bool isDead = MI->getOperand(0).isDead();
bool isKill = MI->getOperand(1).isKill();
unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
? X86::LEA64_32r : X86::LEA32r;
MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Constrain the offset register to a *_NOSP register class when inserting LEA instructions. This unbreaks the machine code verifier and fixes PR8317. llvm-svn: 115879
2010-10-07 08:07:26 +08:00
unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
// Build and insert into an implicit UNDEF value. This is OK because
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
// well be shifting and then extracting the lower 16-bits.
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
// This has the potential to cause partial register stall. e.g.
Add comment about potential partial register stall. llvm-svn: 91220
2009-12-13 02:55:26 +08:00
// movw (%rbp,%rcx,2), %dx
// leal -65(%rdx), %esi
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
// But testing has shown this *does* help performance in 64-bit mode (at
// least on modern x86 machines).
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
MachineInstr *InsMI =
Remove references to INSERT_SUBREG after de-SSA. Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of INSERT_SUBREG. llvm-svn: 107878
2010-07-09 00:40:15 +08:00
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
.addReg(leaInReg, RegState::Define, X86::sub_16bit)
.addReg(Src, getKillRegState(isKill));
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
get(Opc), leaOutReg);
switch (MIOpc) {
default:
llvm_unreachable(0);
break;
case X86::SHL16ri: {
unsigned ShAmt = MI->getOperand(2).getImm();
MIB.addReg(0).addImm(1 << ShAmt)
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
.addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
break;
}
case X86::INC16r:
case X86::INC64_16r:
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
addRegOffset(MIB, leaInReg, true, 1);
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
break;
case X86::DEC16r:
case X86::DEC64_16r:
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
addRegOffset(MIB, leaInReg, true, -1);
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
break;
case X86::ADD16ri:
case X86::ADD16ri8:
reapply: Use the new TB_NOT_REVERSABLE flag instead of special reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
2010-10-08 11:57:25 +08:00
case X86::ADD16ri_DB:
case X86::ADD16ri8_DB:
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
break;
reapply the patch reverted in r116033: "Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'" With a critical fix: the add pseudos clobber EFLAGS. llvm-svn: 116039
2010-10-08 11:54:52 +08:00
case X86::ADD16rr:
case X86::ADD16rr_DB: {
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill();
unsigned leaInReg2 = 0;
MachineInstr *InsMI2 = 0;
if (Src == Src2) {
// ADD16rr %reg1028<kill>, %reg1028
// just a single insert_subreg.
addRegReg(MIB, leaInReg, true, leaInReg, false);
} else {
Constrain the offset register to a *_NOSP register class when inserting LEA instructions. This unbreaks the machine code verifier and fixes PR8317. llvm-svn: 115879
2010-10-07 08:07:26 +08:00
leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
// Build and insert into an implicit UNDEF value. This is OK because
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
// well be shifting and then extracting the lower 16-bits.
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
InsMI2 =
Remove references to INSERT_SUBREG after de-SSA. Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of INSERT_SUBREG. llvm-svn: 107878
2010-07-09 00:40:15 +08:00
BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
.addReg(leaInReg2, RegState::Define, X86::sub_16bit)
.addReg(Src2, getKillRegState(isKill2));
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
addRegReg(MIB, leaInReg, true, leaInReg2, true);
}
if (LV && isKill2 && InsMI2)
LV->replaceKillInstruction(Src2, MI, InsMI2);
break;
}
}
MachineInstr *NewMI = MIB;
MachineInstr *ExtMI =
Convert EXTRACT_SUBREG to COPY when emitting machine instrs. EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
2010-07-09 00:40:22 +08:00
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
.addReg(Dest, RegState::Define | getDeadRegState(isDead))
Convert EXTRACT_SUBREG to COPY when emitting machine instrs. EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
2010-07-09 00:40:22 +08:00
.addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
if (LV) {
// Update live variables
LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
if (isKill)
LV->replaceKillInstruction(Src, MI, InsMI);
if (isDead)
LV->replaceKillInstruction(Dest, MI, ExtMI);
}
return ExtMI;
}
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
/// may be able to convert a two-address instruction into a true
/// three-address instruction on demand. This allows the X86 target (for
/// example) to convert ADD and SHL instructions into LEA instructions if they
/// would require register copies due to two-addressness.
///
/// This method returns a null pointer if the transformation cannot be
/// performed, otherwise it returns the new instruction.
///
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
MachineInstr *
X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
MachineBasicBlock::iterator &MBBI,
Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place. llvm-svn: 53058
2008-07-03 07:41:07 +08:00
LiveVariables *LV) const {
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
MachineInstr *MI = MBBI;
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineFunction &MF = *MI->getParent()->getParent();
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
// All instructions input are two-addr instructions. Get the known operands.
unsigned Dest = MI->getOperand(0).getReg();
unsigned Src = MI->getOperand(1).getReg();
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
bool isDead = MI->getOperand(0).isDead();
bool isKill = MI->getOperand(1).isKill();
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
Properly transfer kill / dead info. llvm-svn: 31765
2006-11-16 04:58:11 +08:00
MachineInstr *NewMI = NULL;
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
// FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
// we have better subtarget support, enable the 16-bit LEA generation here.
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
// 16-bit LEA is also slow on Core2.
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
bool DisableLEA16 = true;
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
unsigned MIOpc = MI->getOpcode();
switch (MIOpc) {
Allow shufps x, x, mask to be converted to pshufd x, mask to save a move. llvm-svn: 28565
2006-05-31 04:26:50 +08:00
case X86::SHUFPSrri: {
assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Fix a build breaker. llvm-svn: 28574
2006-05-31 05:45:53 +08:00
unsigned B = MI->getOperand(1).getReg();
unsigned C = MI->getOperand(2).getReg();
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
if (B != C) return 0;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
unsigned A = MI->getOperand(0).getReg();
unsigned M = MI->getOperand(3).getImm();
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
.addReg(A, RegState::Define | getDeadRegState(isDead))
.addReg(B, getKillRegState(isKill)).addImm(M);
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
break;
}
Compile CodeGen/X86/lea-3.ll:test2 to: _test3: leaq (,%rdi,4), %rax orq %rdi, %rax ret instead of: _test2: movq %rdi, %rax shlq $2, %rax orq %rdi, %rax ret llvm-svn: 35434
2007-03-29 02:12:31 +08:00
case X86::SHL64ri: {
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-15 05:48:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Compile CodeGen/X86/lea-3.ll:test2 to: _test3: leaq (,%rdi,4), %rax orq %rdi, %rax ret instead of: _test2: movq %rdi, %rax shlq $2, %rax orq %rdi, %rax ret llvm-svn: 35434
2007-03-29 02:12:31 +08:00
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
// the flags produced by a shift yet, so this is safe.
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
Constrain the offset register to a *_NOSP register class when inserting LEA instructions. This unbreaks the machine code verifier and fixes PR8317. llvm-svn: 115879
2010-10-07 08:07:26 +08:00
// LEA can't handle RSP.
if (TargetRegisterInfo::isVirtualRegister(Src) &&
!MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
return 0;
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
.addReg(Dest, RegState::Define | getDeadRegState(isDead))
.addReg(0).addImm(1 << ShAmt)
.addReg(Src, getKillRegState(isKill))
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
.addImm(0).addReg(0);
Compile CodeGen/X86/lea-3.ll:test2 to: _test3: leaq (,%rdi,4), %rax orq %rdi, %rax ret instead of: _test2: movq %rdi, %rax shlq $2, %rax orq %rdi, %rax ret llvm-svn: 35434
2007-03-29 02:12:31 +08:00
break;
}
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
case X86::SHL32ri: {
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-15 05:48:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
// the flags produced by a shift yet, so this is safe.
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
Constrain the offset register to a *_NOSP register class when inserting LEA instructions. This unbreaks the machine code verifier and fixes PR8317. llvm-svn: 115879
2010-10-07 08:07:26 +08:00
// LEA can't handle ESP.
if (TargetRegisterInfo::isVirtualRegister(Src) &&
!MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
return 0;
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
.addReg(Dest, RegState::Define | getDeadRegState(isDead))
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
.addReg(0).addImm(1 << ShAmt)
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
.addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
break;
}
case X86::SHL16ri: {
Add implicit def of EFLAGS on those instructions that may modify flags. llvm-svn: 41962
2007-09-15 05:48:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen: leal (,%rcx,8), %rcx It should be leal (,%rcx,8), %ecx llvm-svn: 41735
2007-09-06 08:14:41 +08:00
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
// the flags produced by a shift yet, so this is safe.
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
if (DisableLEA16)
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, RegState::Define | getDeadRegState(isDead))
.addReg(0).addImm(1 << ShAmt)
.addReg(Src, getKillRegState(isKill))
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
.addImm(0).addReg(0);
Two changes: 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
2007-03-20 14:08:29 +08:00
break;
Allow shufps x, x, mask to be converted to pshufd x, mask to save a move. llvm-svn: 28565
2006-05-31 04:26:50 +08:00
}
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
default: {
// The following opcodes also sets the condition code register(s). Only
// convert them to equivalent lea if the condition code register def's
// are dead!
if (hasLiveCondCodeDef(MI))
return 0;
Allow shufps x, x, mask to be converted to pshufd x, mask to save a move. llvm-svn: 28565
2006-05-31 04:26:50 +08:00
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
switch (MIOpc) {
default: return 0;
case X86::INC64r:
Revert r42653 and forward-port the code that lets INC64_32r be converted to LEA64_32r in x86's convertToThreeAddress. This replaces code like this: movl %esi, %edi inc %edi with this: lea 1(%rsi), %edi which appears to be beneficial. llvm-svn: 61830
2009-01-07 07:34:46 +08:00
case X86::INC32r:
case X86::INC64_32r: {
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. llvm-svn: 42783
2007-10-09 15:14:53 +08:00
unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Constrain the offset register to a *_NOSP register class when inserting LEA instructions. This unbreaks the machine code verifier and fixes PR8317. llvm-svn: 115879
2010-10-07 08:07:26 +08:00
// LEA can't handle RSP.
if (TargetRegisterInfo::isVirtualRegister(Src) &&
!MF.getRegInfo().constrainRegClass(Src,
MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
X86::GR32_NOSPRegisterClass))
return 0;
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
.addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. llvm-svn: 68645
2009-04-09 05:14:34 +08:00
Src, isKill, 1);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
}
case X86::INC16r:
case X86::INC64_16r:
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
if (DisableLEA16)
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
.addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
Src, isKill, 1);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
case X86::DEC64r:
Revert r42653 and forward-port the code that lets INC64_32r be converted to LEA64_32r in x86's convertToThreeAddress. This replaces code like this: movl %esi, %edi inc %edi with this: lea 1(%rsi), %edi which appears to be beneficial. llvm-svn: 61830
2009-01-07 07:34:46 +08:00
case X86::DEC32r:
case X86::DEC64_32r: {
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Under 64-bit mode use LEA64_32r instead of LEA64r to save a byte. llvm-svn: 42783
2007-10-09 15:14:53 +08:00
unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Constrain the offset register to a *_NOSP register class when inserting LEA instructions. This unbreaks the machine code verifier and fixes PR8317. llvm-svn: 115879
2010-10-07 08:07:26 +08:00
// LEA can't handle RSP.
if (TargetRegisterInfo::isVirtualRegister(Src) &&
!MF.getRegInfo().constrainRegClass(Src,
MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
X86::GR32_NOSPRegisterClass))
return 0;
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
.addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. llvm-svn: 68645
2009-04-09 05:14:34 +08:00
Src, isKill, -1);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
}
case X86::DEC16r:
case X86::DEC64_16r:
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
if (DisableLEA16)
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
.addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
Src, isKill, -1);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
case X86::ADD64rr:
reapply the patch reverted in r116033: "Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'" With a critical fix: the add pseudos clobber EFLAGS. llvm-svn: 116039
2010-10-08 11:54:52 +08:00
case X86::ADD64rr_DB:
case X86::ADD32rr:
case X86::ADD32rr_DB: {
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
reapply the patch reverted in r116033: "Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'" With a critical fix: the add pseudos clobber EFLAGS. llvm-svn: 116039
2010-10-08 11:54:52 +08:00
unsigned Opc;
TargetRegisterClass *RC;
if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
Opc = X86::LEA64r;
RC = X86::GR64_NOSPRegisterClass;
} else {
Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
RC = X86::GR32_NOSPRegisterClass;
}
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill();
Constrain the offset register to a *_NOSP register class when inserting LEA instructions. This unbreaks the machine code verifier and fixes PR8317. llvm-svn: 115879
2010-10-07 08:07:26 +08:00
// LEA can't handle RSP.
if (TargetRegisterInfo::isVirtualRegister(Src2) &&
reapply the patch reverted in r116033: "Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'" With a critical fix: the add pseudos clobber EFLAGS. llvm-svn: 116039
2010-10-08 11:54:52 +08:00
!MF.getRegInfo().constrainRegClass(Src2, RC))
Constrain the offset register to a *_NOSP register class when inserting LEA instructions. This unbreaks the machine code verifier and fixes PR8317. llvm-svn: 115879
2010-10-07 08:07:26 +08:00
return 0;
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
.addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
Src, isKill, Src2, isKill2);
if (LV && isKill2)
LV->replaceKillInstruction(Src2, MI, NewMI);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
}
reapply the patch reverted in r116033: "Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'" With a critical fix: the add pseudos clobber EFLAGS. llvm-svn: 116039
2010-10-08 11:54:52 +08:00
case X86::ADD16rr:
case X86::ADD16rr_DB: {
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
if (DisableLEA16)
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill();
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
.addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
Src, isKill, Src2, isKill2);
if (LV && isKill2)
LV->replaceKillInstruction(Src2, MI, NewMI);
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
}
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
case X86::ADD64ri32:
case X86::ADD64ri8:
reapply: Use the new TB_NOT_REVERSABLE flag instead of special reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
2010-10-08 11:57:25 +08:00
case X86::ADD64ri32_DB:
case X86::ADD64ri8_DB:
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
.addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, MI->getOperand(2).getImm());
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
case X86::ADD32ri:
reapply: Use the new TB_NOT_REVERSABLE flag instead of special reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
2010-10-08 11:57:25 +08:00
case X86::ADD32ri8:
case X86::ADD32ri_DB:
case X86::ADD32ri8_DB: {
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
.addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. llvm-svn: 68645
2009-04-09 05:14:34 +08:00
Src, isKill, MI->getOperand(2).getImm());
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
}
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
case X86::ADD16ri:
case X86::ADD16ri8:
reapply: Use the new TB_NOT_REVERSABLE flag instead of special reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
2010-10-08 11:57:25 +08:00
case X86::ADD16ri_DB:
case X86::ADD16ri8_DB:
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
if (DisableLEA16)
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. llvm-svn: 91223
2009-12-13 04:03:14 +08:00
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Change LEA to have 5 operands for its memory operand, just like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
2010-07-09 07:46:44 +08:00
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Add support to 3-addressify 16-bit instructions. llvm-svn: 91104
2009-12-11 14:01:48 +08:00
.addReg(Dest, RegState::Define |
getDeadRegState(isDead)),
Src, isKill, MI->getOperand(2).getImm());
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
break;
}
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
}
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's. llvm-svn: 32097
2006-12-02 05:52:41 +08:00
}
In 64-bit mode, avoid using leal with 32-bit 32-bit address size, e.g. leal 1(%ecx), %edi, which requires 67H prefix. llvm-svn: 42647
2007-10-06 04:34:26 +08:00
In some cases, e.g. ADD32ri, no transformation is made. Guide against it. llvm-svn: 46849
2008-02-07 16:29:53 +08:00
if (!NewMI) return 0;
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
if (LV) { // Update live variables
if (isKill)
LV->replaceKillInstruction(Src, MI, NewMI);
if (isDead)
LV->replaceKillInstruction(Dest, MI, NewMI);
}
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
MFI->insert(MBBI, NewMI); // Insert the new inst
Properly transfer kill / dead info. llvm-svn: 31765
2006-11-16 04:58:11 +08:00
return NewMI;
Implement the convertToThreeAddress method, add support for inverting JP/JNP branches. llvm-svn: 19247
2005-01-02 10:37:07 +08:00
}
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
/// commuteInstruction - We have a few instructions that must be hacked on to
/// commute them.
///
Add option to commuteInstruction() which forces it to create a new (commuted) instruction. llvm-svn: 52308
2008-06-16 15:33:11 +08:00
MachineInstr *
X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
switch (MI->getOpcode()) {
Improve coverage of the X86 instruction set by adding 16-bit shift doubles. llvm-svn: 19687
2005-01-19 15:31:24 +08:00
case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Add patterns for SHLD64* and SHRD64*. llvm-svn: 41975
2007-09-15 07:17:45 +08:00
case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Improve coverage of the X86 instruction set by adding 16-bit shift doubles. llvm-svn: 19687
2005-01-19 15:31:24 +08:00
unsigned Opc;
unsigned Size;
switch (MI->getOpcode()) {
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
2009-07-15 00:55:14 +08:00
default: llvm_unreachable("Unreachable!");
Improve coverage of the X86 instruction set by adding 16-bit shift doubles. llvm-svn: 19687
2005-01-19 15:31:24 +08:00
case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Add patterns for SHLD64* and SHRD64*. llvm-svn: 41975
2007-09-15 07:17:45 +08:00
case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Improve coverage of the X86 instruction set by adding 16-bit shift doubles. llvm-svn: 19687
2005-01-19 15:31:24 +08:00
}
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm llvm-svn: 45453
2007-12-31 04:49:49 +08:00
unsigned Amt = MI->getOperand(3).getImm();
Define patterns for shld and shrd that match immediate shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. llvm-svn: 57662
2008-10-17 09:23:35 +08:00
if (NewMI) {
MachineFunction &MF = *MI->getParent()->getParent();
MI = MF.CloneMachineInstr(MI);
NewMI = false;
commuteInstr() can now commute non-ssa machine instrs. llvm-svn: 47043
2008-02-13 10:46:49 +08:00
}
Define patterns for shld and shrd that match immediate shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. llvm-svn: 57662
2008-10-17 09:23:35 +08:00
MI->setDesc(get(Opc));
MI->getOperand(3).setImm(Size-Amt);
return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
}
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
case X86::CMOVB16rr:
case X86::CMOVB32rr:
case X86::CMOVB64rr:
case X86::CMOVAE16rr:
case X86::CMOVAE32rr:
case X86::CMOVAE64rr:
case X86::CMOVE16rr:
case X86::CMOVE32rr:
case X86::CMOVE64rr:
case X86::CMOVNE16rr:
case X86::CMOVNE32rr:
case X86::CMOVNE64rr:
Use #NAME# to have the CMOV multiclass define things with the same names as before (e.g. CMOVBE16rr instead of CMOVBErr16). llvm-svn: 115705
2010-10-06 07:00:14 +08:00
case X86::CMOVBE16rr:
case X86::CMOVBE32rr:
case X86::CMOVBE64rr:
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
case X86::CMOVA16rr:
case X86::CMOVA32rr:
case X86::CMOVA64rr:
case X86::CMOVL16rr:
case X86::CMOVL32rr:
case X86::CMOVL64rr:
case X86::CMOVGE16rr:
case X86::CMOVGE32rr:
case X86::CMOVGE64rr:
case X86::CMOVLE16rr:
case X86::CMOVLE32rr:
case X86::CMOVLE64rr:
case X86::CMOVG16rr:
case X86::CMOVG32rr:
case X86::CMOVG64rr:
case X86::CMOVS16rr:
case X86::CMOVS32rr:
case X86::CMOVS64rr:
case X86::CMOVNS16rr:
case X86::CMOVNS32rr:
case X86::CMOVNS64rr:
case X86::CMOVP16rr:
case X86::CMOVP32rr:
case X86::CMOVP64rr:
case X86::CMOVNP16rr:
case X86::CMOVNP32rr:
Define instructions for cmovo and cmovno. llvm-svn: 61836
2009-01-07 08:35:10 +08:00
case X86::CMOVNP64rr:
case X86::CMOVO16rr:
case X86::CMOVO32rr:
case X86::CMOVO64rr:
case X86::CMOVNO16rr:
case X86::CMOVNO32rr:
case X86::CMOVNO64rr: {
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
unsigned Opc = 0;
switch (MI->getOpcode()) {
default: break;
case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Use #NAME# to have the CMOV multiclass define things with the same names as before (e.g. CMOVBE16rr instead of CMOVBErr16). llvm-svn: 115705
2010-10-06 07:00:14 +08:00
case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Fixed a few 64 bit cases in X86InstrInfo::commuteInstruction llvm-svn: 69417
2009-04-18 13:16:01 +08:00
case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Fixed a few 64 bit cases in X86InstrInfo::commuteInstruction llvm-svn: 69417
2009-04-18 13:16:01 +08:00
case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Define instructions for cmovo and cmovno. llvm-svn: 61836
2009-01-07 08:35:10 +08:00
case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Fixed a few 64 bit cases in X86InstrInfo::commuteInstruction llvm-svn: 69417
2009-04-18 13:16:01 +08:00
case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Define instructions for cmovo and cmovno. llvm-svn: 61836
2009-01-07 08:35:10 +08:00
case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
}
Define patterns for shld and shrd that match immediate shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. llvm-svn: 57662
2008-10-17 09:23:35 +08:00
if (NewMI) {
MachineFunction &MF = *MI->getParent()->getParent();
MI = MF.CloneMachineInstr(MI);
NewMI = false;
}
rename MachineInstr::setInstrDescriptor -> setDesc llvm-svn: 45871
2008-01-12 02:10:50 +08:00
MI->setDesc(get(Opc));
Commute x86 cmove instructions by swapping the operands and change the condition to its inverse. Testing this as llcbeta llvm-svn: 42661
2007-10-06 07:13:21 +08:00
// Fallthrough intended.
}
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
default:
Add option to commuteInstruction() which forces it to create a new (commuted) instruction. llvm-svn: 52308
2008-06-16 15:33:11 +08:00
return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
Teach the code generator that shrd/shld is commutable if it has an immediate. This allows us to generate this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %EDX, DWORD PTR [%ESP + 8] shld %EDX, %EDX, 2 shl %EAX, 2 ret instead of this: foo: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EDX, %EAX shrd %EDX, %ECX, 30 shl %EAX, 2 ret Note the magically transmogrifying immediate. llvm-svn: 19686
2005-01-19 15:11:01 +08:00
}
}
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
switch (BrOpc) {
default: return X86::COND_INVALID;
refactor the conditional jump instructions in the .td file to use a multipattern that generates both the 1-byte and 4-byte versions from the same defm llvm-svn: 95901
2010-02-12 03:25:55 +08:00
case X86::JE_4: return X86::COND_E;
case X86::JNE_4: return X86::COND_NE;
case X86::JL_4: return X86::COND_L;
case X86::JLE_4: return X86::COND_LE;
case X86::JG_4: return X86::COND_G;
case X86::JGE_4: return X86::COND_GE;
case X86::JB_4: return X86::COND_B;
case X86::JBE_4: return X86::COND_BE;
case X86::JA_4: return X86::COND_A;
case X86::JAE_4: return X86::COND_AE;
case X86::JS_4: return X86::COND_S;
case X86::JNS_4: return X86::COND_NS;
case X86::JP_4: return X86::COND_P;
case X86::JNP_4: return X86::COND_NP;
case X86::JO_4: return X86::COND_O;
case X86::JNO_4: return X86::COND_NO;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
}
unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
switch (CC) {
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
2009-07-15 00:55:14 +08:00
default: llvm_unreachable("Illegal condition code!");
refactor the conditional jump instructions in the .td file to use a multipattern that generates both the 1-byte and 4-byte versions from the same defm llvm-svn: 95901
2010-02-12 03:25:55 +08:00
case X86::COND_E: return X86::JE_4;
case X86::COND_NE: return X86::JNE_4;
case X86::COND_L: return X86::JL_4;
case X86::COND_LE: return X86::JLE_4;
case X86::COND_G: return X86::JG_4;
case X86::COND_GE: return X86::JGE_4;
case X86::COND_B: return X86::JB_4;
case X86::COND_BE: return X86::JBE_4;
case X86::COND_A: return X86::JA_4;
case X86::COND_AE: return X86::JAE_4;
case X86::COND_S: return X86::JS_4;
case X86::COND_NS: return X86::JNS_4;
case X86::COND_P: return X86::JP_4;
case X86::COND_NP: return X86::JNP_4;
case X86::COND_O: return X86::JO_4;
case X86::COND_NO: return X86::JNO_4;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
}
Implement support for branch condition reversal. llvm-svn: 31099
2006-10-21 13:52:40 +08:00
/// GetOppositeBranchCondition - Return the inverse of the specified condition,
/// e.g. turning COND_E to COND_NE.
X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
switch (CC) {
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
2009-07-15 00:55:14 +08:00
default: llvm_unreachable("Illegal condition code!");
Implement support for branch condition reversal. llvm-svn: 31099
2006-10-21 13:52:40 +08:00
case X86::COND_E: return X86::COND_NE;
case X86::COND_NE: return X86::COND_E;
case X86::COND_L: return X86::COND_GE;
case X86::COND_LE: return X86::COND_G;
case X86::COND_G: return X86::COND_LE;
case X86::COND_GE: return X86::COND_L;
case X86::COND_B: return X86::COND_AE;
case X86::COND_BE: return X86::COND_A;
case X86::COND_A: return X86::COND_BE;
case X86::COND_AE: return X86::COND_B;
case X86::COND_S: return X86::COND_NS;
case X86::COND_NS: return X86::COND_S;
case X86::COND_P: return X86::COND_NP;
case X86::COND_NP: return X86::COND_P;
case X86::COND_O: return X86::COND_NO;
case X86::COND_NO: return X86::COND_O;
}
}
Do not treat FP_REG_KILL as terminator in branch analysis (X86). llvm-svn: 37578
2007-06-15 06:03:45 +08:00
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
const MCInstrDesc &MCID = MI->getDesc();
if (!MCID.isTerminator()) return false;
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
2008-01-07 09:56:04 +08:00
// Conditional branch is a special case.
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
if (MCID.isBranch() && !MCID.isBarrier())
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
2008-01-07 09:56:04 +08:00
return true;
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
if (!MCID.isPredicable())
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
2008-01-07 09:56:04 +08:00
return true;
return !isPredicated(MI);
Do not treat FP_REG_KILL as terminator in branch analysis (X86). llvm-svn: 37578
2007-06-15 06:03:45 +08:00
}
Implement support for branch condition reversal. llvm-svn: 31099
2006-10-21 13:52:40 +08:00
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
2009-02-09 15:14:22 +08:00
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const {
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Start from the bottom of the block and work up, examining the
// terminator instructions.
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
MachineBasicBlock::iterator I = MBB.end();
Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB. llvm-svn: 101162
2010-04-14 02:50:27 +08:00
MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
while (I != MBB.begin()) {
--I;
Teach AnalyzeBranch, RemoveBranch and the branch folder to be tolerant of debug info following the branch(es) at the end of a block. llvm-svn: 100168
2010-04-02 09:38:09 +08:00
if (I->isDebugValue())
continue;
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
// Working from the bottom, when we see a non-terminator instruction, we're
// done.
Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill pass that inserted it. It is no longer necessary to limit the live ranges of FP registers to a single basic block. llvm-svn: 108536
2010-07-17 01:41:44 +08:00
if (!isUnpredicatedTerminator(I))
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
break;
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
// A terminator that isn't a branch can't easily be handled by this
// analysis.
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
if (!I->getDesc().isBranch())
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
return true;
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Handle unconditional branches.
refactor the conditional jump instructions in the .td file to use a multipattern that generates both the 1-byte and 4-byte versions from the same defm llvm-svn: 95901
2010-02-12 03:25:55 +08:00
if (I->getOpcode() == X86::JMP_4) {
Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB. llvm-svn: 101162
2010-04-14 02:50:27 +08:00
UnCondBrIter = I;
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
2009-02-09 15:14:22 +08:00
if (!AllowModify) {
TBB = I->getOperand(0).getMBB();
Optimize code placement in loop to eliminate unconditional branches or move unconditional branch to the outside of the loop. e.g. /// A: /// ... /// <fallthrough to B> /// /// B: --> loop header /// ... /// jcc <cond> C, [exit] /// /// C: /// ... /// jmp B /// /// ==> /// /// A: /// ... /// jmp B /// /// C: --> new loop header /// ... /// <fallthough to B> /// /// B: /// ... /// jcc <cond> C, [exit] llvm-svn: 71209
2009-05-08 14:34:09 +08:00
continue;
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
2009-02-09 15:14:22 +08:00
}
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// If the block has any instructions after a JMP, delete them.
improve portability to avoid conflicting with std::next in c++'0x. Patch by Howard Hinnant! llvm-svn: 90365
2009-12-03 08:50:42 +08:00
while (llvm::next(I) != MBB.end())
llvm::next(I)->eraseFromParent();
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
Cond.clear();
FBB = 0;
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Delete the JMP if it's equivalent to a fall-through.
if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
TBB = 0;
I->eraseFromParent();
I = MBB.end();
Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB. llvm-svn: 101162
2010-04-14 02:50:27 +08:00
UnCondBrIter = MBB.end();
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
continue;
}
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB. llvm-svn: 101162
2010-04-14 02:50:27 +08:00
// TBB is used to indicate the unconditional destination.
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
TBB = I->getOperand(0).getMBB();
continue;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Handle conditional branches.
X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
if (BranchCode == X86::COND_INVALID)
return true; // Can't handle indirect branch.
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Working from the bottom, handle the first conditional branch.
if (Cond.empty()) {
Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB. llvm-svn: 101162
2010-04-14 02:50:27 +08:00
MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
if (AllowModify && UnCondBrIter != MBB.end() &&
MBB.isLayoutSuccessor(TargetBB)) {
// If we can modify the code and it ends in something like:
//
// jCC L1
// jmp L2
// L1:
// ...
// L2:
//
// Then we can change this to:
//
// jnCC L2
// L1:
// ...
// L2:
//
// Which is a bit more efficient.
// We conditionally jump to the fall-through block.
BranchCode = GetOppositeBranchCondition(BranchCode);
unsigned JNCC = GetCondBranchFromCond(BranchCode);
MachineBasicBlock::iterator OldInst = I;
BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
.addMBB(UnCondBrIter->getOperand(0).getMBB());
BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
.addMBB(TargetBB);
OldInst->eraseFromParent();
UnCondBrIter->eraseFromParent();
// Restart the analysis.
UnCondBrIter = MBB.end();
I = MBB.end();
continue;
}
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
FBB = TBB;
TBB = I->getOperand(0).getMBB();
Cond.push_back(MachineOperand::CreateImm(BranchCode));
continue;
}
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
// Handle subsequent conditional branches. Only handle the case where all
// conditional branches branch to the same destination and their condition
// opcodes fit one of the special multi-branch idioms.
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
assert(Cond.size() == 1);
assert(TBB);
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
// Only handle the case where all conditional branches branch to the same
// destination.
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
if (TBB != I->getOperand(0).getMBB())
return true;
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// If the conditions are the same, we can leave them alone.
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
if (OldBranchCode == BranchCode)
continue;
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
// If they differ, see if they fit one of the known patterns. Theoretically,
// we could handle more patterns here, but we shouldn't expect to see them
// if instruction selection has done a reasonable job.
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
if ((OldBranchCode == X86::COND_NP &&
BranchCode == X86::COND_E) ||
(OldBranchCode == X86::COND_E &&
BranchCode == X86::COND_NP))
BranchCode = X86::COND_NP_OR_E;
else if ((OldBranchCode == X86::COND_P &&
BranchCode == X86::COND_NE) ||
(OldBranchCode == X86::COND_NE &&
BranchCode == X86::COND_P))
BranchCode = X86::COND_NE_OR_P;
else
return true;
Whitespace changes, comment clarification. No functional changes. llvm-svn: 91274
2009-12-14 14:51:19 +08:00
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Update the MachineOperand.
Cond[0].setImm(BranchCode);
Handle blocks with 2 unconditional branches in AnalyzeBranch. llvm-svn: 37571
2007-06-14 01:59:52 +08:00
}
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
return false;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. llvm-svn: 37193
2007-05-18 08:18:17 +08:00
unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
MachineBasicBlock::iterator I = MBB.end();
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
unsigned Count = 0;
while (I != MBB.begin()) {
--I;
Teach AnalyzeBranch, RemoveBranch and the branch folder to be tolerant of debug info following the branch(es) at the end of a block. llvm-svn: 100168
2010-04-02 09:38:09 +08:00
if (I->isDebugValue())
continue;
refactor the conditional jump instructions in the .td file to use a multipattern that generates both the 1-byte and 4-byte versions from the same defm llvm-svn: 95901
2010-02-12 03:25:55 +08:00
if (I->getOpcode() != X86::JMP_4 &&
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
break;
// Remove the branch.
I->eraseFromParent();
I = MBB.end();
++Count;
}
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
return Count;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. llvm-svn: 37193
2007-05-18 08:18:17 +08:00
unsigned
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
2010-06-18 06:43:56 +08:00
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const {
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
allow insertion of a conditional branch with fall-through llvm-svn: 31095
2006-10-21 13:34:23 +08:00
assert((Cond.size() == 1 || Cond.size() == 0) &&
"X86 branch conditions have one component!");
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
if (Cond.empty()) {
// Unconditional branch?
assert(!FBB && "Unconditional branch with multiple successors!");
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
2010-06-18 06:43:56 +08:00
BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. llvm-svn: 37193
2007-05-18 08:18:17 +08:00
return 1;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
// Conditional branch.
unsigned Count = 0;
X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
switch (CC) {
case X86::COND_NP_OR_E:
// Synthesize NP_OR_E with two branches.
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
2010-06-18 06:43:56 +08:00
BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
Revert r97766. It's deleting a tag. llvm-svn: 97768
2010-03-05 08:33:59 +08:00
++Count;
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
2010-06-18 06:43:56 +08:00
BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
Revert r97766. It's deleting a tag. llvm-svn: 97768
2010-03-05 08:33:59 +08:00
++Count;
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
break;
case X86::COND_NE_OR_P:
// Synthesize NE_OR_P with two branches.
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
2010-06-18 06:43:56 +08:00
BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
Revert r97766. It's deleting a tag. llvm-svn: 97768
2010-03-05 08:33:59 +08:00
++Count;
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
2010-06-18 06:43:56 +08:00
BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
Revert r97766. It's deleting a tag. llvm-svn: 97768
2010-03-05 08:33:59 +08:00
++Count;
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
break;
Revert r97766. It's deleting a tag. llvm-svn: 97768
2010-03-05 08:33:59 +08:00
default: {
unsigned Opc = GetCondBranchFromCond(CC);
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
2010-06-18 06:43:56 +08:00
BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Revert r97766. It's deleting a tag. llvm-svn: 97768
2010-03-05 08:33:59 +08:00
++Count;
}
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
}
if (FBB) {
// Two-way Conditional branch. Insert the second branch.
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
2010-06-18 06:43:56 +08:00
BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
++Count;
}
return Count;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. llvm-svn: 69111
2009-04-15 08:04:23 +08:00
/// isHReg - Test if the given register is a physical h register.
static bool isHReg(unsigned Reg) {
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
2009-04-28 00:41:36 +08:00
return X86::GR8_ABCD_HRegClass.contains(Reg);
Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. llvm-svn: 69111
2009-04-15 08:04:23 +08:00
}
Properly handle passing of FP stuff to varargs function on Win64: value should be copied to the corresponding shadow reg as well. Patch by Cameron Esfahani! llvm-svn: 112262
2010-08-27 22:43:06 +08:00
// Try and copy between VR128/VR64 and GR64 registers.
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
bool HasAVX) {
Properly handle passing of FP stuff to varargs function on Win64: value should be copied to the corresponding shadow reg as well. Patch by Cameron Esfahani! llvm-svn: 112262
2010-08-27 22:43:06 +08:00
// SrcReg(VR128) -> DestReg(GR64)
// SrcReg(VR64) -> DestReg(GR64)
// SrcReg(GR64) -> DestReg(VR128)
// SrcReg(GR64) -> DestReg(VR64)
if (X86::GR64RegClass.contains(DestReg)) {
if (X86::VR128RegClass.contains(SrcReg)) {
// Copy from a VR128 register to a GR64 register.
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
Properly handle passing of FP stuff to varargs function on Win64: value should be copied to the corresponding shadow reg as well. Patch by Cameron Esfahani! llvm-svn: 112262
2010-08-27 22:43:06 +08:00
} else if (X86::VR64RegClass.contains(SrcReg)) {
// Copy from a VR64 register to a GR64 register.
return X86::MOVSDto64rr;
}
} else if (X86::GR64RegClass.contains(SrcReg)) {
// Copy from a GR64 register to a VR128 register.
if (X86::VR128RegClass.contains(DestReg))
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
Properly handle passing of FP stuff to varargs function on Win64: value should be copied to the corresponding shadow reg as well. Patch by Cameron Esfahani! llvm-svn: 112262
2010-08-27 22:43:06 +08:00
// Copy from a GR64 register to a VR64 register.
else if (X86::VR64RegClass.contains(DestReg))
return X86::MOV64toSDrr;
}
Add support for GR32 <-> FR32 cross class copies. We already support GR64 <-> VR128 copies. All of these copies break partial register dependencies by zeroing the high part of the target register. llvm-svn: 140348
2011-09-23 06:45:24 +08:00
// SrcReg(FR32) -> DestReg(GR32)
// SrcReg(GR32) -> DestReg(FR32)
if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
// Copy from a FR32 register to a GR32 register.
return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
// Copy from a GR32 register to a FR32 register.
return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
Properly handle passing of FP stuff to varargs function on Win64: value should be copied to the corresponding shadow reg as well. Patch by Cameron Esfahani! llvm-svn: 112262
2010-08-27 22:43:06 +08:00
return 0;
}
Implement X86InstrInfo::copyPhysReg llvm-svn: 107898
2010-07-09 03:46:25 +08:00
void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
// First deal with the normal symmetric copies.
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
Implement X86InstrInfo::copyPhysReg llvm-svn: 107898
2010-07-09 03:46:25 +08:00
unsigned Opc = 0;
if (X86::GR64RegClass.contains(DestReg, SrcReg))
Opc = X86::MOV64rr;
else if (X86::GR32RegClass.contains(DestReg, SrcReg))
Opc = X86::MOV32rr;
else if (X86::GR16RegClass.contains(DestReg, SrcReg))
Opc = X86::MOV16rr;
else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
// Copying to or from a physical H register on x86-64 requires a NOREX
// move. Otherwise use a normal move.
if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Constrain both operands on MOVZX32_NOREXrr8. This instruction is explicitly encoded without an REX prefix, so both operands but be *_NOREX. Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX constraints are not satisfied. This fixes a miscompilation in 20040709-2 in the gcc test suite. llvm-svn: 141410
2011-10-08 04:15:54 +08:00
TM.getSubtarget<X86Subtarget>().is64Bit()) {
Implement X86InstrInfo::copyPhysReg llvm-svn: 107898
2010-07-09 03:46:25 +08:00
Opc = X86::MOV8rr_NOREX;
Constrain both operands on MOVZX32_NOREXrr8. This instruction is explicitly encoded without an REX prefix, so both operands but be *_NOREX. Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX constraints are not satisfied. This fixes a miscompilation in 20040709-2 in the gcc test suite. llvm-svn: 141410
2011-10-08 04:15:54 +08:00
// Both operands must be encodable without an REX prefix.
assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
"8-bit H register can not be copied outside GR8_NOREX");
} else
Implement X86InstrInfo::copyPhysReg llvm-svn: 107898
2010-07-09 03:46:25 +08:00
Opc = X86::MOV8rr;
} else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Add 256-bit load/store recognition and matching in several places. llvm-svn: 135171
2011-07-15 02:50:58 +08:00
else if (X86::VR256RegClass.contains(DestReg, SrcReg))
Opc = X86::VMOVAPSYrr;
Remember the VR64 register class llvm-svn: 107920
2010-07-09 06:30:35 +08:00
else if (X86::VR64RegClass.contains(DestReg, SrcReg))
Opc = X86::MMX_MOVQ64rr;
Properly handle passing of FP stuff to varargs function on Win64: value should be copied to the corresponding shadow reg as well. Patch by Cameron Esfahani! llvm-svn: 112262
2010-08-27 22:43:06 +08:00
else
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
Implement X86InstrInfo::copyPhysReg llvm-svn: 107898
2010-07-09 03:46:25 +08:00
if (Opc) {
BuildMI(MBB, MI, DL, get(Opc), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
}
// Moving EFLAGS to / from another register requires a push and a pop.
if (SrcReg == X86::EFLAGS) {
if (X86::GR64RegClass.contains(DestReg)) {
BuildMI(MBB, MI, DL, get(X86::PUSHF64));
BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
return;
} else if (X86::GR32RegClass.contains(DestReg)) {
BuildMI(MBB, MI, DL, get(X86::PUSHF32));
BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
return;
}
}
if (DestReg == X86::EFLAGS) {
if (X86::GR64RegClass.contains(SrcReg)) {
BuildMI(MBB, MI, DL, get(X86::PUSH64r))
.addReg(SrcReg, getKillRegState(KillSrc));
BuildMI(MBB, MI, DL, get(X86::POPF64));
return;
} else if (X86::GR32RegClass.contains(SrcReg)) {
BuildMI(MBB, MI, DL, get(X86::PUSH32r))
.addReg(SrcReg, getKillRegState(KillSrc));
BuildMI(MBB, MI, DL, get(X86::POPF32));
return;
}
}
DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
<< " to " << RI.getName(DestReg) << '\n');
llvm_unreachable("Cannot emit physreg copy instruction");
}
Merge getStoreRegOpcode and getLoadRegOpcode. llvm-svn: 105900
2010-06-13 04:13:29 +08:00
static unsigned getLoadStoreRegOpcode(unsigned Reg,
const TargetRegisterClass *RC,
bool isStackAligned,
const TargetMachine &TM,
bool load) {
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
Fix PR10059 and future variations by handling all register subclasses. Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible register classes instead of trying to list all register classes in X86's getLoadStoreRegOpcode. llvm-svn: 132398
2011-06-01 23:32:10 +08:00
switch (RC->getSize()) {
Convert getLoadStoreRegOpcode to use a switch. llvm-svn: 108123
2010-07-12 11:43:04 +08:00
default:
Fix PR10059 and future variations by handling all register subclasses. Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible register classes instead of trying to list all register classes in X86's getLoadStoreRegOpcode. llvm-svn: 132398
2011-06-01 23:32:10 +08:00
llvm_unreachable("Unknown spill size");
case 1:
assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
2009-04-28 00:41:36 +08:00
if (TM.getSubtarget<X86Subtarget>().is64Bit())
Fix PR10059 and future variations by handling all register subclasses. Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible register classes instead of trying to list all register classes in X86's getLoadStoreRegOpcode. llvm-svn: 132398
2011-06-01 23:32:10 +08:00
// Copying to or from a physical H register on x86-64 requires a NOREX
// move. Otherwise use a normal move.
if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
return load ? X86::MOV8rm : X86::MOV8mr;
case 2:
assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
return load ? X86::MOV16rm : X86::MOV16mr;
case 4:
if (X86::GR32RegClass.hasSubClassEq(RC))
return load ? X86::MOV32rm : X86::MOV32mr;
if (X86::FR32RegClass.hasSubClassEq(RC))
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
return load ?
(HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
(HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Fix PR10059 and future variations by handling all register subclasses. Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible register classes instead of trying to list all register classes in X86's getLoadStoreRegOpcode. llvm-svn: 132398
2011-06-01 23:32:10 +08:00
if (X86::RFP32RegClass.hasSubClassEq(RC))
return load ? X86::LD_Fp32m : X86::ST_Fp32m;
llvm_unreachable("Unknown 4-byte regclass");
case 8:
if (X86::GR64RegClass.hasSubClassEq(RC))
return load ? X86::MOV64rm : X86::MOV64mr;
if (X86::FR64RegClass.hasSubClassEq(RC))
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
return load ?
(HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
(HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Fix PR10059 and future variations by handling all register subclasses. Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible register classes instead of trying to list all register classes in X86's getLoadStoreRegOpcode. llvm-svn: 132398
2011-06-01 23:32:10 +08:00
if (X86::VR64RegClass.hasSubClassEq(RC))
return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
if (X86::RFP64RegClass.hasSubClassEq(RC))
return load ? X86::LD_Fp64m : X86::ST_Fp64m;
llvm_unreachable("Unknown 8-byte regclass");
case 10:
assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Merge getStoreRegOpcode and getLoadRegOpcode. llvm-svn: 105900
2010-06-13 04:13:29 +08:00
return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS, whenever AVX is enabled. llvm-svn: 138849
2011-08-31 11:04:09 +08:00
case 16: {
Fix PR10059 and future variations by handling all register subclasses. Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible register classes instead of trying to list all register classes in X86's getLoadStoreRegOpcode. llvm-svn: 132398
2011-06-01 23:32:10 +08:00
assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
// If stack is realigned we can use aligned stores.
Merge getStoreRegOpcode and getLoadRegOpcode. llvm-svn: 105900
2010-06-13 04:13:29 +08:00
if (isStackAligned)
Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS, whenever AVX is enabled. llvm-svn: 138849
2011-08-31 11:04:09 +08:00
return load ?
(HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
(HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Merge getStoreRegOpcode and getLoadRegOpcode. llvm-svn: 105900
2010-06-13 04:13:29 +08:00
else
Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS, whenever AVX is enabled. llvm-svn: 138849
2011-08-31 11:04:09 +08:00
return load ?
(HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
(HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
}
Add 256-bit load/store recognition and matching in several places. llvm-svn: 135171
2011-07-15 02:50:58 +08:00
case 32:
assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
// If stack is realigned we can use aligned stores.
if (isStackAligned)
return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
else
return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
}
Merge getStoreRegOpcode and getLoadRegOpcode. llvm-svn: 105900
2010-06-13 04:13:29 +08:00
}
static unsigned getStoreRegOpcode(unsigned SrcReg,
const TargetRegisterClass *RC,
bool isStackAligned,
TargetMachine &TM) {
return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
}
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
Merge getStoreRegOpcode and getLoadRegOpcode. llvm-svn: 105900
2010-06-13 04:13:29 +08:00
static unsigned getLoadRegOpcode(unsigned DestReg,
const TargetRegisterClass *RC,
bool isStackAligned,
const TargetMachine &TM) {
return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
}
void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, int FrameIdx,
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. llvm-svn: 103193
2010-05-07 03:06:44 +08:00
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
const MachineFunction &MF = *MBB.getParent();
Add assertions that expose the PR7713 miscompilation: Accessing a stack slot with a too-big register class. llvm-svn: 109488
2010-07-27 12:16:58 +08:00
assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
"Stack slot too small for store");
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know about stack alignment. llvm-svn: 133679
2011-06-23 09:53:43 +08:00
RI.canRealignStack(MF);
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
2009-04-28 00:41:36 +08:00
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
use findDebugLoc in more places. llvm-svn: 94477
2010-01-26 08:03:12 +08:00
DebugLoc DL = MBB.findDebugLoc(MI);
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
.addReg(SrcReg, getKillRegState(isKill));
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
}
void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
bool isKill,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
Add basic infrastructure and x86 support for preserving MachineMemOperand information when unfolding memory references. llvm-svn: 83656
2009-10-10 02:10:05 +08:00
MachineInstr::mmo_iterator MMOBegin,
MachineInstr::mmo_iterator MMOEnd,
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
SmallVectorImpl<MachineInstr*> &NewMIs) const {
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
bool isAligned = MMOBegin != MMOEnd &&
(*MMOBegin)->getAlignment() >= Alignment;
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
2009-04-28 00:41:36 +08:00
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() llvm-svn: 100214
2010-04-03 04:16:16 +08:00
DebugLoc DL;
Eliminate a couple of non-DebugLoc BuildMI variants. Modify callers. llvm-svn: 64409
2009-02-13 07:08:38 +08:00
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Factor out the code to add a MachineOperand to a MachineInstrBuilder. llvm-svn: 64891
2009-02-18 13:45:50 +08:00
MIB.addOperand(Addr[i]);
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
MIB.addReg(SrcReg, getKillRegState(isKill));
Add basic infrastructure and x86 support for preserving MachineMemOperand information when unfolding memory references. llvm-svn: 83656
2009-10-10 02:10:05 +08:00
(*MIB).setMemRefs(MMOBegin, MMOEnd);
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
NewMIs.push_back(MIB);
}
void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx,
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. llvm-svn: 103193
2010-05-07 03:06:44 +08:00
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
Use aligned stack spills, where possible. This fixes PR2549. llvm-svn: 53784
2008-07-19 14:30:51 +08:00
const MachineFunction &MF = *MBB.getParent();
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know about stack alignment. llvm-svn: 133679
2011-06-23 09:53:43 +08:00
RI.canRealignStack(MF);
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
2009-04-28 00:41:36 +08:00
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
use findDebugLoc in more places. llvm-svn: 94477
2010-01-26 08:03:12 +08:00
DebugLoc DL = MBB.findDebugLoc(MI);
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
}
void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
Add basic infrastructure and x86 support for preserving MachineMemOperand information when unfolding memory references. llvm-svn: 83656
2009-10-10 02:10:05 +08:00
MachineInstr::mmo_iterator MMOBegin,
MachineInstr::mmo_iterator MMOEnd,
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
SmallVectorImpl<MachineInstr*> &NewMIs) const {
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
bool isAligned = MMOBegin != MMOEnd &&
(*MMOBegin)->getAlignment() >= Alignment;
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. llvm-svn: 70211
2009-04-28 00:41:36 +08:00
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() llvm-svn: 100214
2010-04-03 04:16:16 +08:00
DebugLoc DL;
Eliminate a couple of non-DebugLoc BuildMI variants. Modify callers. llvm-svn: 64409
2009-02-13 07:08:38 +08:00
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Factor out the code to add a MachineOperand to a MachineInstrBuilder. llvm-svn: 64891
2009-02-18 13:45:50 +08:00
MIB.addOperand(Addr[i]);
Add basic infrastructure and x86 support for preserving MachineMemOperand information when unfolding memory references. llvm-svn: 83656
2009-10-10 02:10:05 +08:00
(*MIB).setMemRefs(MMOBegin, MMOEnd);
Move some more instruction creation methods from RegisterInfo into InstrInfo. llvm-svn: 45484
2008-01-02 05:11:32 +08:00
NewMIs.push_back(MIB);
}
Expand the x86 V_SET0* pseudos right after register allocation. This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. llvm-svn: 140776
2011-09-29 13:10:54 +08:00
/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
/// instruction with two undef reads of the register being defined. This is
/// used for mapping:
/// %xmm4 = V_SET0
/// to:
/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
///
static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
unsigned Reg = MI->getOperand(0).getReg();
MI->setDesc(Desc);
// MachineInstr::addOperand() will insert explicit operands before any
// implicit operands.
MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
.addReg(Reg, RegState::Undef);
// But we don't trust that.
assert(MI->getOperand(1).getReg() == Reg &&
MI->getOperand(2).getReg() == Reg && "Misplaced operand");
return true;
}
bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
switch (MI->getOpcode()) {
case X86::V_SET0:
return Expand2AddrUndef(MI, get(HasAVX ? X86::VPXORrr : X86::PXORrr));
Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot target all GR8 registers, only those in GR8_NOREX. TO enforce this, we ensure that all instructions using the EXTRACT_SUBREG are GR8_NOREX constrained. This fixes PR11088. llvm-svn: 141499
2011-10-09 02:28:28 +08:00
case X86::TEST8ri_NOREX:
MI->setDesc(get(X86::TEST8ri));
return true;
Expand the x86 V_SET0* pseudos right after register allocation. This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. llvm-svn: 140776
2011-09-29 13:10:54 +08:00
}
return false;
}
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue. - Teach spiller to modify DBG_VALUE instructions to reference spill slots. llvm-svn: 102323
2010-04-26 15:38:55 +08:00
MachineInstr*
X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
Frame index can be negative. llvm-svn: 102577
2010-04-29 09:13:30 +08:00
int FrameIx, uint64_t Offset,
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue. - Teach spiller to modify DBG_VALUE instructions to reference spill slots. llvm-svn: 102323
2010-04-26 15:38:55 +08:00
const MDNode *MDPtr,
DebugLoc DL) const {
X86AddressMode AM;
AM.BaseType = X86AddressMode::FrameIndexBase;
AM.Base.FrameIndex = FrameIx;
MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
return &*MIB;
}
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Tidy up #includes, deleting a bunch of unnecessary #includes. llvm-svn: 61715
2009-01-06 01:59:02 +08:00
const SmallVectorImpl<MachineOperand> &MOs,
Create DebugLoc information in FastISel. Several temporary methods were created. Specifically, those BuildMIs which use "DebugLoc::getUnknownLoc()". I'll remove them soon. llvm-svn: 63584
2009-02-03 08:55:04 +08:00
MachineInstr *MI,
const TargetInstrInfo &TII) {
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// Create the base instruction with the memory operand as the first part.
Create DebugLoc information in FastISel. Several temporary methods were created. Specifically, those BuildMIs which use "DebugLoc::getUnknownLoc()". I'll remove them soon. llvm-svn: 63584
2009-02-03 08:55:04 +08:00
MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
MI->getDebugLoc(), true);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstrBuilder MIB(NewMI);
unsigned NumAddrOps = MOs.size();
for (unsigned i = 0; i != NumAddrOps; ++i)
Factor out the code to add a MachineOperand to a MachineInstrBuilder. llvm-svn: 64891
2009-02-18 13:45:50 +08:00
MIB.addOperand(MOs[i]);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (NumAddrOps < 4) // FrameIndex only
Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. llvm-svn: 68645
2009-04-09 05:14:34 +08:00
addOffset(MIB, 0);
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// Loop over the rest of the ri operands, converting them over.
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
unsigned NumOps = MI->getDesc().getNumOperands()-2;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
for (unsigned i = 0; i != NumOps; ++i) {
MachineOperand &MO = MI->getOperand(i+2);
Factor out the code to add a MachineOperand to a MachineInstrBuilder. llvm-svn: 64891
2009-02-18 13:45:50 +08:00
MIB.addOperand(MO);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
Factor out the code to add a MachineOperand to a MachineInstrBuilder. llvm-svn: 64891
2009-02-18 13:45:50 +08:00
MIB.addOperand(MO);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
return MIB;
}
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
static MachineInstr *FuseInst(MachineFunction &MF,
unsigned Opcode, unsigned OpNo,
Tidy up #includes, deleting a bunch of unnecessary #includes. llvm-svn: 61715
2009-01-06 01:59:02 +08:00
const SmallVectorImpl<MachineOperand> &MOs,
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstr *MI, const TargetInstrInfo &TII) {
Create DebugLoc information in FastISel. Several temporary methods were created. Specifically, those BuildMIs which use "DebugLoc::getUnknownLoc()". I'll remove them soon. llvm-svn: 63584
2009-02-03 08:55:04 +08:00
MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
MI->getDebugLoc(), true);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstrBuilder MIB(NewMI);
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (i == OpNo) {
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
assert(MO.isReg() && "Expected to fold into reg operand!");
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
unsigned NumAddrOps = MOs.size();
for (unsigned i = 0; i != NumAddrOps; ++i)
Factor out the code to add a MachineOperand to a MachineInstrBuilder. llvm-svn: 64891
2009-02-18 13:45:50 +08:00
MIB.addOperand(MOs[i]);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (NumAddrOps < 4) // FrameIndex only
Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. llvm-svn: 68645
2009-04-09 05:14:34 +08:00
addOffset(MIB, 0);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
} else {
Factor out the code to add a MachineOperand to a MachineInstrBuilder. llvm-svn: 64891
2009-02-18 13:45:50 +08:00
MIB.addOperand(MO);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
}
return MIB;
}
static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Tidy up #includes, deleting a bunch of unnecessary #includes. llvm-svn: 61715
2009-01-06 01:59:02 +08:00
const SmallVectorImpl<MachineOperand> &MOs,
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstr *MI) {
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
2008-07-08 07:14:23 +08:00
MachineFunction &MF = *MI->getParent()->getParent();
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
unsigned NumAddrOps = MOs.size();
for (unsigned i = 0; i != NumAddrOps; ++i)
Factor out the code to add a MachineOperand to a MachineInstrBuilder. llvm-svn: 64891
2009-02-18 13:45:50 +08:00
MIB.addOperand(MOs[i]);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (NumAddrOps < 4) // FrameIndex only
Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. llvm-svn: 68645
2009-04-09 05:14:34 +08:00
addOffset(MIB, 0);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
return MIB.addImm(0);
}
MachineInstr*
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
2008-12-04 02:43:12 +08:00
X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI, unsigned i,
Move load / store folding alignment require into the table(s). llvm-svn: 75749
2009-07-15 14:10:07 +08:00
const SmallVectorImpl<MachineOperand> &MOs,
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
unsigned Size, unsigned Align) const {
Reduce casting in various tables by defining the table with the right types. llvm-svn: 116001
2010-10-08 07:08:41 +08:00
const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
bool isTwoAddrFold = false;
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
unsigned NumOps = MI->getDesc().getNumOperands();
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
bool isTwoAddr = NumOps > 1 &&
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
X86AsmPrinter doesn't know how to handle the X86II::MO_GOT_ABSOLUTE_ADDRESS flag after folding ADD32ri to ADD32mi, so don't do that. This only happens when the greedy register allocator gets itself in trouble and spills %vreg9 here: 16L %vreg9<def> = MOVPC32r 0, %ESP<imp-use>; GR32:%vreg9 48L %vreg9<def> = ADD32ri %vreg9, <es:_GLOBAL_OFFSET_TABLE_>[TF=1], %EFLAGS<imp-def,dead>; GR32:%vreg9 That should never happen, the live range should be split instead. llvm-svn: 130625
2011-05-01 07:00:05 +08:00
// FIXME: AsmPrinter doesn't know how to handle
// X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
if (MI->getOpcode() == X86::ADD32ri &&
MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
return NULL;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstr *NewMI = NULL;
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
// replacing the *two* registers with the memory location.
if (isTwoAddr && NumOps >= 2 && i < 2 &&
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
MI->getOperand(0).isReg() &&
MI->getOperand(1).isReg() &&
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
OpcodeTablePtr = &RegOp2MemOpTable2Addr;
isTwoAddrFold = true;
} else if (i == 0) { // If operand 0
Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. llvm-svn: 93229
2010-01-12 12:42:54 +08:00
if (MI->getOpcode() == X86::MOV64r0)
NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
else if (MI->getOpcode() == X86::MOV32r0)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. llvm-svn: 93229
2010-01-12 12:42:54 +08:00
else if (MI->getOpcode() == X86::MOV16r0)
NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
else if (MI->getOpcode() == X86::MOV8r0)
NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
2008-07-03 17:09:37 +08:00
if (NewMI)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
return NewMI;
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
OpcodeTablePtr = &RegOp2MemOpTable0;
} else if (i == 1) {
OpcodeTablePtr = &RegOp2MemOpTable1;
} else if (i == 2) {
OpcodeTablePtr = &RegOp2MemOpTable2;
}
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// If table selected...
if (OpcodeTablePtr) {
// Find the Opcode to fuse
Reduce casting in various tables by defining the table with the right types. llvm-svn: 116001
2010-10-08 07:08:41 +08:00
DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
OpcodeTablePtr->find(MI->getOpcode());
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (I != OpcodeTablePtr->end()) {
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
unsigned Opcode = I->second.first;
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Move load / store folding alignment require into the table(s). llvm-svn: 75749
2009-07-15 14:10:07 +08:00
if (Align < MinAlign)
return NULL;
Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index. llvm-svn: 81496
2009-09-11 09:01:31 +08:00
bool NarrowToMOV32rm = false;
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
if (Size) {
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. llvm-svn: 133944
2011-06-28 05:26:13 +08:00
unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
if (Size < RCSize) {
// Check if it's safe to fold the load. If the size of the object is
// narrower than the load width, then it's not.
if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
return NULL;
// If this is a 64-bit load, but the spill slot is 32, then we can do
// a 32-bit load which is implicitly zero-extended. This likely is due
// to liveintervalanalysis remat'ing a load from stack slot.
Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index. llvm-svn: 81496
2009-09-11 09:01:31 +08:00
if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
return NULL;
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
Opcode = X86::MOV32rm;
Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index. llvm-svn: 81496
2009-09-11 09:01:31 +08:00
NarrowToMOV32rm = true;
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
}
}
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (isTwoAddrFold)
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
else
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index. llvm-svn: 81496
2009-09-11 09:01:31 +08:00
if (NarrowToMOV32rm) {
// If this is the special case where we use a MOV32rm to load a 32-bit
// value and zero-extend the top bits. Change the destination register
// to a 32-bit one.
unsigned DstReg = NewMI->getOperand(0).getReg();
if (TargetRegisterInfo::isPhysicalRegister(DstReg))
NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
Rename X86 subregister indices to something shorter. Use the tablegen-produced enums. llvm-svn: 104493
2010-05-24 22:48:17 +08:00
X86::sub_32bit));
Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index. llvm-svn: 81496
2009-09-11 09:01:31 +08:00
else
Rename X86 subregister indices to something shorter. Use the tablegen-produced enums. llvm-svn: 104493
2010-05-24 22:48:17 +08:00
NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index. llvm-svn: 81496
2009-09-11 09:01:31 +08:00
}
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
return NewMI;
}
}
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
// No fusion
Fix a few tests llvm-svn: 108011
2010-07-10 04:43:09 +08:00
if (PrintFailedFusing && !MI->isCopy())
Change errs() to dbgs(). llvm-svn: 92653
2010-01-05 09:29:29 +08:00
dbgs() << "We failed to fuse operand " << i << " in " << *MI;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
return NULL;
}
Factor out partial register update checks for some SSE instructions. Also add the AVX versions and add comments! llvm-svn: 139854
2011-09-16 05:42:23 +08:00
/// hasPartialRegUpdate - Return true for all instructions that only update
/// the first 32 or 64-bits of the destination register and leave the rest
/// unmodified. This can be used to avoid folding loads if the instructions
/// only update part of the destination register, and the non-updated part is
/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
/// instructions breaks the partial register dependency and it can improve
/// performance. e.g.:
///
/// movss (%rdi), %xmm0
/// cvtss2sd %xmm0, %xmm0
///
/// Instead of
/// cvtss2sd (%rdi), %xmm0
///
Add a fixme note! llvm-svn: 139872
2011-09-16 07:04:24 +08:00
/// FIXME: This should be turned into a TSFlags.
///
Factor out partial register update checks for some SSE instructions. Also add the AVX versions and add comments! llvm-svn: 139854
2011-09-16 05:42:23 +08:00
static bool hasPartialRegUpdate(unsigned Opcode) {
switch (Opcode) {
case X86::CVTSD2SSrr:
case X86::Int_CVTSD2SSrr:
case X86::CVTSS2SDrr:
case X86::Int_CVTSS2SDrr:
case X86::RCPSSr:
case X86::RCPSSr_Int:
case X86::ROUNDSDr:
case X86::ROUNDSSr:
case X86::RSQRTSSr:
case X86::RSQRTSSr_Int:
case X86::SQRTSSr:
case X86::SQRTSSr_Int:
// AVX encoded versions
case X86::VCVTSD2SSrr:
case X86::Int_VCVTSD2SSrr:
case X86::VCVTSS2SDrr:
case X86::Int_VCVTSS2SDrr:
case X86::VRCPSSr:
case X86::VROUNDSDr:
case X86::VROUNDSSr:
case X86::VRSQRTSSr:
case X86::VSQRTSSr:
return true;
}
return false;
}
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
2008-12-04 02:43:12 +08:00
MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI,
Move load / store folding alignment require into the table(s). llvm-svn: 75749
2009-07-15 14:10:07 +08:00
const SmallVectorImpl<unsigned> &Ops,
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
2008-12-04 02:43:12 +08:00
int FrameIndex) const {
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
// Check switch flag
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (NoFusing) return NULL;
Factor out partial register update checks for some SSE instructions. Also add the AVX versions and add comments! llvm-svn: 139854
2011-09-16 05:42:23 +08:00
// Unless optimizing for size, don't fold to avoid partial
// register update stalls
if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
hasPartialRegUpdate(MI->getOpcode()))
return 0;
On recent Intel u-arch's, folding loads into some unary SSE instructions can be non-optimal. To be precise, we should avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g. movss (%rdi), %xmm0 cvtss2sd %xmm0, %xmm0 instead of cvtss2sd (%rdi), %xmm0 An alternative method to break dependency is to clear the register first. e.g. xorps %xmm0, %xmm0 cvtss2sd (%rdi), %xmm0 llvm-svn: 91672
2009-12-18 15:40:29 +08:00
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
2008-02-09 05:20:40 +08:00
const MachineFrameInfo *MFI = MF.getFrameInfo();
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
unsigned Size = MFI->getObjectSize(FrameIndex);
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
2008-02-09 05:20:40 +08:00
unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
unsigned NewOpc = 0;
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
unsigned RCSize = 0;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
switch (MI->getOpcode()) {
default: return NULL;
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
When converting a test to a cmp to fold a load, use the cmp that has an 8-bit immediate field rather than one with a wider immediate field. llvm-svn: 104064
2010-05-19 05:42:03 +08:00
case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
// Check if it's safe to fold the load. If the size of the object is
// narrower than the load width, then it's not.
if (Size < RCSize)
return NULL;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// Change to CMPXXri r, 0 first.
rename MachineInstr::setInstrDescriptor -> setDesc llvm-svn: 45871
2008-01-12 02:10:50 +08:00
MI->setDesc(get(NewOpc));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MI->getOperand(1).ChangeToImmediate(0);
} else if (Ops.size() != 1)
return NULL;
SmallVector<MachineOperand,4> MOs;
MOs.push_back(MachineOperand::CreateFI(FrameIndex));
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
2008-12-04 02:43:12 +08:00
MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI,
Move load / store folding alignment require into the table(s). llvm-svn: 75749
2009-07-15 14:10:07 +08:00
const SmallVectorImpl<unsigned> &Ops,
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
2008-12-04 02:43:12 +08:00
MachineInstr *LoadMI) const {
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
// Check switch flag
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (NoFusing) return NULL;
Factor out partial register update checks for some SSE instructions. Also add the AVX versions and add comments! llvm-svn: 139854
2011-09-16 05:42:23 +08:00
// Unless optimizing for size, don't fold to avoid partial
// register update stalls
if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
hasPartialRegUpdate(MI->getOpcode()))
return 0;
On recent Intel u-arch's, folding loads into some unary SSE instructions can be non-optimal. To be precise, we should avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g. movss (%rdi), %xmm0 cvtss2sd %xmm0, %xmm0 instead of cvtss2sd (%rdi), %xmm0 An alternative method to break dependency is to clear the register first. e.g. xorps %xmm0, %xmm0 cvtss2sd (%rdi), %xmm0 llvm-svn: 91672
2009-12-18 15:40:29 +08:00
Add a utility function to MachineInstr for testing whether an instruction has exactly one MachineMemOperand, and change some X86 lowering code to make use of it. llvm-svn: 53498
2008-07-12 08:10:52 +08:00
// Determine the alignment of the load.
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
2008-02-09 05:20:40 +08:00
unsigned Alignment = 0;
Add a utility function to MachineInstr for testing whether an instruction has exactly one MachineMemOperand, and change some X86 lowering code to make use of it. llvm-svn: 53498
2008-07-12 08:10:52 +08:00
if (LoadMI->hasOneMemOperand())
Improve MachineMemOperand handling. - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
2009-09-26 04:36:54 +08:00
Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
else
switch (LoadMI->getOpcode()) {
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. - Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too. - Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX. - Add a testcase for a simple 128-bit zero vector creation. llvm-svn: 110946
2010-08-13 04:20:53 +08:00
case X86::AVX_SET0PSY:
case X86::AVX_SET0PDY:
Alignment = 32;
break;
Expand the x86 V_SET0* pseudos right after register allocation. This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. llvm-svn: 140776
2011-09-29 13:10:54 +08:00
case X86::V_SET0:
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
case X86::V_SETALLONES:
Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128 This also fixes PR10452 llvm-svn: 136004
2011-07-26 07:05:32 +08:00
case X86::AVX_SETALLONES:
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
Alignment = 16;
break;
case X86::FsFLD0SD:
Add support for AVX to materialize +0.0 when doing scalar FP. llvm-svn: 121415
2010-12-10 05:43:51 +08:00
case X86::VFsFLD0SD:
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
Alignment = 8;
break;
case X86::FsFLD0SS:
Add support for AVX to materialize +0.0 when doing scalar FP. llvm-svn: 121415
2010-12-10 05:43:51 +08:00
case X86::VFsFLD0SS:
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
Alignment = 4;
break;
default:
PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this. llvm-svn: 132826
2011-06-10 09:13:01 +08:00
return 0;
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
}
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
unsigned NewOpc = 0;
switch (MI->getOpcode()) {
default: return NULL;
case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Teach mode load folding and unfolding code about CMP32ri8 and friends. llvm-svn: 104068
2010-05-19 05:54:15 +08:00
case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
// Change to CMPXXri r, 0 first.
rename MachineInstr::setInstrDescriptor -> setDesc llvm-svn: 45871
2008-01-12 02:10:50 +08:00
MI->setDesc(get(NewOpc));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MI->getOperand(1).ChangeToImmediate(0);
} else if (Ops.size() != 1)
return NULL;
Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk. When a register is defined by a partial load: %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234 That load cannot be folded into an instruction using the full 64-bit register. It would become a 64-bit load. This is related to the recent change to have isLoadFromStackSlot return false on a sub-register load. llvm-svn: 110874
2010-08-12 07:08:22 +08:00
// Make sure the subregisters match.
// Otherwise we risk changing the size of the load.
if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
return NULL;
add some long-overdue enums to refer to the parts of the 5-operand X86 memory operand. llvm-svn: 107925
2010-07-09 06:41:28 +08:00
SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
switch (LoadMI->getOpcode()) {
Expand the x86 V_SET0* pseudos right after register allocation. This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. llvm-svn: 140776
2011-09-29 13:10:54 +08:00
case X86::V_SET0:
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
case X86::V_SETALLONES:
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. - Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too. - Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX. - Add a testcase for a simple 128-bit zero vector creation. llvm-svn: 110946
2010-08-13 04:20:53 +08:00
case X86::AVX_SET0PSY:
case X86::AVX_SET0PDY:
Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128 This also fixes PR10452 llvm-svn: 136004
2011-07-26 07:05:32 +08:00
case X86::AVX_SETALLONES:
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
case X86::FsFLD0SD:
Fix PR10422 by adding the necessary AVX UCOMISD memory versions to load folding logic llvm-svn: 135801
2011-07-23 04:53:20 +08:00
case X86::FsFLD0SS:
case X86::VFsFLD0SD:
case X86::VFsFLD0SS: {
Expand the x86 V_SET0* pseudos right after register allocation. This also makes it possible to reduce the number of pseudo instructions and get rid of the encoding information. llvm-svn: 140776
2011-09-29 13:10:54 +08:00
// Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
// Create a constant-pool entry and operands to load from it.
Don't try to fold V_SET0 and V_SETALLONES to loads in medium and large code models. llvm-svn: 98042
2010-03-09 11:01:40 +08:00
// Medium and large mode can't fold loads this way.
if (TM.getCodeModel() != CodeModel::Small &&
TM.getCodeModel() != CodeModel::Kernel)
return NULL;
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
// x86-32 PIC requires a PIC base register for constant pools.
unsigned PICBase = 0;
Silence warning in Linux builds: X86InstrInfo.cpp:2272: warning: suggest explicit braces to avoid ambiguous 'else' llvm-svn: 76105
2009-07-17 05:24:13 +08:00
if (TM.getRelocationModel() == Reloc::PIC_) {
With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction. llvm-svn: 76094
2009-07-17 02:44:05 +08:00
if (TM.getSubtarget<X86Subtarget>().is64Bit())
PICBase = X86::RIP;
Silence warning in Linux builds: X86InstrInfo.cpp:2272: warning: suggest explicit braces to avoid ambiguous 'else' llvm-svn: 76105
2009-07-17 05:24:13 +08:00
else
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
// FIXME: PICBase = getGlobalBaseReg(&MF);
With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction. llvm-svn: 76094
2009-07-17 02:44:05 +08:00
// This doesn't work for several reasons.
// 1. GlobalBaseReg may have been spilled.
// 2. It may not be live at MI.
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
return NULL;
Silence warning in Linux builds: X86InstrInfo.cpp:2272: warning: suggest explicit braces to avoid ambiguous 'else' llvm-svn: 76105
2009-07-17 05:24:13 +08:00
}
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
// Create a constant-pool entry.
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
MachineConstantPool &MCP = *MF.getConstantPool();
land David Blaikie's patch to de-constify Type, with a few tweaks. llvm-svn: 135375
2011-07-18 12:54:35 +08:00
Type *Ty;
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. - Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too. - Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX. - Add a testcase for a simple 128-bit zero vector creation. llvm-svn: 110946
2010-08-13 04:20:53 +08:00
unsigned Opc = LoadMI->getOpcode();
Add support for AVX to materialize +0.0 when doing scalar FP. llvm-svn: 121415
2010-12-10 05:43:51 +08:00
if (Opc == X86::FsFLD0SS || Opc == X86::VFsFLD0SS)
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
Ty = Type::getFloatTy(MF.getFunction()->getContext());
Add support for AVX to materialize +0.0 when doing scalar FP. llvm-svn: 121415
2010-12-10 05:43:51 +08:00
else if (Opc == X86::FsFLD0SD || Opc == X86::VFsFLD0SD)
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
Ty = Type::getDoubleTy(MF.getFunction()->getContext());
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. - Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too. - Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX. - Add a testcase for a simple 128-bit zero vector creation. llvm-svn: 110946
2010-08-13 04:20:53 +08:00
else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
else
Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128 This also fixes PR10452 llvm-svn: 136004
2011-07-26 07:05:32 +08:00
bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES);
const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
Constant::getNullValue(Ty);
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
// Create operands to load from the constant pool entry.
MOs.push_back(MachineOperand::CreateReg(PICBase, false));
MOs.push_back(MachineOperand::CreateImm(1));
MOs.push_back(MachineOperand::CreateReg(0, false));
MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. llvm-svn: 68645
2009-04-09 05:14:34 +08:00
MOs.push_back(MachineOperand::CreateReg(0, false));
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
break;
}
default: {
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
// Folding a normal load. Just copy the load's address operands.
unsigned NumOps = LoadMI->getDesc().getNumOperands();
add some long-overdue enums to refer to the parts of the 5-operand X86 memory operand. llvm-svn: 107925
2010-07-09 06:41:28 +08:00
for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
MOs.push_back(LoadMI->getOperand(i));
Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool loads in order to reduce register pressure. llvm-svn: 82470
2009-09-22 02:30:38 +08:00
break;
}
Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). llvm-svn: 60461
2008-12-03 13:21:24 +08:00
}
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not safe. This can happen we a subreg_to_reg 0 has been coalesced. One exception is when the instruction that folds the load is a move, then we can simply turn it into a 32-bit load from the stack slot. rdar://7170444 llvm-svn: 81494
2009-09-11 08:39:26 +08:00
return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
Const-ify several TargetInstrInfo methods. llvm-svn: 57622
2008-10-16 09:49:15 +08:00
bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops) const {
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
// Check switch flag
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (NoFusing) return 0;
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
switch (MI->getOpcode()) {
default: return false;
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
case X86::TEST8rr:
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
case X86::TEST16rr:
case X86::TEST32rr:
case X86::TEST64rr:
return true;
X86AsmPrinter doesn't know how to handle the X86II::MO_GOT_ABSOLUTE_ADDRESS flag after folding ADD32ri to ADD32mi, so don't do that. This only happens when the greedy register allocator gets itself in trouble and spills %vreg9 here: 16L %vreg9<def> = MOVPC32r 0, %ESP<imp-use>; GR32:%vreg9 48L %vreg9<def> = ADD32ri %vreg9, <es:_GLOBAL_OFFSET_TABLE_>[TF=1], %EFLAGS<imp-def,dead>; GR32:%vreg9 That should never happen, the live range should be split instead. llvm-svn: 130625
2011-05-01 07:00:05 +08:00
case X86::ADD32ri:
// FIXME: AsmPrinter doesn't know how to handle
// X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
return false;
break;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
}
if (Ops.size() != 1)
return false;
unsigned OpNum = Ops[0];
unsigned Opc = MI->getOpcode();
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07 15:27:27 +08:00
unsigned NumOps = MI->getDesc().getNumOperands();
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
bool isTwoAddr = NumOps > 1 &&
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
// replacing the *two* registers with the memory location.
Reduce casting in various tables by defining the table with the right types. llvm-svn: 116001
2010-10-08 07:08:41 +08:00
const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
OpcodeTablePtr = &RegOp2MemOpTable2Addr;
} else if (OpNum == 0) { // If operand 0
switch (Opc) {
reapply r75408, which eliminates MOV64r0 in favor of using MOV32r0 + subregs to do the same thing. This should work now that PR4544 is fixed. Thanks Evan! llvm-svn: 75671
2009-07-15 04:19:57 +08:00
case X86::MOV8r0:
Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. llvm-svn: 93229
2010-01-12 12:42:54 +08:00
case X86::MOV16r0:
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
case X86::MOV32r0:
Reduce casting in various tables by defining the table with the right types. llvm-svn: 116001
2010-10-08 07:08:41 +08:00
case X86::MOV64r0: return true;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
default: break;
}
OpcodeTablePtr = &RegOp2MemOpTable0;
} else if (OpNum == 1) {
OpcodeTablePtr = &RegOp2MemOpTable1;
} else if (OpNum == 2) {
OpcodeTablePtr = &RegOp2MemOpTable2;
}
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
reapply the patch reverted in r116033: "Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'" With a critical fix: the add pseudos clobber EFLAGS. llvm-svn: 116039
2010-10-08 11:54:52 +08:00
if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
return true;
Automatically fold COPY instructions into stack load/store. llvm-svn: 108012
2010-07-10 04:43:13 +08:00
return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
SmallVectorImpl<MachineInstr*> &NewMIs) const {
Reduce casting in various tables by defining the table with the right types. llvm-svn: 116001
2010-10-08 07:08:41 +08:00
DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
MemOp2RegOpTable.find(MI->getOpcode());
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (I == MemOp2RegOpTable.end())
return false;
unsigned Opc = I->second.first;
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
unsigned Index = I->second.second & TB_INDEX_MASK;
bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (UnfoldLoad && !FoldedLoad)
return false;
UnfoldLoad &= FoldedLoad;
if (UnfoldStore && !FoldedStore)
return false;
UnfoldStore &= FoldedStore;
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
const MCInstrDesc &MCID = get(Opc);
const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
- Two-address pass should not assume unfolding is always successful. - X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. llvm-svn: 107509
2010-07-03 04:36:18 +08:00
if (!MI->hasOneMemOperand() &&
RC == &X86::VR128RegClass &&
!TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
// Without memoperands, loadRegFromAddr and storeRegToStackSlot will
// conservatively assume the address is unaligned. That's bad for
// performance.
return false;
add some long-overdue enums to refer to the parts of the 5-operand X86 memory operand. llvm-svn: 107925
2010-07-09 06:41:28 +08:00
SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
SmallVector<MachineOperand,2> BeforeOps;
SmallVector<MachineOperand,2> AfterOps;
SmallVector<MachineOperand,4> ImpOps;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &Op = MI->getOperand(i);
add some long-overdue enums to refer to the parts of the 5-operand X86 memory operand. llvm-svn: 107925
2010-07-09 06:41:28 +08:00
if (i >= Index && i < Index + X86::AddrNumOperands)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AddrOps.push_back(Op);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
else if (Op.isReg() && Op.isImplicit())
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
ImpOps.push_back(Op);
else if (i < Index)
BeforeOps.push_back(Op);
else if (i > Index)
AfterOps.push_back(Op);
}
// Emit the load instruction.
if (UnfoldLoad) {
Add basic infrastructure and x86 support for preserving MachineMemOperand information when unfolding memory references. llvm-svn: 83656
2009-10-10 02:10:05 +08:00
std::pair<MachineInstr::mmo_iterator,
MachineInstr::mmo_iterator> MMOs =
MF.extractLoadMemRefs(MI->memoperands_begin(),
MI->memoperands_end());
loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (UnfoldStore) {
// Address operands cannot be marked isKill.
add some long-overdue enums to refer to the parts of the 5-operand X86 memory operand. llvm-svn: 107925
2010-07-09 06:41:28 +08:00
for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineOperand &MO = NewMIs[0]->getOperand(i);
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-10-03 23:45:36 +08:00
if (MO.isReg())
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MO.setIsKill(false);
}
}
}
// Emit the data processing instruction.
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MachineInstrBuilder MIB(DataMI);
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (FoldedStore)
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
MIB.addReg(Reg, RegState::Define);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
Factor out the code to add a MachineOperand to a MachineInstrBuilder. llvm-svn: 64891
2009-02-18 13:45:50 +08:00
MIB.addOperand(BeforeOps[i]);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (FoldedLoad)
MIB.addReg(Reg);
for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
Factor out the code to add a MachineOperand to a MachineInstrBuilder. llvm-svn: 64891
2009-02-18 13:45:50 +08:00
MIB.addOperand(AfterOps[i]);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
MachineOperand &MO = ImpOps[i];
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-05-14 05:33:08 +08:00
MIB.addReg(MO.getReg(),
getDefRegState(MO.isDef()) |
RegState::Implicit |
getKillRegState(MO.isKill()) |
Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. llvm-svn: 74518
2009-06-30 16:49:04 +08:00
getDeadRegState(MO.isDead()) |
getUndefRegState(MO.isUndef()));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
// Change CMP32ri r, 0 back to TEST32rr r, r, etc.
unsigned NewOpc = 0;
switch (DataMI->getOpcode()) {
default: break;
case X86::CMP64ri32:
Teach mode load folding and unfolding code about CMP32ri8 and friends. llvm-svn: 104068
2010-05-19 05:54:15 +08:00
case X86::CMP64ri8:
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
case X86::CMP32ri:
Teach mode load folding and unfolding code about CMP32ri8 and friends. llvm-svn: 104068
2010-05-19 05:54:15 +08:00
case X86::CMP32ri8:
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
case X86::CMP16ri:
Teach mode load folding and unfolding code about CMP32ri8 and friends. llvm-svn: 104068
2010-05-19 05:54:15 +08:00
case X86::CMP16ri8:
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
case X86::CMP8ri: {
MachineOperand &MO0 = DataMI->getOperand(0);
MachineOperand &MO1 = DataMI->getOperand(1);
if (MO1.getImm() == 0) {
switch (DataMI->getOpcode()) {
default: break;
Teach mode load folding and unfolding code about CMP32ri8 and friends. llvm-svn: 104068
2010-05-19 05:54:15 +08:00
case X86::CMP64ri8:
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Teach mode load folding and unfolding code about CMP32ri8 and friends. llvm-svn: 104068
2010-05-19 05:54:15 +08:00
case X86::CMP32ri8:
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Teach mode load folding and unfolding code about CMP32ri8 and friends. llvm-svn: 104068
2010-05-19 05:54:15 +08:00
case X86::CMP16ri8:
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
}
rename MachineInstr::setInstrDescriptor -> setDesc llvm-svn: 45871
2008-01-12 02:10:50 +08:00
DataMI->setDesc(get(NewOpc));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
MO1.ChangeToRegister(MO0.getReg(), false);
}
}
}
NewMIs.push_back(DataMI);
// Emit the store instruction.
if (UnfoldStore) {
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI);
Add basic infrastructure and x86 support for preserving MachineMemOperand information when unfolding memory references. llvm-svn: 83656
2009-10-10 02:10:05 +08:00
std::pair<MachineInstr::mmo_iterator,
MachineInstr::mmo_iterator> MMOs =
MF.extractStoreMemRefs(MI->memoperands_begin(),
MI->memoperands_end());
storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
return true;
}
bool
X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Propagate DebugLoc info for spiller call-backs. llvm-svn: 64329
2009-02-12 05:51:19 +08:00
SmallVectorImpl<SDNode*> &NewNodes) const {
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk replacement of multiple values. This is slightly more efficient than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically could be optimized even further. However, an important property of this new function is that it handles the case where the source value set and destination value set overlap. This makes it feasible for isel to use SelectNodeTo in many very common cases, which is advantageous because SelectNodeTo avoids a temporary node and it doesn't require CSEMap updates for users of values that don't change position. Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to handle operand lists more efficiently, and to correctly handle a number of corner cases to which its new wider use exposes it. This commit also includes a change to the encoding of post-isel opcodes in SDNodes; now instead of being sandwiched between the target-independent pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel opcodes are now represented as negative values. This makes it possible to test if an opcode is pre-isel or post-isel without having to know the size of the current target's post-isel instruction set. These changes speed up llc overall by 3% and reduce memory usage by 10% on the InstructionCombining.cpp testcase with -fast and -regalloc=local. llvm-svn: 53728
2008-07-18 03:10:17 +08:00
if (!N->isMachineOpcode())
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
return false;
Reduce casting in various tables by defining the table with the right types. llvm-svn: 116001
2010-10-08 07:08:41 +08:00
DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
MemOp2RegOpTable.find(N->getMachineOpcode());
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (I == MemOp2RegOpTable.end())
return false;
unsigned Opc = I->second.first;
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
unsigned Index = I->second.second & TB_INDEX_MASK;
bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
bool FoldedStore = I->second.second & TB_FOLDED_STORE;
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
const MCInstrDesc &MCID = get(Opc);
const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
unsigned NumDefs = MCID.NumDefs;
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
std::vector<SDValue> AddrOps;
std::vector<SDValue> BeforeOps;
std::vector<SDValue> AfterOps;
Get rid of one more non-DebugLoc getNode and its corresponding getTargetNode. Lots of caller changes. llvm-svn: 63904
2009-02-06 09:31:28 +08:00
DebugLoc dl = N->getDebugLoc();
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
unsigned NumOps = N->getNumOperands();
Improve MachineMemOperand handling. - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
2009-09-26 04:36:54 +08:00
for (unsigned i = 0; i != NumOps-1; ++i) {
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue Op = N->getOperand(i);
add some long-overdue enums to refer to the parts of the 5-operand X86 memory operand. llvm-svn: 107925
2010-07-09 06:41:28 +08:00
if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AddrOps.push_back(Op);
When using MachineInstr operand indices on SDNodes, the number of MachineInstr def operands must be subtracted out. This bug was uncovered by the recent x86 EFLAGS optimization. Before that, the only instructions that ever needed unfolding were things like CMP32rm, where NumDefs is zero. llvm-svn: 66056
2009-03-05 03:23:38 +08:00
else if (i < Index-NumDefs)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
BeforeOps.push_back(Op);
When using MachineInstr operand indices on SDNodes, the number of MachineInstr def operands must be subtracted out. This bug was uncovered by the recent x86 EFLAGS optimization. Before that, the only instructions that ever needed unfolding were things like CMP32rm, where NumDefs is zero. llvm-svn: 66056
2009-03-05 03:23:38 +08:00
else if (i > Index-NumDefs)
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AfterOps.push_back(Op);
}
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue Chain = N->getOperand(NumOps-1);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AddrOps.push_back(Chain);
// Emit the load instruction.
SDNode *Load = 0;
Add basic infrastructure and x86 support for preserving MachineMemOperand information when unfolding memory references. llvm-svn: 83656
2009-10-10 02:10:05 +08:00
MachineFunction &MF = DAG.getMachineFunction();
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (FoldedLoad) {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT = *RC->vt_begin();
- Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. - Mark MOVUPSrm re-materializable. llvm-svn: 88974
2009-11-17 05:56:03 +08:00
std::pair<MachineInstr::mmo_iterator,
MachineInstr::mmo_iterator> MMOs =
MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
cast<MachineSDNode>(N)->memoperands_end());
- Two-address pass should not assume unfolding is always successful. - X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. llvm-svn: 107509
2010-07-03 04:36:18 +08:00
if (!(*MMOs.first) &&
RC == &X86::VR128RegClass &&
!TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
// Do not introduce a slow unaligned load.
return false;
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
bool isAligned = (*MMOs.first) &&
(*MMOs.first)->getAlignment() >= Alignment;
Rename getTargetNode to getMachineNode, for consistency with the naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. llvm-svn: 82790
2009-09-26 02:54:59 +08:00
Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
VT, MVT::Other, &AddrOps[0], AddrOps.size());
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
NewNodes.push_back(Load);
Add basic infrastructure and x86 support for preserving MachineMemOperand information when unfolding memory references. llvm-svn: 83656
2009-10-10 02:10:05 +08:00
// Preserve memory reference information.
cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
// Emit the data processing instruction.
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
std::vector<EVT> VTs;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
const TargetRegisterClass *DstRC = 0;
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
if (MCID.getNumDefs() > 0) {
DstRC = getRegClass(MCID, 0, &RI);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
VTs.push_back(*DstRC->vt_begin());
}
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT = N->getValueType(i);
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
2011-06-29 03:10:37 +08:00
if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
VTs.push_back(VT);
}
if (Load)
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
BeforeOps.push_back(SDValue(Load, 0));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
Rename getTargetNode to getMachineNode, for consistency with the naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. llvm-svn: 82790
2009-09-26 02:54:59 +08:00
SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
BeforeOps.size());
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
NewNodes.push_back(NewNode);
// Emit the store instruction.
if (FoldedStore) {
AddrOps.pop_back();
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
AddrOps.push_back(SDValue(NewNode, 0));
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
AddrOps.push_back(Chain);
- Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. - Mark MOVUPSrm re-materializable. llvm-svn: 88974
2009-11-17 05:56:03 +08:00
std::pair<MachineInstr::mmo_iterator,
MachineInstr::mmo_iterator> MMOs =
MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
cast<MachineSDNode>(N)->memoperands_end());
- Two-address pass should not assume unfolding is always successful. - X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. llvm-svn: 107509
2010-07-03 04:36:18 +08:00
if (!(*MMOs.first) &&
RC == &X86::VR128RegClass &&
!TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
// Do not introduce a slow unaligned store.
return false;
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
bool isAligned = (*MMOs.first) &&
(*MMOs.first)->getAlignment() >= Alignment;
Rename getTargetNode to getMachineNode, for consistency with the naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. llvm-svn: 82790
2009-09-26 02:54:59 +08:00
SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
isAligned, TM),
dl, MVT::Other,
&AddrOps[0], AddrOps.size());
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
NewNodes.push_back(Store);
Add basic infrastructure and x86 support for preserving MachineMemOperand information when unfolding memory references. llvm-svn: 83656
2009-10-10 02:10:05 +08:00
// Preserve memory reference information.
cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
}
return true;
}
unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Fix MachineLICM to use the correct virtual register class when unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the opcode of the original operation without the load, not the load itself, MachineLICM needs to know the operand index in order to get the correct register class. Extend getOpcodeAfterMemoryUnfold to return this information. llvm-svn: 85622
2009-10-31 06:18:41 +08:00
bool UnfoldLoad, bool UnfoldStore,
unsigned *LoadRegIndex) const {
Reduce casting in various tables by defining the table with the right types. llvm-svn: 116001
2010-10-08 07:08:41 +08:00
DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
MemOp2RegOpTable.find(Opc);
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (I == MemOp2RegOpTable.end())
return 0;
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
if (UnfoldLoad && !FoldedLoad)
return 0;
if (UnfoldStore && !FoldedStore)
return 0;
Fix MachineLICM to use the correct virtual register class when unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the opcode of the original operation without the load, not the load itself, MachineLICM needs to know the operand index in order to get the correct register class. Extend getOpcodeAfterMemoryUnfold to return this information. llvm-svn: 85622
2009-10-31 06:18:41 +08:00
if (LoadRegIndex)
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
2011-09-09 02:35:57 +08:00
*LoadRegIndex = I->second.second & TB_INDEX_MASK;
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... llvm-svn: 45672
2008-01-07 09:35:02 +08:00
return I->second.first;
}
Add two target hooks to determine whether two loads are near and should be scheduled together. llvm-svn: 94147
2010-01-22 11:34:51 +08:00
bool
X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
int64_t &Offset1, int64_t &Offset2) const {
if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
return false;
unsigned Opc1 = Load1->getMachineOpcode();
unsigned Opc2 = Load2->getMachineOpcode();
switch (Opc1) {
default: return false;
case X86::MOV8rm:
case X86::MOV16rm:
case X86::MOV32rm:
case X86::MOV64rm:
case X86::LD_Fp32m:
case X86::LD_Fp64m:
case X86::LD_Fp80m:
case X86::MOVSSrm:
case X86::MOVSDrm:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
case X86::FsMOVAPSrm:
case X86::FsMOVAPDrm:
case X86::MOVAPSrm:
case X86::MOVUPSrm:
case X86::MOVAPDrm:
case X86::MOVDQArm:
case X86::MOVDQUrm:
Add the remaining AVX versions of instructions to X86InstrInfo, this time for describing high latency ones and for recognizting loads from the same base pointer llvm-svn: 139864
2011-09-16 06:15:52 +08:00
// AVX load instructions
case X86::VMOVSSrm:
case X86::VMOVSDrm:
case X86::FsVMOVAPSrm:
case X86::FsVMOVAPDrm:
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
case X86::VMOVAPSrm:
case X86::VMOVUPSrm:
case X86::VMOVAPDrm:
case X86::VMOVDQArm:
case X86::VMOVDQUrm:
Add 256-bit load/store recognition and matching in several places. llvm-svn: 135171
2011-07-15 02:50:58 +08:00
case X86::VMOVAPSYrm:
case X86::VMOVUPSYrm:
case X86::VMOVAPDYrm:
case X86::VMOVDQAYrm:
case X86::VMOVDQUYrm:
Add two target hooks to determine whether two loads are near and should be scheduled together. llvm-svn: 94147
2010-01-22 11:34:51 +08:00
break;
}
switch (Opc2) {
default: return false;
case X86::MOV8rm:
case X86::MOV16rm:
case X86::MOV32rm:
case X86::MOV64rm:
case X86::LD_Fp32m:
case X86::LD_Fp64m:
case X86::LD_Fp80m:
case X86::MOVSSrm:
case X86::MOVSDrm:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
case X86::FsMOVAPSrm:
case X86::FsMOVAPDrm:
case X86::MOVAPSrm:
case X86::MOVUPSrm:
case X86::MOVAPDrm:
case X86::MOVDQArm:
case X86::MOVDQUrm:
Add the remaining AVX versions of instructions to X86InstrInfo, this time for describing high latency ones and for recognizting loads from the same base pointer llvm-svn: 139864
2011-09-16 06:15:52 +08:00
// AVX load instructions
case X86::VMOVSSrm:
case X86::VMOVSDrm:
case X86::FsVMOVAPSrm:
case X86::FsVMOVAPDrm:
Teach the foldable tables about 128-bit AVX instructions and make the alignment check for 256-bit classes more strict. There're no testcases but we catch more folding cases for AVX while running single and multi sources in the llvm testsuite. Since some 128-bit AVX instructions have different number of operands than their SSE counterparts, they are placed in different tables. 256-bit AVX instructions should also be added in the table soon. And there a few more 128-bit versions to handled, which should come in the following commits. llvm-svn: 139687
2011-09-14 10:36:58 +08:00
case X86::VMOVAPSrm:
case X86::VMOVUPSrm:
case X86::VMOVAPDrm:
case X86::VMOVDQArm:
case X86::VMOVDQUrm:
Add 256-bit load/store recognition and matching in several places. llvm-svn: 135171
2011-07-15 02:50:58 +08:00
case X86::VMOVAPSYrm:
case X86::VMOVUPSYrm:
case X86::VMOVAPDYrm:
case X86::VMOVDQAYrm:
case X86::VMOVDQUYrm:
Add two target hooks to determine whether two loads are near and should be scheduled together. llvm-svn: 94147
2010-01-22 11:34:51 +08:00
break;
}
// Check if chain operands and base addresses match.
if (Load1->getOperand(0) != Load2->getOperand(0) ||
Load1->getOperand(5) != Load2->getOperand(5))
return false;
// Segment operands should match as well.
if (Load1->getOperand(4) != Load2->getOperand(4))
return false;
// Scale should be 1, Index should be Reg0.
if (Load1->getOperand(1) == Load2->getOperand(1) &&
Load1->getOperand(2) == Load2->getOperand(2)) {
if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
return false;
// Now let's examine the displacements.
if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
isa<ConstantSDNode>(Load2->getOperand(3))) {
Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
return true;
}
}
return false;
}
bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
int64_t Offset1, int64_t Offset2,
unsigned NumLoads) const {
assert(Offset2 > Offset1);
if ((Offset2 - Offset1) / 8 > 64)
return false;
unsigned Opc1 = Load1->getMachineOpcode();
unsigned Opc2 = Load2->getMachineOpcode();
if (Opc1 != Opc2)
return false; // FIXME: overly conservative?
switch (Opc1) {
default: break;
case X86::LD_Fp32m:
case X86::LD_Fp64m:
case X86::LD_Fp80m:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
return false;
}
EVT VT = Load1->getValueType(0);
switch (VT.getSimpleVT().SimpleTy) {
Fix the formatting of the switch statement and add a missing break. llvm-svn: 106586
2010-06-23 06:16:17 +08:00
default:
Add two target hooks to determine whether two loads are near and should be scheduled together. llvm-svn: 94147
2010-01-22 11:34:51 +08:00
// XMM registers. In 64-bit mode we can be a bit more aggressive since we
// have 16 of them to play with.
if (TM.getSubtargetImpl()->is64Bit()) {
if (NumLoads >= 3)
return false;
Fix the formatting of the switch statement and add a missing break. llvm-svn: 106586
2010-06-23 06:16:17 +08:00
} else if (NumLoads) {
Add two target hooks to determine whether two loads are near and should be scheduled together. llvm-svn: 94147
2010-01-22 11:34:51 +08:00
return false;
Fix the formatting of the switch statement and add a missing break. llvm-svn: 106586
2010-06-23 06:16:17 +08:00
}
Add two target hooks to determine whether two loads are near and should be scheduled together. llvm-svn: 94147
2010-01-22 11:34:51 +08:00
break;
case MVT::i8:
case MVT::i16:
case MVT::i32:
case MVT::i64:
Be more conservative with clustering f32 / f64 loads. llvm-svn: 94254
2010-01-23 07:49:11 +08:00
case MVT::f32:
case MVT::f64:
Add two target hooks to determine whether two loads are near and should be scheduled together. llvm-svn: 94147
2010-01-22 11:34:51 +08:00
if (NumLoads)
return false;
Fix the formatting of the switch statement and add a missing break. llvm-svn: 106586
2010-06-23 06:16:17 +08:00
break;
Add two target hooks to determine whether two loads are near and should be scheduled together. llvm-svn: 94147
2010-01-22 11:34:51 +08:00
}
return true;
}
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
bool X86InstrInfo::
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
2008-08-15 06:49:33 +08:00
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Implement support for branch condition reversal. llvm-svn: 31099
2006-10-21 13:52:40 +08:00
assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Use static_cast instead of C style cast. llvm-svn: 55552
2008-08-30 07:21:31 +08:00
X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Optimized FCMP_OEQ and FCMP_UNE for x86. Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. llvm-svn: 57873
2008-10-21 11:29:32 +08:00
if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
return true;
Use static_cast instead of C style cast. llvm-svn: 55552
2008-08-30 07:21:31 +08:00
Cond[0].setImm(GetOppositeBranchCondition(CC));
Implement support for branch condition reversal. llvm-svn: 31099
2006-10-21 13:52:40 +08:00
return false;
Implement branch analysis/xform hooks required by the branch folding pass. llvm-svn: 31065
2006-10-21 01:42:20 +08:00
}
For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. llvm-svn: 58230
2008-10-27 15:14:50 +08:00
bool X86InstrInfo::
Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook. llvm-svn: 63936
2009-02-07 01:17:30 +08:00
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
// FIXME: Return false for x87 stack register classes for now. We can't
For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. llvm-svn: 58230
2008-10-27 15:14:50 +08:00
// allow any loads of these registers before FpGet_ST0_80.
Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook. llvm-svn: 63936
2009-02-07 01:17:30 +08:00
return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. llvm-svn: 58230
2008-10-27 15:14:50 +08:00
}
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. llvm-svn: 56825
2008-09-30 08:58:23 +08:00
/// getGlobalBaseReg - Return a virtual register initialized with the
/// the global base register value. Output instructions required to
/// initialize the register in the function entry block, if necessary.
Move the code for initializing the global base reg out of X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. llvm-svn: 56494
2008-09-24 02:22:58 +08:00
///
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
///
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. llvm-svn: 56825
2008-09-30 08:58:23 +08:00
unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
"X86-64 PIC uses RIP relative addressing");
X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
if (GlobalBaseReg != 0)
return GlobalBaseReg;
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
// Create the register. The code to initialize it is inserted
// later, by the CGBR pass (below).
Move the code for initializing the global base reg out of X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. llvm-svn: 56494
2008-09-24 02:22:58 +08:00
MachineRegisterInfo &RegInfo = MF->getRegInfo();
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. llvm-svn: 56825
2008-09-30 08:58:23 +08:00
X86FI->setGlobalBaseReg(GlobalBaseReg);
return GlobalBaseReg;
Move the code for initializing the global base reg out of X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. llvm-svn: 56494
2008-09-24 02:22:58 +08:00
}
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. llvm-svn: 99524
2010-03-26 01:25:00 +08:00
Basic implementation of SSEDomainFix pass. Cross-block inference is primitive and wrong, but the pass is working otherwise. llvm-svn: 99848
2010-03-30 07:24:21 +08:00
// These are the replaceable SSE instructions. Some of these have Int variants
// that we don't include here. We don't want to replace instructions selected
// by intrinsics.
static const unsigned ReplaceableInstrs[][3] = {
Fix comment order llvm-svn: 110898
2010-08-12 10:08:52 +08:00
//PackedSingle PackedDouble PackedInt
Renumber SSE execution domains for better code size. SSEDomainFix will collapse to the domain with the lower number when it has a choice. The SSEPackedSingle domain often has smaller instructions, so prefer that. llvm-svn: 99952
2010-03-31 06:46:53 +08:00
{ X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
{ X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
{ X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
{ X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
{ X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
{ X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
{ X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
{ X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
{ X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
{ X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
{ X86::ORPSrm, X86::ORPDrm, X86::PORrm },
{ X86::ORPSrr, X86::ORPDrr, X86::PORrr },
{ X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
{ X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. - Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too. - Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX. - Add a testcase for a simple 128-bit zero vector creation. llvm-svn: 110946
2010-08-13 04:20:53 +08:00
// AVX 128-bit support
{ X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
{ X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
{ X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
{ X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
{ X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
{ X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
{ X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
{ X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
{ X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
{ X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
{ X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
{ X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
{ X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
{ X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Add 256-bit load/store recognition and matching in several places. llvm-svn: 135171
2011-07-15 02:50:58 +08:00
// AVX 256-bit support
{ X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
{ X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
{ X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
{ X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
{ X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
{ X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
Basic implementation of SSEDomainFix pass. Cross-block inference is primitive and wrong, but the pass is working otherwise. llvm-svn: 99848
2010-03-30 07:24:21 +08:00
};
// FIXME: Some shuffle and unpack instructions have equivalents in different
// domains, but they require a bit more work than just switching opcodes.
static const unsigned *lookup(unsigned opcode, unsigned domain) {
for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
if (ReplaceableInstrs[i][domain-1] == opcode)
return ReplaceableInstrs[i];
return 0;
}
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. llvm-svn: 99524
2010-03-26 01:25:00 +08:00
Basic implementation of SSEDomainFix pass. Cross-block inference is primitive and wrong, but the pass is working otherwise. llvm-svn: 99848
2010-03-30 07:24:21 +08:00
std::pair<uint16_t, uint16_t>
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo. I am going to unify the SSEDomainFix and NEONMoveFix passes into a single target independent pass. They are essentially doing the same thing. llvm-svn: 140652
2011-09-28 06:57:18 +08:00
X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Basic implementation of SSEDomainFix pass. Cross-block inference is primitive and wrong, but the pass is working otherwise. llvm-svn: 99848
2010-03-30 07:24:21 +08:00
uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Renumber SSE execution domains for better code size. SSEDomainFix will collapse to the domain with the lower number when it has a choice. The SSEPackedSingle domain often has smaller instructions, so prefer that. llvm-svn: 99952
2010-03-31 06:46:53 +08:00
return std::make_pair(domain,
domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
Basic implementation of SSEDomainFix pass. Cross-block inference is primitive and wrong, but the pass is working otherwise. llvm-svn: 99848
2010-03-30 07:24:21 +08:00
}
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. llvm-svn: 99524
2010-03-26 01:25:00 +08:00
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo. I am going to unify the SSEDomainFix and NEONMoveFix passes into a single target independent pass. They are essentially doing the same thing. llvm-svn: 140652
2011-09-28 06:57:18 +08:00
void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Basic implementation of SSEDomainFix pass. Cross-block inference is primitive and wrong, but the pass is working otherwise. llvm-svn: 99848
2010-03-30 07:24:21 +08:00
assert(Domain>0 && Domain<4 && "Invalid execution domain");
uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
assert(dom && "Not an SSE instruction");
const unsigned *table = lookup(MI->getOpcode(), dom);
assert(table && "Cannot change domain");
MI->setDesc(get(table[Domain-1]));
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. llvm-svn: 99524
2010-03-26 01:25:00 +08:00
}
on darwin empty functions need to codegen into something of non-zero length, otherwise labels get incorrectly merged. We handled this by emitting a ".byte 0", but this isn't correct on thumb/arm targets where the text segment needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This is more gross than it should be because arm/ppc are not fully mc'ized yet. This fixes rdar://7908505 llvm-svn: 102400
2010-04-27 07:37:21 +08:00
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.setOpcode(X86::NOOP);
}
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
Increased the register pressure limit on x86_64 from 8 to 12 regs. This is the only change in this checkin that may affects the default scheduler. With better register tracking and heuristics, it doesn't make sense to artificially lower the register limit so much. Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to give the scheduler a way to account for div and sqrt on targets that don't have an itinerary. It is currently defaults to 10 (the actual number doesn't matter much), but only takes effect on non-default schedulers: list-hybrid and list-ilp. Added several heuristics that can be individually disabled for the non-default sched=list-ilp mode. This helps us determine how much better we can do on a given benchmark than the default scheduler. Certain compute intensive loops run much faster in this mode with the right set of heuristics, and it doesn't seem to have much negative impact elsewhere. Not all of the heuristics are needed, but we still need to experiment to decide which should be disabled by default for sched=list-ilp. llvm-svn: 127067
2011-03-05 16:00:22 +08:00
bool X86InstrInfo::isHighLatencyDef(int opc) const {
switch (opc) {
Re-enable register pressure aware machine licm with fixes. Hoist() may have erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. llvm-svn: 116845
2010-10-20 02:58:51 +08:00
default: return false;
case X86::DIVSDrm:
case X86::DIVSDrm_Int:
case X86::DIVSDrr:
case X86::DIVSDrr_Int:
case X86::DIVSSrm:
case X86::DIVSSrm_Int:
case X86::DIVSSrr:
case X86::DIVSSrr_Int:
case X86::SQRTPDm:
case X86::SQRTPDm_Int:
case X86::SQRTPDr:
case X86::SQRTPDr_Int:
case X86::SQRTPSm:
case X86::SQRTPSm_Int:
case X86::SQRTPSr:
case X86::SQRTPSr_Int:
case X86::SQRTSDm:
case X86::SQRTSDm_Int:
case X86::SQRTSDr:
case X86::SQRTSDr_Int:
case X86::SQRTSSm:
case X86::SQRTSSm_Int:
case X86::SQRTSSr:
case X86::SQRTSSr_Int:
Add the remaining AVX versions of instructions to X86InstrInfo, this time for describing high latency ones and for recognizting loads from the same base pointer llvm-svn: 139864
2011-09-16 06:15:52 +08:00
// AVX instructions with high latency
case X86::VDIVSDrm:
case X86::VDIVSDrm_Int:
case X86::VDIVSDrr:
case X86::VDIVSDrr_Int:
case X86::VDIVSSrm:
case X86::VDIVSSrm_Int:
case X86::VDIVSSrr:
case X86::VDIVSSrr_Int:
case X86::VSQRTPDm:
case X86::VSQRTPDm_Int:
case X86::VSQRTPDr:
case X86::VSQRTPDr_Int:
case X86::VSQRTPSm:
case X86::VSQRTPSm_Int:
case X86::VSQRTPSr:
case X86::VSQRTPSr_Int:
case X86::VSQRTSDm:
case X86::VSQRTSDm_Int:
case X86::VSQRTSDr:
case X86::VSQRTSSm:
case X86::VSQRTSSm_Int:
case X86::VSQRTSSr:
Re-enable register pressure aware machine licm with fixes. Hoist() may have erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. llvm-svn: 116845
2010-10-20 02:58:51 +08:00
return true;
}
}
Increased the register pressure limit on x86_64 from 8 to 12 regs. This is the only change in this checkin that may affects the default scheduler. With better register tracking and heuristics, it doesn't make sense to artificially lower the register limit so much. Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to give the scheduler a way to account for div and sqrt on targets that don't have an itinerary. It is currently defaults to 10 (the actual number doesn't matter much), but only takes effect on non-default schedulers: list-hybrid and list-ilp. Added several heuristics that can be individually disabled for the non-default sched=list-ilp mode. This helps us determine how much better we can do on a given benchmark than the default scheduler. Certain compute intensive loops run much faster in this mode with the right set of heuristics, and it doesn't seem to have much negative impact elsewhere. Not all of the heuristics are needed, but we still need to experiment to decide which should be disabled by default for sched=list-ilp. llvm-svn: 127067
2011-03-05 16:00:22 +08:00
bool X86InstrInfo::
hasHighOperandLatency(const InstrItineraryData *ItinData,
const MachineRegisterInfo *MRI,
const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI, unsigned UseIdx) const {
return isHighLatencyDef(DefMI->getOpcode());
}
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
namespace {
/// CGBR - Create Global Base Reg pass. This initializes the PIC
/// global base register for x86-32.
struct CGBR : public MachineFunctionPass {
static char ID;
Reapply r110396, with fixes to appease the Linux buildbot gods. llvm-svn: 110460
2010-08-07 02:33:48 +08:00
CGBR() : MachineFunctionPass(ID) {}
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
virtual bool runOnMachineFunction(MachineFunction &MF) {
const X86TargetMachine *TM =
static_cast<const X86TargetMachine *>(&MF.getTarget());
assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
"X86-64 PIC uses RIP relative addressing");
// Only emit a global base reg in PIC mode.
if (TM->getRelocationModel() != Reloc::PIC_)
return false;
Avoid emitting a PIC base register if no PIC addresses are needed. This fixes rdar://8396318. llvm-svn: 114201
2010-09-18 04:24:24 +08:00
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
// If we didn't need a GlobalBaseReg, don't insert code.
if (GlobalBaseReg == 0)
return false;
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = MF.front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
MachineRegisterInfo &RegInfo = MF.getRegInfo();
const X86InstrInfo *TII = TM->getInstrInfo();
unsigned PC;
if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
else
Avoid emitting a PIC base register if no PIC addresses are needed. This fixes rdar://8396318. llvm-svn: 114201
2010-09-18 04:24:24 +08:00
PC = GlobalBaseReg;
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
// Operand of MovePCtoStack is completely ignored by asm printer. It's
// only used in JIT code emission as displacement to pc.
BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
Fix whitespace. llvm-svn: 124270
2011-01-26 10:03:37 +08:00
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
// If we're using vanilla 'GOT' PIC style, we should use relative addressing
// not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
// Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
.addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
X86II::MO_GOT_ABSOLUTE_ADDRESS);
}
return true;
}
virtual const char *getPassName() const {
return "X86 PIC Global Base Reg Initialization";
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU);
}
};
}
char CGBR::ID = 0;
FunctionPass*
llvm::createGlobalBaseRegPass() { return new CGBR(); }