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[NFC][SCEV] Add tests related to bit masking (PR37793) Summary: Related to https://bugs.llvm.org/show_bug.cgi?id=37793, https://reviews.llvm.org/D46760#1127287 We'd like to do this canonicalization https://rise4fun.com/Alive/Gmc But it is currently restricted by rL155136 / rL155362, which says: ``` // This is a constant shift of a constant shift. Be careful about hiding // shl instructions behind bit masks. They are used to represent multiplies // by a constant, and it is important that simple arithmetic expressions // are still recognizable by scalar evolution. // // The transforms applied to shl are very similar to the transforms applied // to mul by constant. We can be more aggressive about optimizing right // shifts. // // Combinations of right and left shifts will still be optimized in // DAGCombine where scalar evolution no longer applies. ``` I think these tests show that for *constants*, SCEV has no issues with that canonicalization. Reviewers: mkazantsev, spatel, efriedma, sanjoy Reviewed By: mkazantsev Subscribers: sanjoy, javed.absar, llvm-commits, stoklund, bixia Differential Revision: https://reviews.llvm.org/D48229 llvm-svn: 335101
2018-06-20 15:54:11 +08:00
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -S -analyze -scalar-evolution < %s | FileCheck %s
; The obvious case.
define i32 @div(i32 %val) nounwind {
; CHECK-LABEL: 'div'
; CHECK-NEXT: Classifying expressions for: @div
; CHECK-NEXT: %tmp1 = udiv i32 %val, 16
; CHECK-NEXT: --> (%val /u 16) U: [0,268435456) S: [0,268435456)
; CHECK-NEXT: %tmp2 = mul i32 %tmp1, 16
[SCEV] Use unsigned/signed intersection type in SCEV Based on D59959, this switches SCEV to use unsigned/signed range intersection based on the sign hint. This will prefer non-wrapping ranges in the relevant domain. I've left the one intersection in getRangeForAffineAR() to use the smallest intersection heuristic, as there doesn't seem to be any obvious preference there. Differential Revision: https://reviews.llvm.org/D60035 llvm-svn: 363490
2019-06-15 17:15:52 +08:00
; CHECK-NEXT: --> (16 * (%val /u 16))<nuw> U: [0,-15) S: [-2147483648,2147483633)
[NFC][SCEV] Add tests related to bit masking (PR37793) Summary: Related to https://bugs.llvm.org/show_bug.cgi?id=37793, https://reviews.llvm.org/D46760#1127287 We'd like to do this canonicalization https://rise4fun.com/Alive/Gmc But it is currently restricted by rL155136 / rL155362, which says: ``` // This is a constant shift of a constant shift. Be careful about hiding // shl instructions behind bit masks. They are used to represent multiplies // by a constant, and it is important that simple arithmetic expressions // are still recognizable by scalar evolution. // // The transforms applied to shl are very similar to the transforms applied // to mul by constant. We can be more aggressive about optimizing right // shifts. // // Combinations of right and left shifts will still be optimized in // DAGCombine where scalar evolution no longer applies. ``` I think these tests show that for *constants*, SCEV has no issues with that canonicalization. Reviewers: mkazantsev, spatel, efriedma, sanjoy Reviewed By: mkazantsev Subscribers: sanjoy, javed.absar, llvm-commits, stoklund, bixia Differential Revision: https://reviews.llvm.org/D48229 llvm-svn: 335101
2018-06-20 15:54:11 +08:00
; CHECK-NEXT: Determining loop execution counts for: @div
;
%tmp1 = udiv i32 %val, 16
%tmp2 = mul i32 %tmp1, 16
ret i32 %tmp2
}
define i32 @sdiv(i32 %val) nounwind {
; CHECK-LABEL: 'sdiv'
; CHECK-NEXT: Classifying expressions for: @sdiv
; CHECK-NEXT: %tmp1 = sdiv i32 %val, 16
; CHECK-NEXT: --> %tmp1 U: full-set S: [-134217728,134217728)
; CHECK-NEXT: %tmp2 = mul i32 %tmp1, 16
Re-apply "[SCEV] Strengthen StrengthenNoWrapFlags (reapply r334428)." llvm-svn: 337075
2018-07-14 07:58:46 +08:00
; CHECK-NEXT: --> (16 * %tmp1)<nsw> U: [0,-15) S: [-2147483648,2147483633)
[NFC][SCEV] Add tests related to bit masking (PR37793) Summary: Related to https://bugs.llvm.org/show_bug.cgi?id=37793, https://reviews.llvm.org/D46760#1127287 We'd like to do this canonicalization https://rise4fun.com/Alive/Gmc But it is currently restricted by rL155136 / rL155362, which says: ``` // This is a constant shift of a constant shift. Be careful about hiding // shl instructions behind bit masks. They are used to represent multiplies // by a constant, and it is important that simple arithmetic expressions // are still recognizable by scalar evolution. // // The transforms applied to shl are very similar to the transforms applied // to mul by constant. We can be more aggressive about optimizing right // shifts. // // Combinations of right and left shifts will still be optimized in // DAGCombine where scalar evolution no longer applies. ``` I think these tests show that for *constants*, SCEV has no issues with that canonicalization. Reviewers: mkazantsev, spatel, efriedma, sanjoy Reviewed By: mkazantsev Subscribers: sanjoy, javed.absar, llvm-commits, stoklund, bixia Differential Revision: https://reviews.llvm.org/D48229 llvm-svn: 335101
2018-06-20 15:54:11 +08:00
; CHECK-NEXT: Determining loop execution counts for: @sdiv
;
%tmp1 = sdiv i32 %val, 16
%tmp2 = mul i32 %tmp1, 16
ret i32 %tmp2
}
; Or, it could be a number of equivalent patterns with mask:
; b) x & (-1 << nbits)
; d) x >> nbits << nbits
define i32 @mask_b(i32 %val) nounwind {
; CHECK-LABEL: 'mask_b'
; CHECK-NEXT: Classifying expressions for: @mask_b
; CHECK-NEXT: %masked = and i32 %val, -16
[SCEV] Use unsigned/signed intersection type in SCEV Based on D59959, this switches SCEV to use unsigned/signed range intersection based on the sign hint. This will prefer non-wrapping ranges in the relevant domain. I've left the one intersection in getRangeForAffineAR() to use the smallest intersection heuristic, as there doesn't seem to be any obvious preference there. Differential Revision: https://reviews.llvm.org/D60035 llvm-svn: 363490
2019-06-15 17:15:52 +08:00
; CHECK-NEXT: --> (16 * (%val /u 16))<nuw> U: [0,-15) S: [-2147483648,2147483633)
[NFC][SCEV] Add tests related to bit masking (PR37793) Summary: Related to https://bugs.llvm.org/show_bug.cgi?id=37793, https://reviews.llvm.org/D46760#1127287 We'd like to do this canonicalization https://rise4fun.com/Alive/Gmc But it is currently restricted by rL155136 / rL155362, which says: ``` // This is a constant shift of a constant shift. Be careful about hiding // shl instructions behind bit masks. They are used to represent multiplies // by a constant, and it is important that simple arithmetic expressions // are still recognizable by scalar evolution. // // The transforms applied to shl are very similar to the transforms applied // to mul by constant. We can be more aggressive about optimizing right // shifts. // // Combinations of right and left shifts will still be optimized in // DAGCombine where scalar evolution no longer applies. ``` I think these tests show that for *constants*, SCEV has no issues with that canonicalization. Reviewers: mkazantsev, spatel, efriedma, sanjoy Reviewed By: mkazantsev Subscribers: sanjoy, javed.absar, llvm-commits, stoklund, bixia Differential Revision: https://reviews.llvm.org/D48229 llvm-svn: 335101
2018-06-20 15:54:11 +08:00
; CHECK-NEXT: Determining loop execution counts for: @mask_b
;
%masked = and i32 %val, -16
ret i32 %masked
}
define i32 @mask_d(i32 %val) nounwind {
; CHECK-LABEL: 'mask_d'
; CHECK-NEXT: Classifying expressions for: @mask_d
; CHECK-NEXT: %lowbitscleared = lshr i32 %val, 4
; CHECK-NEXT: --> (%val /u 16) U: [0,268435456) S: [0,268435456)
; CHECK-NEXT: %masked = shl i32 %lowbitscleared, 4
[SCEV] Use unsigned/signed intersection type in SCEV Based on D59959, this switches SCEV to use unsigned/signed range intersection based on the sign hint. This will prefer non-wrapping ranges in the relevant domain. I've left the one intersection in getRangeForAffineAR() to use the smallest intersection heuristic, as there doesn't seem to be any obvious preference there. Differential Revision: https://reviews.llvm.org/D60035 llvm-svn: 363490
2019-06-15 17:15:52 +08:00
; CHECK-NEXT: --> (16 * (%val /u 16))<nuw> U: [0,-15) S: [-2147483648,2147483633)
[NFC][SCEV] Add tests related to bit masking (PR37793) Summary: Related to https://bugs.llvm.org/show_bug.cgi?id=37793, https://reviews.llvm.org/D46760#1127287 We'd like to do this canonicalization https://rise4fun.com/Alive/Gmc But it is currently restricted by rL155136 / rL155362, which says: ``` // This is a constant shift of a constant shift. Be careful about hiding // shl instructions behind bit masks. They are used to represent multiplies // by a constant, and it is important that simple arithmetic expressions // are still recognizable by scalar evolution. // // The transforms applied to shl are very similar to the transforms applied // to mul by constant. We can be more aggressive about optimizing right // shifts. // // Combinations of right and left shifts will still be optimized in // DAGCombine where scalar evolution no longer applies. ``` I think these tests show that for *constants*, SCEV has no issues with that canonicalization. Reviewers: mkazantsev, spatel, efriedma, sanjoy Reviewed By: mkazantsev Subscribers: sanjoy, javed.absar, llvm-commits, stoklund, bixia Differential Revision: https://reviews.llvm.org/D48229 llvm-svn: 335101
2018-06-20 15:54:11 +08:00
; CHECK-NEXT: Determining loop execution counts for: @mask_d
;
%lowbitscleared = lshr i32 %val, 4
%masked = shl i32 %lowbitscleared, 4
ret i32 %masked
}