forked from OSchip/llvm-project
65 lines
2.0 KiB
C++
65 lines
2.0 KiB
C++
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//===--- AMDGPUMacroFusion.cpp - AMDGPU Macro Fusion ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the AMDGPU implementation of the DAG scheduling
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/// mutation to pair instructions back to back.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMacroFusion.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MacroFusion.h"
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using namespace llvm;
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namespace {
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/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
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/// together. Given SecondMI, when FirstMI is unspecified, then check if
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/// SecondMI may be part of a fused pair at all.
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static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_,
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const TargetSubtargetInfo &TSI,
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const MachineInstr *FirstMI,
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const MachineInstr &SecondMI) {
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const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_);
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switch (SecondMI.getOpcode()) {
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case AMDGPU::V_ADDC_U32_e64:
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case AMDGPU::V_SUBB_U32_e64:
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case AMDGPU::V_CNDMASK_B32_e64: {
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// Try to cluster defs of condition registers to their uses. This improves
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// the chance VCC will be available which will allow shrinking to VOP2
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// encodings.
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if (!FirstMI)
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return true;
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const MachineOperand *Src2 = TII.getNamedOperand(SecondMI,
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AMDGPU::OpName::src2);
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return FirstMI->definesRegister(Src2->getReg());
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}
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default:
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return false;
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}
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return false;
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}
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} // end namespace
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namespace llvm {
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std::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation () {
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return createMacroFusionDAGMutation(shouldScheduleAdjacent);
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}
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} // end namespace llvm
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