2010-01-28 14:22:43 +08:00
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; RUN: llc < %s -march=xcore -asm-verbose=0 | FileCheck %s
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2009-10-08 23:38:17 +08:00
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define i32 @ashr(i32 %a, i32 %b) {
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%1 = ashr i32 %a, %b
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ret i32 %1
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}
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; CHECK: ashr:
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; CHECK-NEXT: ashr r0, r0, r1
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define i32 @ashri1(i32 %a) {
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%1 = ashr i32 %a, 24
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ret i32 %1
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}
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; CHECK: ashri1:
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; CHECK-NEXT: ashr r0, r0, 24
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define i32 @ashri2(i32 %a) {
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%1 = ashr i32 %a, 31
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ret i32 %1
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}
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; CHECK: ashri2:
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; CHECK-NEXT: ashr r0, r0, 32
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define i32 @f1(i32 %a) {
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%1 = icmp slt i32 %a, 0
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br i1 %1, label %less, label %not_less
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less:
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ret i32 10
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not_less:
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ret i32 17
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}
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; CHECK: f1:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bf r0
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define i32 @f2(i32 %a) {
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%1 = icmp sge i32 %a, 0
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br i1 %1, label %greater, label %not_greater
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greater:
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ret i32 10
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not_greater:
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ret i32 17
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}
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; CHECK: f2:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bt r0
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define i32 @f3(i32 %a) {
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%1 = icmp slt i32 %a, 0
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%2 = select i1 %1, i32 10, i32 17
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ret i32 %2
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}
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; CHECK: f3:
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Enable machine sinking critical edge splitting. e.g.
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
%z = select i1 %c, double %a, double %y
ret double %z
}
Was:
_foo:
divsd LCPI0_0(%rip), %xmm0
testb $1, %dil
jne LBB0_2
movaps %xmm1, %xmm0
LBB0_2:
ret
Now:
_foo:
testb $1, %dil
je LBB0_2
divsd LCPI0_0(%rip), %xmm0
ret
LBB0_2:
movaps %xmm1, %xmm0
ret
This avoids the divsd when early exit is taken.
rdar://8454886
llvm-svn: 114372
2010-09-21 06:52:00 +08:00
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bf r0
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2009-10-08 23:38:17 +08:00
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; CHECK-NEXT: ldc r0, 10
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; CHECK: ldc r0, 17
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define i32 @f4(i32 %a) {
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%1 = icmp sge i32 %a, 0
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%2 = select i1 %1, i32 10, i32 17
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ret i32 %2
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}
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; CHECK: f4:
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Enable machine sinking critical edge splitting. e.g.
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
%z = select i1 %c, double %a, double %y
ret double %z
}
Was:
_foo:
divsd LCPI0_0(%rip), %xmm0
testb $1, %dil
jne LBB0_2
movaps %xmm1, %xmm0
LBB0_2:
ret
Now:
_foo:
testb $1, %dil
je LBB0_2
divsd LCPI0_0(%rip), %xmm0
ret
LBB0_2:
movaps %xmm1, %xmm0
ret
This avoids the divsd when early exit is taken.
rdar://8454886
llvm-svn: 114372
2010-09-21 06:52:00 +08:00
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: bf r0
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2009-10-08 23:38:17 +08:00
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; CHECK-NEXT: ldc r0, 17
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; CHECK: ldc r0, 10
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define i32 @f5(i32 %a) {
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%1 = icmp sge i32 %a, 0
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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; CHECK: f5:
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; CHECK-NEXT: ashr r0, r0, 32
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; CHECK-NEXT: eq r0, r0, 0
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