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llvm-project/llvm/test/CodeGen/X86/tbm-intrinsics-x86_64.ll

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[X86][TBM] Regenerate bextri intrinsics tests. NFCI. llvm-svn: 310788
2017-08-13 19:56:15 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
X86: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309774
2017-08-02 08:28:10 +08:00
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+tbm < %s | FileCheck %s
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind readnone {
[X86][TBM] Regenerate bextri intrinsics tests. NFCI. llvm-svn: 310788
2017-08-13 19:56:15 +08:00
; CHECK-LABEL: test_x86_tbm_bextri_u32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: bextr $2814, %edi, %eax # imm = 0xAFE
; CHECK-NEXT: retq
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
entry:
%0 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %a, i32 2814)
ret i32 %0
}
declare i32 @llvm.x86.tbm.bextri.u32(i32, i32) nounwind readnone
define i32 @test_x86_tbm_bextri_u32_m(i32* nocapture %a) nounwind readonly {
[X86][TBM] Regenerate bextri intrinsics tests. NFCI. llvm-svn: 310788
2017-08-13 19:56:15 +08:00
; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: bextr $2814, (%rdi), %eax # imm = 0xAFE
; CHECK-NEXT: retq
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load i32, i32* %a, align 4
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
%0 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %tmp1, i32 2814)
ret i32 %0
}
[X86][TBM] Add tests showing failure to fold RFLAGS result into TBM instructions. And fails to select TBM instructions at all. llvm-svn: 310790
2017-08-13 20:16:00 +08:00
define i32 @test_x86_tbm_bextri_u32_z(i32 %a, i32 %b) nounwind readonly {
; CHECK-LABEL: test_x86_tbm_bextri_u32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: bextr $2814, %edi, %eax # imm = 0xAFE
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
entry:
%0 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %a, i32 2814)
%1 = icmp eq i32 %0, 0
%2 = select i1 %1, i32 %b, i32 %0
ret i32 %2
}
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind readnone {
[X86][TBM] Regenerate bextri intrinsics tests. NFCI. llvm-svn: 310788
2017-08-13 19:56:15 +08:00
; CHECK-LABEL: test_x86_tbm_bextri_u64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: bextr $2814, %rdi, %rax # imm = 0xAFE
; CHECK-NEXT: retq
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
entry:
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %a, i64 2814)
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
ret i64 %0
}
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
declare i64 @llvm.x86.tbm.bextri.u64(i64, i64) nounwind readnone
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly {
[X86][TBM] Regenerate bextri intrinsics tests. NFCI. llvm-svn: 310788
2017-08-13 19:56:15 +08:00
; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: bextr $2814, (%rdi), %rax # imm = 0xAFE
; CHECK-NEXT: retq
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load i64, i64* %a, align 8
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. llvm-svn: 191871
2013-10-03 12:16:45 +08:00
%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %tmp1, i64 2814)
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
2013-09-28 02:38:42 +08:00
ret i64 %0
}
[X86][TBM] Add tests showing failure to fold RFLAGS result into TBM instructions. And fails to select TBM instructions at all. llvm-svn: 310790
2017-08-13 20:16:00 +08:00
define i64 @test_x86_tbm_bextri_u64_z(i64 %a, i64 %b) nounwind readnone {
; CHECK-LABEL: test_x86_tbm_bextri_u64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: bextr $2814, %rdi, %rax # imm = 0xAFE
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
entry:
%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %a, i64 2814)
%1 = icmp eq i64 %0, 0
%2 = select i1 %1, i64 %b, i64 %0
ret i64 %2
}