2017-04-23 21:59:29 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
2017-08-01 23:14:35 +08:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+sse3 | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
|
2017-04-23 21:59:29 +08:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=atom | FileCheck %s --check-prefix=CHECK --check-prefix=ATOM
|
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=slm | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
|
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=sandybridge | FileCheck %s --check-prefix=CHECK --check-prefix=SANDY
|
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=ivybridge | FileCheck %s --check-prefix=CHECK --check-prefix=SANDY
|
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
|
2017-10-17 21:45:39 +08:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=broadwell | FileCheck %s --check-prefix=CHECK --check-prefix=BROADWELL
|
2017-08-30 16:08:50 +08:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=SKYLAKE
|
2017-10-06 21:40:29 +08:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skx | FileCheck %s --check-prefix=CHECK --check-prefix=SKX
|
2017-04-23 21:59:29 +08:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2
|
2017-07-19 10:45:14 +08:00
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=ZNVER1
|
2017-04-23 21:59:29 +08:00
|
|
|
|
|
|
|
define <2 x double> @test_addsubpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
|
|
|
|
; GENERIC-LABEL: test_addsubpd:
|
|
|
|
; GENERIC: # BB#0:
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: addsubpd %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; GENERIC-NEXT: addsubpd (%rdi), %xmm0 # sched: [9:1.00]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_addsubpd:
|
|
|
|
; ATOM: # BB#0:
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: addsubpd %xmm1, %xmm0 # sched: [6:3.00]
|
|
|
|
; ATOM-NEXT: addsubpd (%rdi), %xmm0 # sched: [6:3.00]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; SLM-LABEL: test_addsubpd:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: addsubpd %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; SLM-NEXT: addsubpd (%rdi), %xmm0 # sched: [6:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_addsubpd:
|
|
|
|
; SANDY: # BB#0:
|
|
|
|
; SANDY-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
|
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_addsubpd:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_addsubpd:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
|
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_addsubpd:
|
|
|
|
; SKYLAKE: # BB#0:
|
2017-09-19 14:19:27 +08:00
|
|
|
; SKYLAKE-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
|
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_addsubpd:
|
|
|
|
; SKX: # BB#0:
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
|
|
|
|
; SKX-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
|
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-LABEL: test_addsubpd:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; BTVER2-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
2017-07-19 10:45:14 +08:00
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_addsubpd:
|
|
|
|
; ZNVER1: # BB#0:
|
|
|
|
; ZNVER1-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; ZNVER1-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
%1 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1)
|
|
|
|
%2 = load <2 x double>, <2 x double> *%a2, align 16
|
|
|
|
%3 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %1, <2 x double> %2)
|
|
|
|
ret <2 x double> %3
|
|
|
|
}
|
|
|
|
declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
|
|
|
|
|
|
|
|
define <4 x float> @test_addsubps(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a2) {
|
|
|
|
; GENERIC-LABEL: test_addsubps:
|
|
|
|
; GENERIC: # BB#0:
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: addsubps %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; GENERIC-NEXT: addsubps (%rdi), %xmm0 # sched: [9:1.00]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_addsubps:
|
|
|
|
; ATOM: # BB#0:
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: addsubps %xmm1, %xmm0 # sched: [5:5.00]
|
|
|
|
; ATOM-NEXT: addsubps (%rdi), %xmm0 # sched: [5:5.00]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; SLM-LABEL: test_addsubps:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: addsubps %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; SLM-NEXT: addsubps (%rdi), %xmm0 # sched: [6:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_addsubps:
|
|
|
|
; SANDY: # BB#0:
|
|
|
|
; SANDY-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
|
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_addsubps:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_addsubps:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
|
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_addsubps:
|
|
|
|
; SKYLAKE: # BB#0:
|
2017-09-19 14:19:27 +08:00
|
|
|
; SKYLAKE-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
|
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_addsubps:
|
|
|
|
; SKX: # BB#0:
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
|
|
|
|
; SKX-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
|
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-LABEL: test_addsubps:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; BTVER2-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
2017-07-19 10:45:14 +08:00
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_addsubps:
|
|
|
|
; ZNVER1: # BB#0:
|
|
|
|
; ZNVER1-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; ZNVER1-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
%1 = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1)
|
|
|
|
%2 = load <4 x float>, <4 x float> *%a2, align 16
|
|
|
|
%3 = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %1, <4 x float> %2)
|
|
|
|
ret <4 x float> %3
|
|
|
|
}
|
|
|
|
declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
|
|
|
|
|
|
|
|
define <2 x double> @test_haddpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
|
|
|
|
; GENERIC-LABEL: test_haddpd:
|
|
|
|
; GENERIC: # BB#0:
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: haddpd %xmm1, %xmm0 # sched: [5:2.00]
|
|
|
|
; GENERIC-NEXT: haddpd (%rdi), %xmm0 # sched: [11:2.00]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_haddpd:
|
|
|
|
; ATOM: # BB#0:
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: haddpd %xmm1, %xmm0 # sched: [8:4.00]
|
|
|
|
; ATOM-NEXT: haddpd (%rdi), %xmm0 # sched: [9:4.50]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; SLM-LABEL: test_haddpd:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: haddpd %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; SLM-NEXT: haddpd (%rdi), %xmm0 # sched: [6:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_haddpd:
|
|
|
|
; SANDY: # BB#0:
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
|
|
|
; SANDY-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [11:2.00]
|
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_haddpd:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [5:2.00]
|
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_haddpd:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [10:2.00]
|
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_haddpd:
|
|
|
|
; SKYLAKE: # BB#0:
|
2017-09-19 14:19:27 +08:00
|
|
|
; SKYLAKE-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
|
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_haddpd:
|
|
|
|
; SKX: # BB#0:
|
|
|
|
; SKX-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
|
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-LABEL: test_haddpd:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; BTVER2-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
2017-07-19 10:45:14 +08:00
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_haddpd:
|
|
|
|
; ZNVER1: # BB#0:
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 # sched: [100:?]
|
|
|
|
; ZNVER1-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [100:?]
|
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
%1 = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1)
|
|
|
|
%2 = load <2 x double>, <2 x double> *%a2, align 16
|
|
|
|
%3 = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %1, <2 x double> %2)
|
|
|
|
ret <2 x double> %3
|
|
|
|
}
|
|
|
|
declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone
|
|
|
|
|
|
|
|
define <4 x float> @test_haddps(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a2) {
|
|
|
|
; GENERIC-LABEL: test_haddps:
|
|
|
|
; GENERIC: # BB#0:
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: haddps %xmm1, %xmm0 # sched: [5:2.00]
|
|
|
|
; GENERIC-NEXT: haddps (%rdi), %xmm0 # sched: [11:2.00]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_haddps:
|
|
|
|
; ATOM: # BB#0:
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: haddps %xmm1, %xmm0 # sched: [8:4.00]
|
|
|
|
; ATOM-NEXT: haddps (%rdi), %xmm0 # sched: [9:4.50]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; SLM-LABEL: test_haddps:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: haddps %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; SLM-NEXT: haddps (%rdi), %xmm0 # sched: [6:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_haddps:
|
|
|
|
; SANDY: # BB#0:
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: vhaddps %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
|
|
|
; SANDY-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [11:2.00]
|
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_haddps:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: vhaddps %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [5:2.00]
|
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_haddps:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: vhaddps %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [10:2.00]
|
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_haddps:
|
|
|
|
; SKYLAKE: # BB#0:
|
2017-09-19 14:19:27 +08:00
|
|
|
; SKYLAKE-NEXT: vhaddps %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
|
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_haddps:
|
|
|
|
; SKX: # BB#0:
|
|
|
|
; SKX-NEXT: vhaddps %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
|
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-LABEL: test_haddps:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: vhaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; BTVER2-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
2017-07-19 10:45:14 +08:00
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_haddps:
|
|
|
|
; ZNVER1: # BB#0:
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: vhaddps %xmm1, %xmm0, %xmm0 # sched: [100:?]
|
|
|
|
; ZNVER1-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [100:?]
|
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
%1 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1)
|
|
|
|
%2 = load <4 x float>, <4 x float> *%a2, align 16
|
|
|
|
%3 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %1, <4 x float> %2)
|
|
|
|
ret <4 x float> %3
|
|
|
|
}
|
|
|
|
declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
|
|
|
|
|
|
|
|
define <2 x double> @test_hsubpd(<2 x double> %a0, <2 x double> %a1, <2 x double> *%a2) {
|
|
|
|
; GENERIC-LABEL: test_hsubpd:
|
|
|
|
; GENERIC: # BB#0:
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: hsubpd %xmm1, %xmm0 # sched: [5:2.00]
|
|
|
|
; GENERIC-NEXT: hsubpd (%rdi), %xmm0 # sched: [11:2.00]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_hsubpd:
|
|
|
|
; ATOM: # BB#0:
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: hsubpd %xmm1, %xmm0 # sched: [8:4.00]
|
|
|
|
; ATOM-NEXT: hsubpd (%rdi), %xmm0 # sched: [9:4.50]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; SLM-LABEL: test_hsubpd:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: hsubpd %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; SLM-NEXT: hsubpd (%rdi), %xmm0 # sched: [6:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_hsubpd:
|
|
|
|
; SANDY: # BB#0:
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
|
|
|
; SANDY-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [11:2.00]
|
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_hsubpd:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [5:2.00]
|
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_hsubpd:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [10:2.00]
|
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_hsubpd:
|
|
|
|
; SKYLAKE: # BB#0:
|
2017-09-19 14:19:27 +08:00
|
|
|
; SKYLAKE-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
|
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_hsubpd:
|
|
|
|
; SKX: # BB#0:
|
|
|
|
; SKX-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
|
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-LABEL: test_hsubpd:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; BTVER2-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
2017-07-19 10:45:14 +08:00
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_hsubpd:
|
|
|
|
; ZNVER1: # BB#0:
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 # sched: [100:?]
|
|
|
|
; ZNVER1-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [100:?]
|
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
%1 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
|
|
|
|
%2 = load <2 x double>, <2 x double> *%a2, align 16
|
|
|
|
%3 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %1, <2 x double> %2)
|
|
|
|
ret <2 x double> %3
|
|
|
|
}
|
|
|
|
declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
|
|
|
|
|
|
|
|
define <4 x float> @test_hsubps(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a2) {
|
|
|
|
; GENERIC-LABEL: test_hsubps:
|
|
|
|
; GENERIC: # BB#0:
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: hsubps %xmm1, %xmm0 # sched: [5:2.00]
|
|
|
|
; GENERIC-NEXT: hsubps (%rdi), %xmm0 # sched: [11:2.00]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_hsubps:
|
|
|
|
; ATOM: # BB#0:
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: hsubps %xmm1, %xmm0 # sched: [8:4.00]
|
|
|
|
; ATOM-NEXT: hsubps (%rdi), %xmm0 # sched: [9:4.50]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; SLM-LABEL: test_hsubps:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: hsubps %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; SLM-NEXT: hsubps (%rdi), %xmm0 # sched: [6:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_hsubps:
|
|
|
|
; SANDY: # BB#0:
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: vhsubps %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
|
|
|
; SANDY-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [11:2.00]
|
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_hsubps:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: vhsubps %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [5:2.00]
|
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_hsubps:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: vhsubps %xmm1, %xmm0, %xmm0 # sched: [5:2.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [10:2.00]
|
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_hsubps:
|
|
|
|
; SKYLAKE: # BB#0:
|
2017-09-19 14:19:27 +08:00
|
|
|
; SKYLAKE-NEXT: vhsubps %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
|
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_hsubps:
|
|
|
|
; SKX: # BB#0:
|
|
|
|
; SKX-NEXT: vhsubps %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
|
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-LABEL: test_hsubps:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: vhsubps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; BTVER2-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
2017-07-19 10:45:14 +08:00
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_hsubps:
|
|
|
|
; ZNVER1: # BB#0:
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: vhsubps %xmm1, %xmm0, %xmm0 # sched: [100:?]
|
|
|
|
; ZNVER1-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [100:?]
|
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
%1 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
|
|
|
|
%2 = load <4 x float>, <4 x float> *%a2, align 16
|
|
|
|
%3 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %1, <4 x float> %2)
|
|
|
|
ret <4 x float> %3
|
|
|
|
}
|
|
|
|
declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
|
|
|
|
|
|
|
|
define <16 x i8> @test_lddqu(i8* %a0) {
|
|
|
|
; GENERIC-LABEL: test_lddqu:
|
|
|
|
; GENERIC: # BB#0:
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: lddqu (%rdi), %xmm0 # sched: [6:0.50]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_lddqu:
|
|
|
|
; ATOM: # BB#0:
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: lddqu (%rdi), %xmm0 # sched: [3:1.50]
|
|
|
|
; ATOM-NEXT: nop # sched: [1:0.50]
|
|
|
|
; ATOM-NEXT: nop # sched: [1:0.50]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; SLM-LABEL: test_lddqu:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: lddqu (%rdi), %xmm0 # sched: [3:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_lddqu:
|
|
|
|
; SANDY: # BB#0:
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: vlddqu (%rdi), %xmm0 # sched: [6:0.50]
|
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_lddqu:
|
|
|
|
; HASWELL: # BB#0:
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: vlddqu (%rdi), %xmm0 # sched: [1:0.50]
|
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_lddqu:
|
|
|
|
; BROADWELL: # BB#0:
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: vlddqu (%rdi), %xmm0 # sched: [5:0.50]
|
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_lddqu:
|
|
|
|
; SKYLAKE: # BB#0:
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: vlddqu (%rdi), %xmm0 # sched: [6:0.50]
|
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_lddqu:
|
|
|
|
; SKX: # BB#0:
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: vlddqu (%rdi), %xmm0 # sched: [6:0.50]
|
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-LABEL: test_lddqu:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: vlddqu (%rdi), %xmm0 # sched: [5:1.00]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
2017-07-19 10:45:14 +08:00
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_lddqu:
|
|
|
|
; ZNVER1: # BB#0:
|
|
|
|
; ZNVER1-NEXT: vlddqu (%rdi), %xmm0 # sched: [8:0.50]
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
%1 = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %a0)
|
|
|
|
ret <16 x i8> %1
|
|
|
|
}
|
|
|
|
declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8*) nounwind readonly
|
|
|
|
|
2017-08-02 02:16:44 +08:00
|
|
|
define void @test_monitor(i8* %a0, i32 %a1, i32 %a2) {
|
|
|
|
; GENERIC-LABEL: test_monitor:
|
|
|
|
; GENERIC: # BB#0:
|
|
|
|
; GENERIC-NEXT: leaq (%rdi), %rax # sched: [1:0.50]
|
|
|
|
; GENERIC-NEXT: movl %esi, %ecx # sched: [1:0.33]
|
|
|
|
; GENERIC-NEXT: monitor # sched: [100:0.33]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_monitor:
|
|
|
|
; ATOM: # BB#0:
|
|
|
|
; ATOM-NEXT: leaq (%rdi), %rax # sched: [1:1.00]
|
|
|
|
; ATOM-NEXT: movl %esi, %ecx # sched: [1:0.50]
|
|
|
|
; ATOM-NEXT: monitor # sched: [45:22.50]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
|
|
|
;
|
|
|
|
; SLM-LABEL: test_monitor:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: leaq (%rdi), %rax # sched: [1:1.00]
|
|
|
|
; SLM-NEXT: movl %esi, %ecx # sched: [1:0.50]
|
|
|
|
; SLM-NEXT: monitor # sched: [100:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_monitor:
|
|
|
|
; SANDY: # BB#0:
|
|
|
|
; SANDY-NEXT: leaq (%rdi), %rax # sched: [1:0.50]
|
|
|
|
; SANDY-NEXT: movl %esi, %ecx # sched: [1:0.33]
|
|
|
|
; SANDY-NEXT: monitor # sched: [100:0.33]
|
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_monitor:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: leaq (%rdi), %rax # sched: [1:0.50]
|
|
|
|
; HASWELL-NEXT: movl %esi, %ecx # sched: [1:0.25]
|
|
|
|
; HASWELL-NEXT: monitor # sched: [100:0.25]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-08-02 02:16:44 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_monitor:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: leaq (%rdi), %rax # sched: [1:0.50]
|
|
|
|
; BROADWELL-NEXT: movl %esi, %ecx # sched: [1:0.25]
|
|
|
|
; BROADWELL-NEXT: monitor # sched: [100:0.25]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_monitor:
|
|
|
|
; SKYLAKE: # BB#0:
|
|
|
|
; SKYLAKE-NEXT: leaq (%rdi), %rax # sched: [1:0.50]
|
|
|
|
; SKYLAKE-NEXT: movl %esi, %ecx # sched: [1:0.25]
|
|
|
|
; SKYLAKE-NEXT: monitor # sched: [100:0.25]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_monitor:
|
|
|
|
; SKX: # BB#0:
|
|
|
|
; SKX-NEXT: leaq (%rdi), %rax # sched: [1:0.50]
|
|
|
|
; SKX-NEXT: movl %esi, %ecx # sched: [1:0.25]
|
|
|
|
; SKX-NEXT: monitor # sched: [100:0.25]
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-08-02 02:16:44 +08:00
|
|
|
; BTVER2-LABEL: test_monitor:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: leaq (%rdi), %rax # sched: [1:0.50]
|
|
|
|
; BTVER2-NEXT: movl %esi, %ecx # sched: [1:0.17]
|
|
|
|
; BTVER2-NEXT: monitor # sched: [100:0.17]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_monitor:
|
|
|
|
; ZNVER1: # BB#0:
|
|
|
|
; ZNVER1-NEXT: leaq (%rdi), %rax # sched: [1:0.25]
|
|
|
|
; ZNVER1-NEXT: movl %esi, %ecx # sched: [1:0.25]
|
|
|
|
; ZNVER1-NEXT: monitor # sched: [100:?]
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-08-02 02:16:44 +08:00
|
|
|
tail call void @llvm.x86.sse3.monitor(i8* %a0, i32 %a1, i32 %a2)
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
declare void @llvm.x86.sse3.monitor(i8*, i32, i32)
|
|
|
|
|
2017-04-23 21:59:29 +08:00
|
|
|
define <2 x double> @test_movddup(<2 x double> %a0, <2 x double> *%a1) {
|
|
|
|
; GENERIC-LABEL: test_movddup:
|
|
|
|
; GENERIC: # BB#0:
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: movddup {{.*#+}} xmm1 = xmm0[0,0] sched: [1:1.00]
|
|
|
|
; GENERIC-NEXT: movddup {{.*#+}} xmm0 = mem[0,0] sched: [6:0.50]
|
2017-10-14 05:56:45 +08:00
|
|
|
; GENERIC-NEXT: subpd %xmm1, %xmm0 # sched: [3:1.00]
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_movddup:
|
|
|
|
; ATOM: # BB#0:
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: movddup {{.*#+}} xmm1 = mem[0,0] sched: [1:1.00]
|
|
|
|
; ATOM-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]
|
2017-10-14 05:56:45 +08:00
|
|
|
; ATOM-NEXT: subpd %xmm0, %xmm1 # sched: [6:3.00]
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: movapd %xmm1, %xmm0 # sched: [1:0.50]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; SLM-LABEL: test_movddup:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: movddup {{.*#+}} xmm1 = xmm0[0,0] sched: [1:1.00]
|
|
|
|
; SLM-NEXT: movddup {{.*#+}} xmm0 = mem[0,0] sched: [3:1.00]
|
2017-10-14 05:56:45 +08:00
|
|
|
; SLM-NEXT: subpd %xmm1, %xmm0 # sched: [3:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_movddup:
|
|
|
|
; SANDY: # BB#0:
|
|
|
|
; SANDY-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [6:0.50]
|
2017-10-14 05:56:45 +08:00
|
|
|
; SANDY-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_movddup:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [1:0.50]
|
2017-10-14 05:56:45 +08:00
|
|
|
; HASWELL-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_movddup:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [5:0.50]
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_movddup:
|
|
|
|
; SKYLAKE: # BB#0:
|
|
|
|
; SKYLAKE-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [5:0.50]
|
2017-10-14 05:56:45 +08:00
|
|
|
; SKYLAKE-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_movddup:
|
|
|
|
; SKX: # BB#0:
|
|
|
|
; SKX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [5:0.50]
|
2017-10-14 05:56:45 +08:00
|
|
|
; SKX-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [4:0.33]
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-LABEL: test_movddup:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [5:1.00]
|
|
|
|
; BTVER2-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:0.50]
|
2017-10-14 05:56:45 +08:00
|
|
|
; BTVER2-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
2017-07-19 10:45:14 +08:00
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_movddup:
|
|
|
|
; ZNVER1: # BB#0:
|
|
|
|
; ZNVER1-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [8:0.50]
|
|
|
|
; ZNVER1-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:0.50]
|
2017-10-14 05:56:45 +08:00
|
|
|
; ZNVER1-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
%1 = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> zeroinitializer
|
|
|
|
%2 = load <2 x double>, <2 x double> *%a1, align 16
|
|
|
|
%3 = shufflevector <2 x double> %2, <2 x double> undef, <2 x i32> zeroinitializer
|
2017-10-14 05:56:45 +08:00
|
|
|
%4 = fsub <2 x double> %3, %1 ; Use fsub to stop the movddup from being folded as a broadcast load in avx512vl.
|
2017-04-23 21:59:29 +08:00
|
|
|
ret <2 x double> %4
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x float> @test_movshdup(<4 x float> %a0, <4 x float> *%a1) {
|
|
|
|
; GENERIC-LABEL: test_movshdup:
|
|
|
|
; GENERIC: # BB#0:
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] sched: [1:1.00]
|
|
|
|
; GENERIC-NEXT: movshdup {{.*#+}} xmm0 = mem[1,1,3,3] sched: [6:0.50]
|
|
|
|
; GENERIC-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_movshdup:
|
|
|
|
; ATOM: # BB#0:
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: movshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [1:1.00]
|
|
|
|
; ATOM-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]
|
|
|
|
; ATOM-NEXT: addps %xmm0, %xmm1 # sched: [5:5.00]
|
|
|
|
; ATOM-NEXT: movaps %xmm1, %xmm0 # sched: [1:0.50]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; SLM-LABEL: test_movshdup:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] sched: [1:1.00]
|
|
|
|
; SLM-NEXT: movshdup {{.*#+}} xmm0 = mem[1,1,3,3] sched: [3:1.00]
|
|
|
|
; SLM-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_movshdup:
|
|
|
|
; SANDY: # BB#0:
|
|
|
|
; SANDY-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [6:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
; SANDY-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_movshdup:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
; HASWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_movshdup:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [5:0.50]
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_movshdup:
|
|
|
|
; SKYLAKE: # BB#0:
|
|
|
|
; SKYLAKE-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [6:0.50]
|
2017-09-19 14:19:27 +08:00
|
|
|
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_movshdup:
|
|
|
|
; SKX: # BB#0:
|
|
|
|
; SKX-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [6:0.50]
|
|
|
|
; SKX-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
|
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-LABEL: test_movshdup:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [5:1.00]
|
|
|
|
; BTVER2-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:0.50]
|
|
|
|
; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
2017-07-19 10:45:14 +08:00
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_movshdup:
|
|
|
|
; ZNVER1: # BB#0:
|
|
|
|
; ZNVER1-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [8:0.50]
|
|
|
|
; ZNVER1-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:0.50]
|
|
|
|
; ZNVER1-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
%1 = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
|
|
|
%2 = load <4 x float>, <4 x float> *%a1, align 16
|
|
|
|
%3 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
|
|
|
%4 = fadd <4 x float> %1, %3
|
|
|
|
ret <4 x float> %4
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x float> @test_movsldup(<4 x float> %a0, <4 x float> *%a1) {
|
|
|
|
; GENERIC-LABEL: test_movsldup:
|
|
|
|
; GENERIC: # BB#0:
|
2017-08-01 23:14:35 +08:00
|
|
|
; GENERIC-NEXT: movsldup {{.*#+}} xmm1 = xmm0[0,0,2,2] sched: [1:1.00]
|
|
|
|
; GENERIC-NEXT: movsldup {{.*#+}} xmm0 = mem[0,0,2,2] sched: [6:0.50]
|
|
|
|
; GENERIC-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_movsldup:
|
|
|
|
; ATOM: # BB#0:
|
2017-08-01 17:15:43 +08:00
|
|
|
; ATOM-NEXT: movsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [1:1.00]
|
|
|
|
; ATOM-NEXT: movsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]
|
|
|
|
; ATOM-NEXT: addps %xmm0, %xmm1 # sched: [5:5.00]
|
|
|
|
; ATOM-NEXT: movaps %xmm1, %xmm0 # sched: [1:0.50]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; SLM-LABEL: test_movsldup:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: movsldup {{.*#+}} xmm1 = xmm0[0,0,2,2] sched: [1:1.00]
|
|
|
|
; SLM-NEXT: movsldup {{.*#+}} xmm0 = mem[0,0,2,2] sched: [3:1.00]
|
|
|
|
; SLM-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_movsldup:
|
|
|
|
; SANDY: # BB#0:
|
|
|
|
; SANDY-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [6:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
; SANDY-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information.
Please note that the patch extensively affects the X86 MC instr scheduling for SNB.
Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.
The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script.
Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb
Differential Revision: https://reviews.llvm.org/D35019#inline-304691
llvm-svn: 307529
2017-07-10 17:53:16 +08:00
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_movsldup:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
; HASWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-04-23 21:59:29 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_movsldup:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [5:0.50]
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_movsldup:
|
|
|
|
; SKYLAKE: # BB#0:
|
|
|
|
; SKYLAKE-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [6:0.50]
|
2017-09-19 14:19:27 +08:00
|
|
|
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
|
2017-10-17 14:47:04 +08:00
|
|
|
; SKYLAKE-NEXT: retq # sched: [7:1.00]
|
2017-08-30 16:08:50 +08:00
|
|
|
;
|
2017-10-06 21:40:29 +08:00
|
|
|
; SKX-LABEL: test_movsldup:
|
|
|
|
; SKX: # BB#0:
|
|
|
|
; SKX-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [6:0.50]
|
|
|
|
; SKX-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
|
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-04-23 21:59:29 +08:00
|
|
|
; BTVER2-LABEL: test_movsldup:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [5:1.00]
|
|
|
|
; BTVER2-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:0.50]
|
|
|
|
; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
2017-07-19 10:45:14 +08:00
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_movsldup:
|
|
|
|
; ZNVER1: # BB#0:
|
|
|
|
; ZNVER1-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [8:0.50]
|
|
|
|
; ZNVER1-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:0.50]
|
|
|
|
; ZNVER1-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-04-23 21:59:29 +08:00
|
|
|
%1 = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
|
|
|
%2 = load <4 x float>, <4 x float> *%a1, align 16
|
|
|
|
%3 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
|
|
|
%4 = fadd <4 x float> %1, %3
|
|
|
|
ret <4 x float> %4
|
|
|
|
}
|
2017-08-02 02:16:44 +08:00
|
|
|
|
|
|
|
define void @test_mwait(i32 %a0, i32 %a1) {
|
|
|
|
; GENERIC-LABEL: test_mwait:
|
|
|
|
; GENERIC: # BB#0:
|
|
|
|
; GENERIC-NEXT: movl %edi, %ecx # sched: [1:0.33]
|
|
|
|
; GENERIC-NEXT: movl %esi, %eax # sched: [1:0.33]
|
|
|
|
; GENERIC-NEXT: mwait # sched: [100:0.33]
|
|
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
|
|
;
|
|
|
|
; ATOM-LABEL: test_mwait:
|
|
|
|
; ATOM: # BB#0:
|
|
|
|
; ATOM-NEXT: movl %edi, %ecx # sched: [1:0.50]
|
|
|
|
; ATOM-NEXT: movl %esi, %eax # sched: [1:0.50]
|
|
|
|
; ATOM-NEXT: mwait # sched: [46:23.00]
|
|
|
|
; ATOM-NEXT: retq # sched: [79:39.50]
|
|
|
|
;
|
|
|
|
; SLM-LABEL: test_mwait:
|
|
|
|
; SLM: # BB#0:
|
|
|
|
; SLM-NEXT: movl %edi, %ecx # sched: [1:0.50]
|
|
|
|
; SLM-NEXT: movl %esi, %eax # sched: [1:0.50]
|
|
|
|
; SLM-NEXT: mwait # sched: [100:1.00]
|
|
|
|
; SLM-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; SANDY-LABEL: test_mwait:
|
|
|
|
; SANDY: # BB#0:
|
|
|
|
; SANDY-NEXT: movl %edi, %ecx # sched: [1:0.33]
|
|
|
|
; SANDY-NEXT: movl %esi, %eax # sched: [1:0.33]
|
|
|
|
; SANDY-NEXT: mwait # sched: [100:0.33]
|
|
|
|
; SANDY-NEXT: retq # sched: [1:1.00]
|
|
|
|
;
|
|
|
|
; HASWELL-LABEL: test_mwait:
|
|
|
|
; HASWELL: # BB#0:
|
|
|
|
; HASWELL-NEXT: movl %edi, %ecx # sched: [1:0.25]
|
|
|
|
; HASWELL-NEXT: movl %esi, %eax # sched: [1:0.25]
|
2017-08-28 18:04:16 +08:00
|
|
|
; HASWELL-NEXT: mwait # sched: [20:2.50]
|
|
|
|
; HASWELL-NEXT: retq # sched: [2:1.00]
|
2017-08-02 02:16:44 +08:00
|
|
|
;
|
2017-10-17 21:45:39 +08:00
|
|
|
; BROADWELL-LABEL: test_mwait:
|
|
|
|
; BROADWELL: # BB#0:
|
|
|
|
; BROADWELL-NEXT: movl %edi, %ecx # sched: [1:0.25]
|
|
|
|
; BROADWELL-NEXT: movl %esi, %eax # sched: [1:0.25]
|
2017-10-25 04:19:47 +08:00
|
|
|
; BROADWELL-NEXT: mwait # sched: [100:0.25]
|
|
|
|
; BROADWELL-NEXT: retq # sched: [7:1.00]
|
2017-10-17 21:45:39 +08:00
|
|
|
;
|
2017-08-30 16:08:50 +08:00
|
|
|
; SKYLAKE-LABEL: test_mwait:
|
|
|
|
; SKYLAKE: # BB#0:
|
|
|
|
; SKYLAKE-NEXT: movl %edi, %ecx # sched: [1:0.25]
|
|
|
|
; SKYLAKE-NEXT: movl %esi, %eax # sched: [1:0.25]
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; SKYLAKE-NEXT: mwait # sched: [20:2.50]
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2017-10-17 14:47:04 +08:00
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; SKYLAKE-NEXT: retq # sched: [7:1.00]
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2017-08-30 16:08:50 +08:00
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|
|
;
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2017-10-06 21:40:29 +08:00
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|
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; SKX-LABEL: test_mwait:
|
|
|
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; SKX: # BB#0:
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|
|
|
; SKX-NEXT: movl %edi, %ecx # sched: [1:0.25]
|
|
|
|
; SKX-NEXT: movl %esi, %eax # sched: [1:0.25]
|
|
|
|
; SKX-NEXT: mwait # sched: [20:2.50]
|
2017-10-08 20:52:54 +08:00
|
|
|
; SKX-NEXT: retq # sched: [7:1.00]
|
2017-10-06 21:40:29 +08:00
|
|
|
;
|
2017-08-02 02:16:44 +08:00
|
|
|
; BTVER2-LABEL: test_mwait:
|
|
|
|
; BTVER2: # BB#0:
|
|
|
|
; BTVER2-NEXT: movl %edi, %ecx # sched: [1:0.17]
|
|
|
|
; BTVER2-NEXT: movl %esi, %eax # sched: [1:0.17]
|
|
|
|
; BTVER2-NEXT: mwait # sched: [100:0.17]
|
|
|
|
; BTVER2-NEXT: retq # sched: [4:1.00]
|
|
|
|
;
|
|
|
|
; ZNVER1-LABEL: test_mwait:
|
|
|
|
; ZNVER1: # BB#0:
|
|
|
|
; ZNVER1-NEXT: movl %edi, %ecx # sched: [1:0.25]
|
|
|
|
; ZNVER1-NEXT: movl %esi, %eax # sched: [1:0.25]
|
|
|
|
; ZNVER1-NEXT: mwait # sched: [100:?]
|
AMD family 17h (znver1) scheduler model update.
Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
(move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
for SSE4A, BMI, BMI2 and SHA instructions.
Patch by Ganesh Gopalasubramanian
Reviewers: RKSimon, craig.topper
Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D36617
llvm-svn: 312237
2017-08-31 20:38:35 +08:00
|
|
|
; ZNVER1-NEXT: retq # sched: [1:0.50]
|
2017-08-02 02:16:44 +08:00
|
|
|
tail call void @llvm.x86.sse3.mwait(i32 %a0, i32 %a1)
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
declare void @llvm.x86.sse3.mwait(i32, i32)
|