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llvm-project/llvm/test/CodeGen/X86/pr34381.ll

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[X86] Add test case I forgot to commit with r312285. llvm-svn: 312335
2017-09-02 00:40:24 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Teach fastisel to handle zext/sext i8->i16 and sext i1->i8/i16/i32/i64 Summary: ZExt and SExt from i8 to i16 aren't implemented in the autogenerated fast isel table because normal isel does a zext/sext to 32-bits and a subreg extract to avoid a partial register write or false dependency on the upper bits of the destination. This means without handling in fast isel we end up triggering a fast isel abort. We had no custom sign extend handling at all so while I was there I went ahead and implemented sext i1->i8/i16/i32/i64 which was also missing. This generates an i1->i8 sign extend using a mask with 1, then an 8-bit negate, then continues with a sext from i8. A better sequence would be a wider and/negate, but would require more custom code. Fast isel tests are a mess and I couldn't find a good home for the tests so I created a new one. The test pr34381.ll had to have fast-isel removed because it was relying on a fast isel abort to hit the bug. The test case still seems valid with fast-isel disabled though some of the instructions changed. Reviewers: spatel, zvi, igorb, guyblank, RKSimon Reviewed By: guyblank Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37320 llvm-svn: 312422
2017-09-03 02:53:46 +08:00
;RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=slow-incdec | FileCheck %s
[X86] Add test case I forgot to commit with r312285. llvm-svn: 312335
2017-09-02 00:40:24 +08:00
@var_21 = external constant i32, align 4
@var_29 = external constant i8, align 1
@var_390 = external global i32, align 4
@var_11 = external constant i8, align 1
@var_370 = external global i8, align 1
; Function Attrs: noinline nounwind optnone uwtable
define void @_Z3foov() {
; CHECK-LABEL: _Z3foov:
; CHECK: # BB#0: # %entry
[X86] Teach fastisel to handle zext/sext i8->i16 and sext i1->i8/i16/i32/i64 Summary: ZExt and SExt from i8 to i16 aren't implemented in the autogenerated fast isel table because normal isel does a zext/sext to 32-bits and a subreg extract to avoid a partial register write or false dependency on the upper bits of the destination. This means without handling in fast isel we end up triggering a fast isel abort. We had no custom sign extend handling at all so while I was there I went ahead and implemented sext i1->i8/i16/i32/i64 which was also missing. This generates an i1->i8 sign extend using a mask with 1, then an 8-bit negate, then continues with a sext from i8. A better sequence would be a wider and/negate, but would require more custom code. Fast isel tests are a mess and I couldn't find a good home for the tests so I created a new one. The test pr34381.ll had to have fast-isel removed because it was relying on a fast isel abort to hit the bug. The test case still seems valid with fast-isel disabled though some of the instructions changed. Reviewers: spatel, zvi, igorb, guyblank, RKSimon Reviewed By: guyblank Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37320 llvm-svn: 312422
2017-09-03 02:53:46 +08:00
; CHECK-NEXT: movsbl {{.*}}(%rip), %eax
; CHECK-NEXT: negl %eax
; CHECK-NEXT: cmpl %eax, {{.*}}(%rip)
; CHECK-NEXT: setb %al
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: addb $-1, %al
; CHECK-NEXT: sete %cl
[X86] Add test case I forgot to commit with r312285. llvm-svn: 312335
2017-09-02 00:40:24 +08:00
; CHECK-NEXT: movl %ecx, {{.*}}(%rip)
[X86] Teach fastisel to handle zext/sext i8->i16 and sext i1->i8/i16/i32/i64 Summary: ZExt and SExt from i8 to i16 aren't implemented in the autogenerated fast isel table because normal isel does a zext/sext to 32-bits and a subreg extract to avoid a partial register write or false dependency on the upper bits of the destination. This means without handling in fast isel we end up triggering a fast isel abort. We had no custom sign extend handling at all so while I was there I went ahead and implemented sext i1->i8/i16/i32/i64 which was also missing. This generates an i1->i8 sign extend using a mask with 1, then an 8-bit negate, then continues with a sext from i8. A better sequence would be a wider and/negate, but would require more custom code. Fast isel tests are a mess and I couldn't find a good home for the tests so I created a new one. The test pr34381.ll had to have fast-isel removed because it was relying on a fast isel abort to hit the bug. The test case still seems valid with fast-isel disabled though some of the instructions changed. Reviewers: spatel, zvi, igorb, guyblank, RKSimon Reviewed By: guyblank Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37320 llvm-svn: 312422
2017-09-03 02:53:46 +08:00
; CHECK-NEXT: movb {{.*}}(%rip), %al
; CHECK-NEXT: movb %al, {{.*}}(%rip)
[X86] Add test case I forgot to commit with r312285. llvm-svn: 312335
2017-09-02 00:40:24 +08:00
; CHECK-NEXT: retq
entry:
%0 = load i32, i32* @var_21, align 4
%1 = load i8, i8* @var_29, align 1
%conv = sext i8 %1 to i32
%sub = sub nsw i32 0, %conv
%cmp = icmp ult i32 %0, %sub
%conv1 = zext i1 %cmp to i32
%add = add nsw i32 %conv1, -1
%conv2 = trunc i32 %add to i8
%tobool = icmp ne i8 %conv2, 0
%lnot = xor i1 %tobool, true
%conv3 = zext i1 %lnot to i32
store i32 %conv3, i32* @var_390, align 4
%2 = load i8, i8* @var_11, align 1
%conv4 = sext i8 %2 to i16
%conv5 = trunc i16 %conv4 to i8
store i8 %conv5, i8* @var_370, align 1
ret void
}