2015-11-24 05:33:58 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2015-04-26 04:41:51 +08:00
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX
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2017-11-13 13:25:21 +08:00
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512f < %s | FileCheck %s --check-prefix=AVX
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2015-02-20 00:59:11 +08:00
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2015-12-31 17:45:16 +08:00
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; Verify we fold loads into unary sse intrinsics only when optimizing for size
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2015-02-20 00:59:11 +08:00
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define float @rcpss(float* %a) {
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2015-04-26 04:41:51 +08:00
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; SSE-LABEL: rcpss:
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; SSE: # BB#0:
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2017-11-13 13:25:21 +08:00
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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2015-12-31 17:45:16 +08:00
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; SSE-NEXT: rcpss %xmm0, %xmm0
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2015-04-26 04:41:51 +08:00
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; SSE-NEXT: retq
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;
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; AVX-LABEL: rcpss:
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; AVX: # BB#0:
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2017-11-13 13:25:21 +08:00
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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2015-12-31 17:45:16 +08:00
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; AVX-NEXT: vrcpss %xmm0, %xmm0, %xmm0
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2015-04-26 04:41:51 +08:00
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; AVX-NEXT: retq
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2015-02-28 05:17:42 +08:00
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%ld = load float, float* %a
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2015-02-20 00:59:11 +08:00
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%ins = insertelement <4 x float> undef, float %ld, i32 0
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%res = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %ins)
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%ext = extractelement <4 x float> %res, i32 0
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ret float %ext
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}
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define float @rsqrtss(float* %a) {
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2015-04-26 04:41:51 +08:00
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; SSE-LABEL: rsqrtss:
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; SSE: # BB#0:
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2017-11-13 13:25:21 +08:00
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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2015-12-31 17:45:16 +08:00
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; SSE-NEXT: rsqrtss %xmm0, %xmm0
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2015-04-26 04:41:51 +08:00
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; SSE-NEXT: retq
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;
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; AVX-LABEL: rsqrtss:
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; AVX: # BB#0:
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2017-11-13 13:25:21 +08:00
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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2015-12-31 17:45:16 +08:00
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; AVX-NEXT: vrsqrtss %xmm0, %xmm0, %xmm0
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2015-04-26 04:41:51 +08:00
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; AVX-NEXT: retq
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2015-02-28 05:17:42 +08:00
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%ld = load float, float* %a
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2015-02-20 00:59:11 +08:00
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%ins = insertelement <4 x float> undef, float %ld, i32 0
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%res = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %ins)
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%ext = extractelement <4 x float> %res, i32 0
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ret float %ext
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}
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define float @sqrtss(float* %a) {
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2015-04-26 04:41:51 +08:00
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; SSE-LABEL: sqrtss:
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; SSE: # BB#0:
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2017-11-13 13:25:21 +08:00
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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2015-12-31 17:45:16 +08:00
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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2015-04-26 04:41:51 +08:00
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtss:
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; AVX: # BB#0:
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2017-11-13 13:25:21 +08:00
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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2015-12-31 17:45:16 +08:00
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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2015-04-26 04:41:51 +08:00
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; AVX-NEXT: retq
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2015-02-28 05:17:42 +08:00
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%ld = load float, float* %a
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2015-02-20 00:59:11 +08:00
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%ins = insertelement <4 x float> undef, float %ld, i32 0
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%res = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %ins)
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%ext = extractelement <4 x float> %res, i32 0
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ret float %ext
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}
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define double @sqrtsd(double* %a) {
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2015-04-26 04:41:51 +08:00
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; SSE-LABEL: sqrtsd:
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; SSE: # BB#0:
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2017-11-13 13:25:21 +08:00
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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2015-12-31 17:45:16 +08:00
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; SSE-NEXT: sqrtsd %xmm0, %xmm0
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2015-04-26 04:41:51 +08:00
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtsd:
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; AVX: # BB#0:
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2017-11-13 13:25:21 +08:00
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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2015-12-31 17:45:16 +08:00
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; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
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2015-04-26 04:41:51 +08:00
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; AVX-NEXT: retq
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2015-02-28 05:17:42 +08:00
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%ld = load double, double* %a
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2015-02-20 00:59:11 +08:00
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%ins = insertelement <2 x double> undef, double %ld, i32 0
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%res = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %ins)
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%ext = extractelement <2 x double> %res, i32 0
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ret double %ext
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}
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2015-12-31 17:45:16 +08:00
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define float @rcpss_size(float* %a) optsize {
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; SSE-LABEL: rcpss_size:
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; SSE: # BB#0:
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; SSE-NEXT: rcpss (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: rcpss_size:
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; AVX: # BB#0:
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; AVX-NEXT: vrcpss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%ld = load float, float* %a
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%ins = insertelement <4 x float> undef, float %ld, i32 0
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%res = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %ins)
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%ext = extractelement <4 x float> %res, i32 0
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ret float %ext
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}
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2017-11-13 13:25:23 +08:00
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define <4 x float> @rcpss_full_size(<4 x float>* %a) optsize {
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; SSE-LABEL: rcpss_full_size:
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; SSE: # BB#0:
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2017-11-13 13:25:24 +08:00
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; SSE-NEXT: rcpss (%rdi), %xmm0
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2017-11-13 13:25:23 +08:00
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; SSE-NEXT: retq
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;
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; AVX-LABEL: rcpss_full_size:
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; AVX: # BB#0:
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2017-11-13 13:25:24 +08:00
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; AVX-NEXT: vrcpss (%rdi), %xmm0, %xmm0
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2017-11-13 13:25:23 +08:00
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; AVX-NEXT: retq
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%ld = load <4 x float>, <4 x float>* %a
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%res = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %ld)
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ret <4 x float> %res
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}
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2015-12-31 17:45:16 +08:00
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define float @rsqrtss_size(float* %a) optsize {
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; SSE-LABEL: rsqrtss_size:
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; SSE: # BB#0:
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; SSE-NEXT: rsqrtss (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: rsqrtss_size:
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; AVX: # BB#0:
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; AVX-NEXT: vrsqrtss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%ld = load float, float* %a
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%ins = insertelement <4 x float> undef, float %ld, i32 0
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%res = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %ins)
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%ext = extractelement <4 x float> %res, i32 0
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ret float %ext
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}
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2017-11-13 13:25:23 +08:00
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define <4 x float> @rsqrtss_full_size(<4 x float>* %a) optsize {
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; SSE-LABEL: rsqrtss_full_size:
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; SSE: # BB#0:
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2017-11-13 13:25:24 +08:00
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; SSE-NEXT: rsqrtss (%rdi), %xmm0
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2017-11-13 13:25:23 +08:00
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; SSE-NEXT: retq
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;
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; AVX-LABEL: rsqrtss_full_size:
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; AVX: # BB#0:
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2017-11-13 13:25:24 +08:00
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; AVX-NEXT: vrsqrtss (%rdi), %xmm0, %xmm0
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2017-11-13 13:25:23 +08:00
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; AVX-NEXT: retq
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%ld = load <4 x float>, <4 x float>* %a
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%res = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %ld)
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ret <4 x float> %res
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}
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2015-12-31 17:45:16 +08:00
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define float @sqrtss_size(float* %a) optsize{
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; SSE-LABEL: sqrtss_size:
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; SSE: # BB#0:
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; SSE-NEXT: sqrtss (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtss_size:
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; AVX: # BB#0:
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; AVX-NEXT: vsqrtss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%ld = load float, float* %a
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%ins = insertelement <4 x float> undef, float %ld, i32 0
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%res = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %ins)
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%ext = extractelement <4 x float> %res, i32 0
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ret float %ext
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}
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2017-11-13 13:25:23 +08:00
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define <4 x float> @sqrtss_full_size(<4 x float>* %a) optsize{
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; SSE-LABEL: sqrtss_full_size:
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; SSE: # BB#0:
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2017-11-13 13:25:24 +08:00
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; SSE-NEXT: sqrtss (%rdi), %xmm0
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2017-11-13 13:25:23 +08:00
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtss_full_size:
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; AVX: # BB#0:
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2017-11-13 13:25:24 +08:00
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; AVX-NEXT: vsqrtss (%rdi), %xmm0, %xmm0
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2017-11-13 13:25:23 +08:00
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; AVX-NEXT: retq
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%ld = load <4 x float>, <4 x float>* %a
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%res = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %ld)
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ret <4 x float> %res
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}
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2015-12-31 17:45:16 +08:00
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define double @sqrtsd_size(double* %a) optsize {
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; SSE-LABEL: sqrtsd_size:
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; SSE: # BB#0:
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; SSE-NEXT: sqrtsd (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtsd_size:
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; AVX: # BB#0:
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; AVX-NEXT: vsqrtsd (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%ld = load double, double* %a
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%ins = insertelement <2 x double> undef, double %ld, i32 0
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%res = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %ins)
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%ext = extractelement <2 x double> %res, i32 0
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ret double %ext
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}
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2015-02-20 00:59:11 +08:00
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2017-11-13 13:25:23 +08:00
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define <2 x double> @sqrtsd_full_size(<2 x double>* %a) optsize {
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; SSE-LABEL: sqrtsd_full_size:
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; SSE: # BB#0:
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2017-11-13 13:25:24 +08:00
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; SSE-NEXT: sqrtsd (%rdi), %xmm0
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2017-11-13 13:25:23 +08:00
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtsd_full_size:
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; AVX: # BB#0:
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2017-11-13 13:25:24 +08:00
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; AVX-NEXT: vsqrtsd (%rdi), %xmm0, %xmm0
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2017-11-13 13:25:23 +08:00
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; AVX-NEXT: retq
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%ld = load <2 x double>, <2 x double>* %a
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%res = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %ld)
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ret <2 x double> %res
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}
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2015-02-20 00:59:11 +08:00
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declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
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