[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
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# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
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# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
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2017-02-10 15:05:56 +08:00
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--- |
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define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
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%ret = add i8 %arg1, %arg2
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ret i8 %ret
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}
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2017-03-03 16:06:46 +08:00
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2017-02-10 15:05:56 +08:00
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define i16 @test_add_i16(i16 %arg1, i16 %arg2) {
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%ret = add i16 %arg1, %arg2
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ret i16 %ret
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}
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2017-03-03 16:06:46 +08:00
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2017-02-10 15:05:56 +08:00
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define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
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%ret = add i32 %arg1, %arg2
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ret i32 %ret
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}
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2017-03-03 16:06:46 +08:00
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2017-02-10 15:05:56 +08:00
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define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
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%ret = add i64 %arg1, %arg2
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ret i64 %ret
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}
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2017-05-08 17:03:37 +08:00
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define void @test_mul_gpr() {
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ret void
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}
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2017-03-03 16:06:46 +08:00
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define float @test_add_float(float %arg1, float %arg2) {
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%ret = fadd float %arg1, %arg2
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ret float %ret
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}
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define double @test_add_double(double %arg1, double %arg2) {
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%ret = fadd double %arg1, %arg2
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ret double %ret
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}
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2017-10-25 02:04:54 +08:00
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2017-06-27 15:01:54 +08:00
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define void @test_fsub_float() {
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%ret1 = fsub float undef, undef
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%ret2 = fsub double undef, undef
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ret void
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}
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define void @test_fmul_float() {
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%ret1 = fmul float undef, undef
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%ret2 = fmul double undef, undef
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ret void
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}
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define void @test_fdiv_float() {
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%ret1 = fdiv float undef, undef
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%ret2 = fdiv double undef, undef
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ret void
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}
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2017-10-25 02:04:54 +08:00
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2017-03-03 16:06:46 +08:00
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[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
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define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
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%ret = add <4 x i32> %arg1, %arg2
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ret <4 x i32> %ret
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2017-03-03 16:06:46 +08:00
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}
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|
|
|
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
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define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
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%ret = fadd <4 x float> %arg1, %arg2
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ret <4 x float> %ret
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2017-03-03 16:06:46 +08:00
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}
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2017-03-23 23:25:57 +08:00
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define i8 @test_load_i8(i8* %p1) {
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%r = load i8, i8* %p1
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ret i8 %r
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}
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define i16 @test_load_i16(i16* %p1) {
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%r = load i16, i16* %p1
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ret i16 %r
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}
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define i32 @test_load_i32(i32* %p1) {
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%r = load i32, i32* %p1
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ret i32 %r
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}
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define i64 @test_load_i64(i64* %p1) {
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%r = load i64, i64* %p1
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ret i64 %r
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}
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define float @test_load_float(float* %p1) {
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%r = load float, float* %p1
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ret float %r
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}
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define double @test_load_double(double* %p1) {
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%r = load double, double* %p1
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ret double %r
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}
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define <4 x i32> @test_load_v4i32(<4 x i32>* %p1) {
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%r = load <4 x i32>, <4 x i32>* %p1, align 16
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ret <4 x i32> %r
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}
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define i32* @test_store_i32(i32 %val, i32* %p1) {
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store i32 %val, i32* %p1
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ret i32* %p1
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}
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define i64* @test_store_i64(i64 %val, i64* %p1) {
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store i64 %val, i64* %p1
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ret i64* %p1
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}
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define float* @test_store_float(float %val, float* %p1) {
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store float %val, float* %p1
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ret float* %p1
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}
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define double* @test_store_double(double %val, double* %p1) {
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store double %val, double* %p1
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ret double* %p1
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}
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2017-04-12 20:54:54 +08:00
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define void @constInt_check() {
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ret void
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}
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2017-04-19 19:34:59 +08:00
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define void @trunc_check() {
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ret void
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}
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2017-05-08 17:40:43 +08:00
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define void @test_gep() {
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%p1 = getelementptr i32, i32* undef, i32 5
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%p2 = getelementptr i32, i32* undef, i64 5
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ret void
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}
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2017-05-11 15:17:40 +08:00
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define i1 @test_icmp_eq_i8(i8 %a, i8 %b) {
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%r = icmp eq i8 %a, %b
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ret i1 %r
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}
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define i1 @test_icmp_eq_i16(i16 %a, i16 %b) {
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%r = icmp eq i16 %a, %b
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ret i1 %r
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}
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define i1 @test_icmp_eq_i32(i32 %a, i32 %b) {
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%r = icmp eq i32 %a, %b
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ret i1 %r
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}
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define i1 @test_icmp_eq_i64(i64 %a, i64 %b) {
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%r = icmp eq i64 %a, %b
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ret i1 %r
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}
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2017-06-28 19:39:04 +08:00
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define i8 @test_xor_i8() {
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%ret = xor i8 undef, undef
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ret i8 %ret
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}
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define i16 @test_or_i16() {
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%ret = or i16 undef, undef
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ret i16 %ret
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}
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define i32 @test_and_i32() {
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%ret = and i32 undef, undef
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ret i32 %ret
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}
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define i64 @test_and_i64() {
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%ret = and i64 undef, undef
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ret i64 %ret
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}
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2017-07-02 16:58:29 +08:00
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@g_int = global i32 0, align 4
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define i32* @test_global_ptrv() {
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entry:
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ret i32* @g_int
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}
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2017-10-25 02:04:54 +08:00
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2017-08-24 15:06:27 +08:00
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define i8 @test_undef() {
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ret i8 undef
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}
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define i8 @test_undef2(i8 %a) {
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%r = add i8 %a, undef
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ret i8 %r
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}
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define float @test_undef3() {
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ret float undef
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}
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define float @test_undef4(float %a) {
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%r = fadd float %a, undef
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ret float %r
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2017-09-04 17:06:45 +08:00
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}
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2017-10-25 02:04:54 +08:00
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2017-09-04 17:06:45 +08:00
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define i32 @test_i32(i32 %a, i32 %f, i32 %t) {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i32 [ %f, %cond.true ], [ %t, %cond.false ]
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ret i32 %cond
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}
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define float @test_float(i32 %a, float %f, float %t) {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi float [ %f, %cond.true ], [ %t, %cond.false ]
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ret float %cond
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}
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2017-09-13 17:05:23 +08:00
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define double @test_fpext(float %a) {
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entry:
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%conv = fpext float %a to double
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ret double %conv
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}
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2017-10-25 02:04:54 +08:00
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define void @test_fconstant() {
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ret void
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2017-09-17 16:08:13 +08:00
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}
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2017-09-13 17:05:23 +08:00
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2017-02-10 15:05:56 +08:00
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...
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---
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name: test_add_i8
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alignment: 4
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legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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# CHECK-LABEL: name: test_add_i8
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# CHECK: registers:
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2017-06-06 16:16:19 +08:00
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# CHECK: - { id: 0, class: gpr, preferred-register: '' }
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# CHECK: - { id: 1, class: gpr, preferred-register: '' }
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# CHECK: - { id: 2, class: gpr, preferred-register: '' }
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2017-03-03 16:06:46 +08:00
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registers:
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2017-02-10 15:05:56 +08:00
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi, %esi
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2017-03-03 16:06:46 +08:00
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2017-09-17 16:30:42 +08:00
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%0(s8) = COPY %dil
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%1(s8) = COPY %sil
|
2017-02-10 15:05:56 +08:00
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%2(s8) = G_ADD %0, %1
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%al = COPY %2(s8)
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RET 0, implicit %al
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|
...
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|
|
|
---
|
|
|
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name: test_add_i16
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|
alignment: 4
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|
legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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# CHECK-LABEL: name: test_add_i16
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# CHECK: registers:
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2017-06-06 16:16:19 +08:00
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# CHECK: - { id: 0, class: gpr, preferred-register: '' }
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# CHECK: - { id: 1, class: gpr, preferred-register: '' }
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# CHECK: - { id: 2, class: gpr, preferred-register: '' }
|
2017-03-03 16:06:46 +08:00
|
|
|
registers:
|
2017-02-10 15:05:56 +08:00
|
|
|
- { id: 0, class: _ }
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|
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- { id: 1, class: _ }
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|
|
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- { id: 2, class: _ }
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|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
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|
|
liveins: %edi, %esi
|
2017-03-03 16:06:46 +08:00
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|
|
2017-09-17 16:30:42 +08:00
|
|
|
%0(s16) = COPY %di
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|
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|
%1(s16) = COPY %si
|
2017-02-10 15:05:56 +08:00
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|
%2(s16) = G_ADD %0, %1
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|
|
%ax = COPY %2(s16)
|
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|
|
RET 0, implicit %ax
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|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_add_i32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
# CHECK-LABEL: name: test_add_i32
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|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 2, class: gpr, preferred-register: '' }
|
2017-03-03 16:06:46 +08:00
|
|
|
registers:
|
2017-02-10 15:05:56 +08:00
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %edi, %esi
|
2017-03-03 16:06:46 +08:00
|
|
|
|
2017-02-10 15:05:56 +08:00
|
|
|
%0(s32) = COPY %edi
|
|
|
|
%1(s32) = COPY %esi
|
|
|
|
%2(s32) = G_ADD %0, %1
|
|
|
|
%eax = COPY %2(s32)
|
|
|
|
RET 0, implicit %eax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_add_i64
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
# CHECK-LABEL: name: test_add_i64
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 2, class: gpr, preferred-register: '' }
|
2017-03-03 16:06:46 +08:00
|
|
|
registers:
|
2017-02-10 15:05:56 +08:00
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi, %rsi
|
2017-03-03 16:06:46 +08:00
|
|
|
|
2017-02-10 15:05:56 +08:00
|
|
|
%0(s64) = COPY %rdi
|
|
|
|
%1(s64) = COPY %rsi
|
|
|
|
%2(s64) = G_ADD %0, %1
|
|
|
|
%rax = COPY %2(s64)
|
|
|
|
RET 0, implicit %rax
|
|
|
|
|
|
|
|
...
|
2017-03-03 16:06:46 +08:00
|
|
|
---
|
2017-05-08 17:03:37 +08:00
|
|
|
name: test_mul_gpr
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
# CHECK-LABEL: name: test_mul_gpr
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 3, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 4, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 5, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 6, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 7, class: gpr, preferred-register: '' }
|
2017-05-08 17:03:37 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
- { id: 3, class: _ }
|
|
|
|
- { id: 4, class: _ }
|
|
|
|
- { id: 5, class: _ }
|
|
|
|
- { id: 6, class: _ }
|
2017-10-25 02:04:54 +08:00
|
|
|
- { id: 7, class: _ }
|
2017-05-08 17:03:37 +08:00
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
2017-10-25 02:04:54 +08:00
|
|
|
|
2017-05-08 17:03:37 +08:00
|
|
|
%0(s64) = IMPLICIT_DEF
|
|
|
|
%1(s32) = IMPLICIT_DEF
|
|
|
|
%2(s16) = IMPLICIT_DEF
|
|
|
|
%3(s8) = IMPLICIT_DEF
|
|
|
|
%4(s64) = G_MUL %0, %0
|
|
|
|
%5(s32) = G_MUL %1, %1
|
|
|
|
%6(s16) = G_MUL %2, %2
|
|
|
|
%7(s8) = G_MUL %3, %3
|
|
|
|
RET 0
|
|
|
|
...
|
|
|
|
---
|
2017-03-03 16:06:46 +08:00
|
|
|
name: test_add_float
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
# CHECK-LABEL: name: test_add_float
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 2, class: vecr, preferred-register: '' }
|
2017-03-03 16:06:46 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %xmm0, %xmm1
|
|
|
|
|
|
|
|
%0(s32) = COPY %xmm0
|
|
|
|
%1(s32) = COPY %xmm1
|
|
|
|
%2(s32) = G_FADD %0, %1
|
|
|
|
%xmm0 = COPY %2(s32)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_add_double
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
# CHECK-LABEL: name: test_add_double
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 2, class: vecr, preferred-register: '' }
|
2017-03-03 16:06:46 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %xmm0, %xmm1
|
|
|
|
|
|
|
|
%0(s64) = COPY %xmm0
|
|
|
|
%1(s64) = COPY %xmm1
|
|
|
|
%2(s64) = G_FADD %0, %1
|
|
|
|
%xmm0 = COPY %2(s64)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
2017-06-27 15:01:54 +08:00
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_fsub_float
|
|
|
|
# CHECK-LABEL: name: test_fsub_float
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 4, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 6, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 7, class: vecr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
- { id: 2, class: _, preferred-register: '' }
|
|
|
|
- { id: 3, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
%0(s32) = IMPLICIT_DEF
|
|
|
|
%2(s64) = IMPLICIT_DEF
|
|
|
|
%1(s32) = G_FSUB %0, %0
|
|
|
|
%3(s64) = G_FSUB %2, %2
|
|
|
|
RET 0
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_fmul_float
|
|
|
|
# CHECK-LABEL: name: test_fmul_float
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 4, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 6, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 7, class: vecr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
- { id: 2, class: _, preferred-register: '' }
|
|
|
|
- { id: 3, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
%0(s32) = IMPLICIT_DEF
|
|
|
|
%2(s64) = IMPLICIT_DEF
|
|
|
|
%1(s32) = G_FMUL %0, %0
|
|
|
|
%3(s64) = G_FMUL %2, %2
|
|
|
|
RET 0
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_fdiv_float
|
|
|
|
# CHECK-LABEL: name: test_fdiv_float
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 4, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 6, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 7, class: vecr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
- { id: 2, class: _, preferred-register: '' }
|
|
|
|
- { id: 3, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
%0(s32) = IMPLICIT_DEF
|
|
|
|
%2(s64) = IMPLICIT_DEF
|
|
|
|
%1(s32) = G_FDIV %0, %0
|
|
|
|
%3(s64) = G_FDIV %2, %2
|
|
|
|
RET 0
|
|
|
|
|
2017-03-03 16:06:46 +08:00
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_add_v4i32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
# CHECK-LABEL: name: test_add_v4i32
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 2, class: vecr, preferred-register: '' }
|
2017-03-03 16:06:46 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %xmm0, %xmm1
|
|
|
|
|
|
|
|
%0(<4 x s32>) = COPY %xmm0
|
|
|
|
%1(<4 x s32>) = COPY %xmm1
|
|
|
|
%2(<4 x s32>) = G_ADD %0, %1
|
|
|
|
%xmm0 = COPY %2(<4 x s32>)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_add_v4f32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
# CHECK-LABEL: name: test_add_v4f32
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 2, class: vecr, preferred-register: '' }
|
2017-03-03 16:06:46 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %xmm0, %xmm1
|
|
|
|
|
|
|
|
%0(<4 x s32>) = COPY %xmm0
|
|
|
|
%1(<4 x s32>) = COPY %xmm1
|
|
|
|
%2(<4 x s32>) = G_FADD %0, %1
|
|
|
|
%xmm0 = COPY %2(<4 x s32>)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
|
|
|
...
|
2017-03-23 23:25:57 +08:00
|
|
|
---
|
|
|
|
name: test_load_i8
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_load_i8
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi
|
|
|
|
|
|
|
|
%0(p0) = COPY %rdi
|
|
|
|
%1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
|
|
|
|
%al = COPY %1(s8)
|
|
|
|
RET 0, implicit %al
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_load_i16
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_load_i16
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi
|
|
|
|
|
|
|
|
%0(p0) = COPY %rdi
|
|
|
|
%1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
|
|
|
|
%ax = COPY %1(s16)
|
|
|
|
RET 0, implicit %ax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_load_i32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_load_i32
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi
|
|
|
|
|
|
|
|
%0(p0) = COPY %rdi
|
|
|
|
%1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
|
|
|
|
%eax = COPY %1(s32)
|
|
|
|
RET 0, implicit %eax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_load_i64
|
|
|
|
alignment: 4
|
|
|
|
exposesReturnsTwice: false
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_load_i64
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi
|
|
|
|
|
|
|
|
%0(p0) = COPY %rdi
|
|
|
|
%1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
|
|
|
|
%rax = COPY %1(s64)
|
|
|
|
RET 0, implicit %rax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_load_float
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_load_float
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi
|
|
|
|
|
|
|
|
%0(p0) = COPY %rdi
|
|
|
|
%1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
|
|
|
|
%xmm0 = COPY %1(s32)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_load_double
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_load_double
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi
|
|
|
|
|
|
|
|
%0(p0) = COPY %rdi
|
|
|
|
%1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
|
|
|
|
%xmm0 = COPY %1(s64)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_load_v4i32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_load_v4i32
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi
|
|
|
|
|
|
|
|
%0(p0) = COPY %rdi
|
|
|
|
%1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
|
|
|
|
%xmm0 = COPY %1(<4 x s32>)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_store_i32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_store_i32
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %edi, %rsi
|
|
|
|
|
|
|
|
%0(s32) = COPY %edi
|
|
|
|
%1(p0) = COPY %rsi
|
|
|
|
G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
|
|
|
|
%rax = COPY %1(p0)
|
|
|
|
RET 0, implicit %rax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_store_i64
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_store_i64
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi, %rsi
|
|
|
|
|
|
|
|
%0(s64) = COPY %rdi
|
|
|
|
%1(p0) = COPY %rsi
|
|
|
|
G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
|
|
|
|
%rax = COPY %1(p0)
|
|
|
|
RET 0, implicit %rax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_store_float
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_store_float
|
|
|
|
# CHECK: registers:
|
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
|
|
|
|
2017-06-06 16:16:19 +08:00
|
|
|
# FAST-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# FAST-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
|
|
|
|
2017-06-06 16:16:19 +08:00
|
|
|
# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi, %xmm0
|
|
|
|
|
|
|
|
%0(s32) = COPY %xmm0
|
|
|
|
%1(p0) = COPY %rdi
|
2017-10-25 02:04:54 +08:00
|
|
|
; CHECK: %1:gpr(p0) = COPY %rdi
|
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
|
|
|
|
2017-10-25 02:04:54 +08:00
|
|
|
; FAST-NEXT: %2:gpr(s32) = COPY %0(s32)
|
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
|
|
|
; FAST-NEXT: G_STORE %2(s32), %1(p0) :: (store 4 into %ir.p1)
|
|
|
|
|
|
|
|
; GREEDY-NEXT: G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
|
|
|
|
|
2017-03-23 23:25:57 +08:00
|
|
|
G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
|
|
|
|
%rax = COPY %1(p0)
|
|
|
|
RET 0, implicit %rax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_store_double
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
selected: false
|
|
|
|
# CHECK-LABEL: name: test_store_double
|
|
|
|
# CHECK: registers:
|
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
|
|
|
|
2017-06-06 16:16:19 +08:00
|
|
|
# FAST-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# FAST-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
|
|
|
|
2017-06-06 16:16:19 +08:00
|
|
|
# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
2017-03-23 23:25:57 +08:00
|
|
|
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi, %xmm0
|
|
|
|
|
|
|
|
%0(s64) = COPY %xmm0
|
|
|
|
%1(p0) = COPY %rdi
|
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
|
|
|
|
2017-10-25 02:04:54 +08:00
|
|
|
; CHECK: %1:gpr(p0) = COPY %rdi
|
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
|
|
|
|
2017-10-25 02:04:54 +08:00
|
|
|
; FAST-NEXT: %2:gpr(s64) = COPY %0(s64)
|
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary:
G_LOAD/G_STORE, add alternative RegisterBank mapping.
For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank.
Reviewers: zvi, rovka, qcolombet, ab
Reviewed By: zvi
Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank
Differential Revision: https://reviews.llvm.org/D30979
llvm-svn: 298907
2017-03-28 17:35:06 +08:00
|
|
|
; FAST-NEXT: G_STORE %2(s64), %1(p0) :: (store 8 into %ir.p1)
|
|
|
|
|
|
|
|
; GREEDY-NEXT: G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
|
|
|
|
|
2017-03-23 23:25:57 +08:00
|
|
|
G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
|
|
|
|
%rax = COPY %1(p0)
|
|
|
|
RET 0, implicit %rax
|
|
|
|
|
|
|
|
...
|
2017-04-12 20:54:54 +08:00
|
|
|
---
|
|
|
|
name: constInt_check
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
# CHECK-LABEL: name: constInt_check
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
2017-04-12 20:54:54 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
- { id: 3, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.0 (%ir-block.0):
|
|
|
|
%0(s8) = G_CONSTANT i8 8
|
|
|
|
%1(s16) = G_CONSTANT i16 16
|
|
|
|
%2(s32) = G_CONSTANT i32 32
|
|
|
|
%3(s64) = G_CONSTANT i64 64
|
|
|
|
RET 0
|
2017-03-03 16:06:46 +08:00
|
|
|
|
2017-04-12 20:54:54 +08:00
|
|
|
...
|
2017-04-19 19:34:59 +08:00
|
|
|
---
|
|
|
|
name: trunc_check
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
# CHECK-LABEL: name: trunc_check
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
2017-04-19 19:34:59 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
- { id: 3, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.0 (%ir-block.0):
|
|
|
|
%0(s32) = IMPLICIT_DEF
|
|
|
|
%1(s1) = G_TRUNC %0(s32)
|
|
|
|
%2(s8) = G_TRUNC %0(s32)
|
|
|
|
%3(s16) = G_TRUNC %0(s32)
|
|
|
|
RET 0
|
|
|
|
|
|
|
|
...
|
2017-05-08 17:40:43 +08:00
|
|
|
---
|
|
|
|
name: test_gep
|
|
|
|
legalized: true
|
|
|
|
# CHECK-LABEL: name: test_gep
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
|
2017-05-08 17:40:43 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
- { id: 3, class: _ }
|
|
|
|
- { id: 4, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.0 (%ir-block.0):
|
|
|
|
%0(p0) = IMPLICIT_DEF
|
|
|
|
%1(s32) = G_CONSTANT i32 20
|
|
|
|
%2(p0) = G_GEP %0, %1(s32)
|
|
|
|
%3(s64) = G_CONSTANT i64 20
|
|
|
|
%4(p0) = G_GEP %0, %3(s64)
|
|
|
|
RET 0
|
|
|
|
|
|
|
|
...
|
2017-05-11 15:17:40 +08:00
|
|
|
---
|
|
|
|
name: test_icmp_eq_i8
|
|
|
|
# CHECK-LABEL: name: test_icmp_eq_i8
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
2017-05-11 15:17:40 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %edi, %esi
|
|
|
|
|
2017-09-17 16:30:42 +08:00
|
|
|
%0(s8) = COPY %dil
|
|
|
|
%1(s8) = COPY %sil
|
2017-05-11 15:17:40 +08:00
|
|
|
%2(s1) = G_ICMP intpred(eq), %0(s8), %1
|
|
|
|
%al = COPY %2(s1)
|
|
|
|
RET 0, implicit %al
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_icmp_eq_i16
|
|
|
|
# CHECK-LABEL: name: test_icmp_eq_i16
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
2017-05-11 15:17:40 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %edi, %esi
|
|
|
|
|
2017-09-17 16:30:42 +08:00
|
|
|
%0(s16) = COPY %di
|
|
|
|
%1(s16) = COPY %si
|
2017-05-11 15:17:40 +08:00
|
|
|
%2(s1) = G_ICMP intpred(eq), %0(s16), %1
|
|
|
|
%al = COPY %2(s1)
|
|
|
|
RET 0, implicit %al
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_icmp_eq_i32
|
|
|
|
# CHECK-LABEL: name: test_icmp_eq_i32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
2017-05-11 15:17:40 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %edi, %esi
|
|
|
|
|
|
|
|
%0(s32) = COPY %edi
|
|
|
|
%1(s32) = COPY %esi
|
|
|
|
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
|
|
|
|
%al = COPY %2(s1)
|
|
|
|
RET 0, implicit %al
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_icmp_eq_i64
|
|
|
|
# CHECK-LABEL: name: test_icmp_eq_i64
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
2017-06-06 16:16:19 +08:00
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
2017-05-11 15:17:40 +08:00
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
- { id: 2, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %rdi, %rsi
|
|
|
|
|
|
|
|
%0(s64) = COPY %rdi
|
|
|
|
%1(s64) = COPY %rsi
|
|
|
|
%2(s1) = G_ICMP intpred(eq), %0(s64), %1
|
|
|
|
%al = COPY %2(s1)
|
|
|
|
RET 0, implicit %al
|
|
|
|
|
|
|
|
...
|
2017-06-28 19:39:04 +08:00
|
|
|
---
|
|
|
|
name: test_xor_i8
|
|
|
|
# CHECK-LABEL: name: test_xor_i8
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
%0(s8) = IMPLICIT_DEF
|
|
|
|
%1(s8) = G_XOR %0, %0
|
|
|
|
%al = COPY %1(s8)
|
|
|
|
RET 0, implicit %al
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_or_i16
|
|
|
|
# CHECK-LABEL: name: test_or_i16
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
%0(s16) = IMPLICIT_DEF
|
|
|
|
%1(s16) = G_OR %0, %0
|
|
|
|
%ax = COPY %1(s16)
|
|
|
|
RET 0, implicit %ax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_and_i32
|
|
|
|
# CHECK-LABEL: name: test_and_i32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
%0(s32) = IMPLICIT_DEF
|
|
|
|
%1(s32) = G_AND %0, %0
|
|
|
|
%eax = COPY %1(s32)
|
|
|
|
RET 0, implicit %eax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_and_i64
|
|
|
|
# CHECK-LABEL: name: test_and_i64
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
%0(s64) = IMPLICIT_DEF
|
|
|
|
%1(s64) = G_AND %0, %0
|
|
|
|
%rax = COPY %1(s64)
|
|
|
|
RET 0, implicit %rax
|
|
|
|
|
|
|
|
...
|
2017-07-02 16:58:29 +08:00
|
|
|
---
|
|
|
|
name: test_global_ptrv
|
|
|
|
# CHECK-LABEL: name: test_global_ptrv
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
2017-10-25 02:04:54 +08:00
|
|
|
# CHECK: %0:gpr(p0) = G_GLOBAL_VALUE @g_int
|
2017-07-02 16:58:29 +08:00
|
|
|
# CHECK-NEXT: %rax = COPY %0(p0)
|
|
|
|
# CHECK-NEXT: RET 0, implicit %rax
|
|
|
|
body: |
|
|
|
|
bb.1.entry:
|
|
|
|
%0(p0) = G_GLOBAL_VALUE @g_int
|
|
|
|
%rax = COPY %0(p0)
|
|
|
|
RET 0, implicit %rax
|
|
|
|
|
|
|
|
...
|
2017-08-24 15:06:27 +08:00
|
|
|
---
|
|
|
|
name: test_undef
|
|
|
|
# CHECK-LABEL: name: test_undef
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
2017-10-25 02:04:54 +08:00
|
|
|
# CHECK: %0:gpr(s8) = G_IMPLICIT_DEF
|
2017-08-24 15:06:27 +08:00
|
|
|
# CHECK-NEXT: %al = COPY %0(s8)
|
|
|
|
# CHECK-NEXT: RET 0, implicit %al
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
%0(s8) = G_IMPLICIT_DEF
|
|
|
|
%al = COPY %0(s8)
|
|
|
|
RET 0, implicit %al
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_undef2
|
|
|
|
# CHECK-LABEL: name: test_undef2
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
- { id: 2, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
2017-10-25 02:04:54 +08:00
|
|
|
# CHECK: %0:gpr(s8) = COPY %dil
|
|
|
|
# CHECK-NEXT: %1:gpr(s8) = G_IMPLICIT_DEF
|
|
|
|
# CHECK-NEXT: %2:gpr(s8) = G_ADD %0, %1
|
2017-08-24 15:06:27 +08:00
|
|
|
# CHECK-NEXT: %al = COPY %2(s8)
|
|
|
|
# CHECK-NEXT: RET 0, implicit %al
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %edi
|
|
|
|
|
2017-09-17 16:30:42 +08:00
|
|
|
%0(s8) = COPY %dil
|
2017-08-24 15:06:27 +08:00
|
|
|
%1(s8) = G_IMPLICIT_DEF
|
|
|
|
%2(s8) = G_ADD %0, %1
|
|
|
|
%al = COPY %2(s8)
|
|
|
|
RET 0, implicit %al
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_undef3
|
|
|
|
# CHECK-LABEL: name: test_undef3
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
2017-10-25 02:04:54 +08:00
|
|
|
# CHECK: %0:gpr(s32) = G_IMPLICIT_DEF
|
2017-08-24 15:06:27 +08:00
|
|
|
# CHECK-NEXT: %xmm0 = COPY %0(s32)
|
|
|
|
# CHECK-NEXT: RET 0, implicit %xmm0
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
%0(s32) = G_IMPLICIT_DEF
|
|
|
|
%xmm0 = COPY %0(s32)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_undef4
|
|
|
|
# CHECK-LABEL: name: test_undef4
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
- { id: 2, class: _, preferred-register: '' }
|
|
|
|
liveins:
|
|
|
|
fixedStack:
|
|
|
|
stack:
|
|
|
|
constants:
|
2017-10-25 02:04:54 +08:00
|
|
|
# CHECK: %0:vecr(s32) = COPY %xmm0
|
|
|
|
# CHECK-NEXT: %1:gpr(s32) = G_IMPLICIT_DEF
|
|
|
|
# CHECK-NEXT: %3:vecr(s32) = COPY %1(s32)
|
|
|
|
# CHECK-NEXT: %2:vecr(s32) = G_FADD %0, %3
|
2017-08-24 15:06:27 +08:00
|
|
|
# CHECK-NEXT: %xmm0 = COPY %2(s32)
|
|
|
|
# CHECK-NEXT: RET 0, implicit %xmm0
|
|
|
|
body: |
|
|
|
|
bb.1 (%ir-block.0):
|
|
|
|
liveins: %xmm0
|
|
|
|
|
|
|
|
%0(s32) = COPY %xmm0
|
|
|
|
%1(s32) = G_IMPLICIT_DEF
|
|
|
|
%2(s32) = G_FADD %0, %1
|
|
|
|
%xmm0 = COPY %2(s32)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
|
|
|
...
|
2017-09-04 17:06:45 +08:00
|
|
|
---
|
|
|
|
name: test_i32
|
|
|
|
# CHECK-LABEL: name: test_i32
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 5, class: gpr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
- { id: 2, class: _, preferred-register: '' }
|
|
|
|
- { id: 3, class: _, preferred-register: '' }
|
|
|
|
- { id: 4, class: _, preferred-register: '' }
|
|
|
|
- { id: 5, class: _, preferred-register: '' }
|
|
|
|
# CHECK: bb.3.cond.end:
|
2017-10-25 02:04:54 +08:00
|
|
|
# CHECK-NEXT: %5:gpr(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
|
2017-09-04 17:06:45 +08:00
|
|
|
# CHECK-NEXT: %eax = COPY %5(s32)
|
|
|
|
# CHECK-NEXT: RET 0, implicit %eax
|
|
|
|
body: |
|
|
|
|
bb.0.entry:
|
|
|
|
successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
|
|
|
|
liveins: %edi, %edx, %esi
|
|
|
|
|
|
|
|
%0(s32) = COPY %edi
|
|
|
|
%1(s32) = COPY %esi
|
|
|
|
%2(s32) = COPY %edx
|
|
|
|
%3(s32) = G_CONSTANT i32 0
|
|
|
|
%4(s1) = G_ICMP intpred(sgt), %0(s32), %3
|
|
|
|
G_BRCOND %4(s1), %bb.1.cond.true
|
|
|
|
G_BR %bb.2.cond.false
|
2017-06-28 19:39:04 +08:00
|
|
|
|
2017-09-04 17:06:45 +08:00
|
|
|
bb.1.cond.true:
|
|
|
|
successors: %bb.3.cond.end(0x80000000)
|
|
|
|
|
|
|
|
G_BR %bb.3.cond.end
|
|
|
|
|
|
|
|
bb.2.cond.false:
|
|
|
|
successors: %bb.3.cond.end(0x80000000)
|
|
|
|
|
|
|
|
bb.3.cond.end:
|
|
|
|
%5(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
|
|
|
|
%eax = COPY %5(s32)
|
|
|
|
RET 0, implicit %eax
|
|
|
|
|
|
|
|
...
|
|
|
|
---
|
|
|
|
name: test_float
|
|
|
|
# CHECK-LABEL: name: test_float
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
tracksRegLiveness: true
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 2, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
- { id: 2, class: _, preferred-register: '' }
|
|
|
|
- { id: 3, class: _, preferred-register: '' }
|
|
|
|
- { id: 4, class: _, preferred-register: '' }
|
|
|
|
- { id: 5, class: _, preferred-register: '' }
|
|
|
|
# CHECK: bb.3.cond.end:
|
2017-10-25 02:04:54 +08:00
|
|
|
# CHECK-NEXT: %5:vecr(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
|
2017-09-04 17:06:45 +08:00
|
|
|
# CHECK-NEXT: %xmm0 = COPY %5(s32)
|
|
|
|
# CHECK-NEXT: RET 0, implicit %xmm0
|
|
|
|
body: |
|
|
|
|
bb.0.entry:
|
|
|
|
successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
|
|
|
|
liveins: %edi, %xmm0, %xmm1
|
|
|
|
|
|
|
|
%0(s32) = COPY %edi
|
|
|
|
%1(s32) = COPY %xmm0
|
|
|
|
%2(s32) = COPY %xmm1
|
|
|
|
%3(s32) = G_CONSTANT i32 0
|
|
|
|
%4(s1) = G_ICMP intpred(sgt), %0(s32), %3
|
|
|
|
G_BRCOND %4(s1), %bb.1.cond.true
|
|
|
|
G_BR %bb.2.cond.false
|
|
|
|
|
|
|
|
bb.1.cond.true:
|
|
|
|
successors: %bb.3.cond.end(0x80000000)
|
|
|
|
|
|
|
|
G_BR %bb.3.cond.end
|
|
|
|
|
|
|
|
bb.2.cond.false:
|
|
|
|
successors: %bb.3.cond.end(0x80000000)
|
|
|
|
|
|
|
|
bb.3.cond.end:
|
|
|
|
%5(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
|
|
|
|
%xmm0 = COPY %5(s32)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
|
|
|
...
|
2017-09-13 17:05:23 +08:00
|
|
|
---
|
|
|
|
name: test_fpext
|
|
|
|
# CHECK-LABEL: name: test_fpext
|
|
|
|
alignment: 4
|
|
|
|
legalized: true
|
|
|
|
regBankSelected: false
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _, preferred-register: '' }
|
|
|
|
- { id: 1, class: _, preferred-register: '' }
|
|
|
|
body: |
|
|
|
|
bb.1.entry:
|
|
|
|
liveins: %xmm0
|
|
|
|
|
|
|
|
%0(s32) = COPY %xmm0
|
|
|
|
%1(s64) = G_FPEXT %0(s32)
|
|
|
|
%xmm0 = COPY %1(s64)
|
|
|
|
RET 0, implicit %xmm0
|
|
|
|
|
|
|
|
...
|
2017-09-17 16:08:13 +08:00
|
|
|
---
|
|
|
|
name: test_fconstant
|
|
|
|
# ALL-LABEL: name: test_fconstant
|
|
|
|
legalized: true
|
|
|
|
# CHECK: registers:
|
|
|
|
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
|
|
|
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
|
|
|
|
registers:
|
|
|
|
- { id: 0, class: _ }
|
|
|
|
- { id: 1, class: _ }
|
|
|
|
body: |
|
|
|
|
bb.0:
|
|
|
|
%0(s32) = G_FCONSTANT float 1.0
|
|
|
|
%1(s64) = G_FCONSTANT double 2.0
|
|
|
|
...
|