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llvm-project/llvm/test/CodeGen/RISCV/mul.ll

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[RISCV] Support and tests for a variety of additional LLVM IR constructs Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases: * Improved sext/zext/trunc support * Support for setcc variants that don't map directly to RISC-V instructions * Lowering mul, and hence support for external symbols * addc, adde, subc, sube * mulhs, srem, mulhu, urem, udiv, sdiv * {srl,sra,shl}_parts * brind * br_jt * bswap, ctlz, cttz, ctpop * rotl, rotr * BlockAddress operands Differential Revision: https://reviews.llvm.org/D29938 llvm-svn: 318737
2017-11-21 16:11:03 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
define i32 @square(i32 %a) {
; RV32I-LABEL: square:
; RV32I: # BB#0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a1, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
; RV32I-NEXT: addi a1, a0, 0
; RV32I-NEXT: jalr ra, a2, 0
; RV32I-NEXT: lw ra, 12(s0)
; RV32I-NEXT: jalr zero, ra, 0
%1 = mul i32 %a, %a
ret i32 %1
}
define i32 @mul(i32 %a, i32 %b) {
; RV32I-LABEL: mul:
; RV32I: # BB#0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a2, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr ra, a2, 0
; RV32I-NEXT: lw ra, 12(s0)
; RV32I-NEXT: jalr zero, ra, 0
%1 = mul i32 %a, %b
ret i32 %1
}
define i32 @mul_constant(i32 %a) {
; RV32I-LABEL: mul_constant:
; RV32I: # BB#0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a1, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
; RV32I-NEXT: addi a1, zero, 5
; RV32I-NEXT: jalr ra, a2, 0
; RV32I-NEXT: lw ra, 12(s0)
; RV32I-NEXT: jalr zero, ra, 0
%1 = mul i32 %a, 5
ret i32 %1
}
define i32 @mul_pow2(i32 %a) {
; RV32I-LABEL: mul_pow2:
; RV32I: # BB#0:
; RV32I-NEXT: slli a0, a0, 3
; RV32I-NEXT: jalr zero, ra, 0
%1 = mul i32 %a, 8
ret i32 %1
}
define i64 @mul64(i64 %a, i64 %b) {
; RV32I-LABEL: mul64:
; RV32I: # BB#0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a4, %hi(__muldi3)
; RV32I-NEXT: addi a4, a4, %lo(__muldi3)
; RV32I-NEXT: jalr ra, a4, 0
; RV32I-NEXT: lw ra, 12(s0)
; RV32I-NEXT: jalr zero, ra, 0
%1 = mul i64 %a, %b
ret i64 %1
}
define i64 @mul64_constant(i64 %a) {
; RV32I-LABEL: mul64_constant:
; RV32I: # BB#0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a2, %hi(__muldi3)
; RV32I-NEXT: addi a4, a2, %lo(__muldi3)
; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: addi a3, zero, 0
; RV32I-NEXT: jalr ra, a4, 0
; RV32I-NEXT: lw ra, 12(s0)
; RV32I-NEXT: jalr zero, ra, 0
%1 = mul i64 %a, 5
ret i64 %1
}