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llvm-project/llvm/test/CodeGen/RISCV/bare-select.ll

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[RISCV] Implement lowering of ISD::SELECT Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and ultimately the integer RISC-V conditional branch instructions), we choose to expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch will be created in the case where an ISD::SELECT condition value is created by an ISD::SETCC node, which operates on XLen types. Other datatypes such as floating point don't have conditional branch instructions, and lowering ISD::SELECT allows more flexibility for handling these cases. Differential Revision: https://reviews.llvm.org/D29937 llvm-svn: 318735
2017-11-21 15:51:32 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
; RV32I-LABEL: bare_select:
; RV32I: # BB#0:
; RV32I-NEXT: andi a0, a0, 1
[RISCV] Use register X0 (ZERO) for constant 0 The obvious approach of defining a pattern like the one below actually doesn't work: `def : Pat<(i32 0), (i32 X0)>;` As was noted when Lanai made this change (https://reviews.llvm.org/rL288215), attempting to handle the constant 0 in tablegen leads to assertions due to a physical register being used where a virtual register is expected. llvm-svn: 318738
2017-11-21 16:23:08 +08:00
; RV32I-NEXT: bne a0, zero, .LBB0_2
[RISCV] Implement lowering of ISD::SELECT Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and ultimately the integer RISC-V conditional branch instructions), we choose to expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch will be created in the case where an ISD::SELECT condition value is created by an ISD::SETCC node, which operates on XLen types. Other datatypes such as floating point don't have conditional branch instructions, and lowering ISD::SELECT allows more flexibility for handling these cases. Differential Revision: https://reviews.llvm.org/D29937 llvm-svn: 318735
2017-11-21 15:51:32 +08:00
; RV32I-NEXT: # BB#1:
; RV32I-NEXT: addi a1, a2, 0
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: addi a0, a1, 0
; RV32I-NEXT: jalr zero, ra, 0
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
}